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authordiego <diego@b3059339-0415-0410-9bf9-f77b7e298cf2>2010-04-12 10:56:17 +0000
committerdiego <diego@b3059339-0415-0410-9bf9-f77b7e298cf2>2010-04-12 10:56:17 +0000
commit7573c29480850d715e2f06cae70f252573098123 (patch)
treea5a2f498ad3a19806957e1d7e01f913c1650b33d /drivers
parent86ea8d4f4abf23672516fa0ca3378aa19c44bf2c (diff)
downloadmpv-7573c29480850d715e2f06cae70f252573098123.tar.bz2
mpv-7573c29480850d715e2f06cae70f252573098123.tar.xz
the great MPlayer tab removal: part I
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@31032 b3059339-0415-0410-9bf9-f77b7e298cf2
Diffstat (limited to 'drivers')
-rw-r--r--drivers/3dfx.h288
-rw-r--r--drivers/README.Ati8
-rw-r--r--drivers/README.Matrox34
-rw-r--r--drivers/generic_math.h2
-rw-r--r--drivers/hacking.ati240
-rw-r--r--drivers/mga_vid.c2324
-rw-r--r--drivers/mga_vid_test.c326
-rw-r--r--drivers/radeon.h3660
8 files changed, 3436 insertions, 3446 deletions
diff --git a/drivers/3dfx.h b/drivers/3dfx.h
index 0cabc492ce..159327d482 100644
--- a/drivers/3dfx.h
+++ b/drivers/3dfx.h
@@ -29,10 +29,10 @@
#define VOODOO_YUV_PLANE_OFFSET ((unsigned long int)0x0C00000)
#define VOODOO_BLT_FORMAT_YUYV (8<<16)
-#define VOODOO_BLT_FORMAT_UYVY (9<<16)
+#define VOODOO_BLT_FORMAT_UYVY (9<<16)
#define VOODOO_BLT_FORMAT_16 (3<<16)
-#define VOODOO_BLT_FORMAT_24 (4<<16)
-#define VOODOO_BLT_FORMAT_32 (5<<16)
+#define VOODOO_BLT_FORMAT_24 (4<<16)
+#define VOODOO_BLT_FORMAT_32 (5<<16)
#define VOODOO_YUV_STRIDE (1024>>2)
@@ -164,95 +164,95 @@ typedef struct voodoo_yuv_fb_t voodoo_yuv_fb;
*/
#ifndef PCI_DEVICE_ID_3DFX_VOODOO5
-#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009
+#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009
#endif
/* membase0 register offsets */
-#define STATUS 0x00
-#define PCIINIT0 0x04
-#define SIPMONITOR 0x08
-#define LFBMEMORYCONFIG 0x0c
-#define MISCINIT0 0x10
-#define MISCINIT1 0x14
-#define DRAMINIT0 0x18
-#define DRAMINIT1 0x1c
-#define AGPINIT 0x20
-#define TMUGBEINIT 0x24
-#define VGAINIT0 0x28
-#define VGAINIT1 0x2c
-#define DRAMCOMMAND 0x30
-#define DRAMDATA 0x34
-/* reserved 0x38 */
-/* reserved 0x3c */
-#define PLLCTRL0 0x40
-#define PLLCTRL1 0x44
-#define PLLCTRL2 0x48
-#define DACMODE 0x4c
-#define DACADDR 0x50
-#define DACDATA 0x54
-#define RGBMAXDELTA 0x58
-#define VIDPROCCFG 0x5c
-#define HWCURPATADDR 0x60
-#define HWCURLOC 0x64
-#define HWCURC0 0x68
-#define HWCURC1 0x6c
-#define VIDINFORMAT 0x70
-#define VIDINSTATUS 0x74
-#define VIDSERPARPORT 0x78
-#define VIDINXDELTA 0x7c
-#define VIDININITERR 0x80
-#define VIDINYDELTA 0x84
-#define VIDPIXBUFTHOLD 0x88
-#define VIDCHRMIN 0x8c
-#define VIDCHRMAX 0x90
-#define VIDCURLIN 0x94
-#define VIDSCREENSIZE 0x98
-#define VIDOVRSTARTCRD 0x9c
-#define VIDOVRENDCRD 0xa0
-#define VIDOVRDUDX 0xa4
-#define VIDOVRDUDXOFF 0xa8
-#define VIDOVRDVDY 0xac
+#define STATUS 0x00
+#define PCIINIT0 0x04
+#define SIPMONITOR 0x08
+#define LFBMEMORYCONFIG 0x0c
+#define MISCINIT0 0x10
+#define MISCINIT1 0x14
+#define DRAMINIT0 0x18
+#define DRAMINIT1 0x1c
+#define AGPINIT 0x20
+#define TMUGBEINIT 0x24
+#define VGAINIT0 0x28
+#define VGAINIT1 0x2c
+#define DRAMCOMMAND 0x30
+#define DRAMDATA 0x34
+/* reserved 0x38 */
+/* reserved 0x3c */
+#define PLLCTRL0 0x40
+#define PLLCTRL1 0x44
+#define PLLCTRL2 0x48
+#define DACMODE 0x4c
+#define DACADDR 0x50
+#define DACDATA 0x54
+#define RGBMAXDELTA 0x58
+#define VIDPROCCFG 0x5c
+#define HWCURPATADDR 0x60
+#define HWCURLOC 0x64
+#define HWCURC0 0x68
+#define HWCURC1 0x6c
+#define VIDINFORMAT 0x70
+#define VIDINSTATUS 0x74
+#define VIDSERPARPORT 0x78
+#define VIDINXDELTA 0x7c
+#define VIDININITERR 0x80
+#define VIDINYDELTA 0x84
+#define VIDPIXBUFTHOLD 0x88
+#define VIDCHRMIN 0x8c
+#define VIDCHRMAX 0x90
+#define VIDCURLIN 0x94
+#define VIDSCREENSIZE 0x98
+#define VIDOVRSTARTCRD 0x9c
+#define VIDOVRENDCRD 0xa0
+#define VIDOVRDUDX 0xa4
+#define VIDOVRDUDXOFF 0xa8
+#define VIDOVRDVDY 0xac
/* ... */
-#define VIDOVRDVDYOFF 0xe0
-#define VIDDESKSTART 0xe4
-#define VIDDESKSTRIDE 0xe8
-#define VIDINADDR0 0xec
-#define VIDINADDR1 0xf0
-#define VIDINADDR2 0xf4
-#define VIDINSTRIDE 0xf8
-#define VIDCUROVRSTART 0xfc
-
-#define INTCTRL (0x00100000 + 0x04)
-#define CLIP0MIN (0x00100000 + 0x08)
-#define CLIP0MAX (0x00100000 + 0x0c)
-#define DSTBASE (0x00100000 + 0x10)
-#define DSTFORMAT (0x00100000 + 0x14)
-#define SRCCOLORKEYMIN (0x00100000 + 0x18)
-#define SRCCOLORKEYMAX (0x00100000 + 0x1c)
-#define DSTCOLORKEYMIN (0x00100000 + 0x20)
-#define DSTCOLORKEYMAX (0x00100000 + 0x24)
-#define ROP123 (0x00100000 + 0x30)
-#define SRCBASE (0x00100000 + 0x34)
-#define COMMANDEXTRA_2D (0x00100000 + 0x38)
-#define CLIP1MIN (0x00100000 + 0x4c)
-#define CLIP1MAX (0x00100000 + 0x50)
-#define SRCFORMAT (0x00100000 + 0x54)
-#define SRCSIZE (0x00100000 + 0x58)
-#define SRCXY (0x00100000 + 0x5c)
-#define COLORBACK (0x00100000 + 0x60)
-#define COLORFORE (0x00100000 + 0x64)
-#define DSTSIZE (0x00100000 + 0x68)
-#define DSTXY (0x00100000 + 0x6c)
-#define COMMAND_2D (0x00100000 + 0x70)
-#define LAUNCH_2D (0x00100000 + 0x80)
-
-#define COMMAND_3D (0x00200000 + 0x120)
-
-#define SWAPBUFCMD (0x00200000 + 0x128)
-#define SWAPPENDING (0x00200000 + 0x24C)
-#define LEFTOVBUF (0x00200000 + 0x250)
-#define RIGHTOVBUF (0x00200000 + 0x254)
-#define FBISWAPBUFHIST (0x00200000 + 0x258)
+#define VIDOVRDVDYOFF 0xe0
+#define VIDDESKSTART 0xe4
+#define VIDDESKSTRIDE 0xe8
+#define VIDINADDR0 0xec
+#define VIDINADDR1 0xf0
+#define VIDINADDR2 0xf4
+#define VIDINSTRIDE 0xf8
+#define VIDCUROVRSTART 0xfc
+
+#define INTCTRL (0x00100000 + 0x04)
+#define CLIP0MIN (0x00100000 + 0x08)
+#define CLIP0MAX (0x00100000 + 0x0c)
+#define DSTBASE (0x00100000 + 0x10)
+#define DSTFORMAT (0x00100000 + 0x14)
+#define SRCCOLORKEYMIN (0x00100000 + 0x18)
+#define SRCCOLORKEYMAX (0x00100000 + 0x1c)
+#define DSTCOLORKEYMIN (0x00100000 + 0x20)
+#define DSTCOLORKEYMAX (0x00100000 + 0x24)
+#define ROP123 (0x00100000 + 0x30)
+#define SRCBASE (0x00100000 + 0x34)
+#define COMMANDEXTRA_2D (0x00100000 + 0x38)
+#define CLIP1MIN (0x00100000 + 0x4c)
+#define CLIP1MAX (0x00100000 + 0x50)
+#define SRCFORMAT (0x00100000 + 0x54)
+#define SRCSIZE (0x00100000 + 0x58)
+#define SRCXY (0x00100000 + 0x5c)
+#define COLORBACK (0x00100000 + 0x60)
+#define COLORFORE (0x00100000 + 0x64)
+#define DSTSIZE (0x00100000 + 0x68)
+#define DSTXY (0x00100000 + 0x6c)
+#define COMMAND_2D (0x00100000 + 0x70)
+#define LAUNCH_2D (0x00100000 + 0x80)
+
+#define COMMAND_3D (0x00200000 + 0x120)
+
+#define SWAPBUFCMD (0x00200000 + 0x128)
+#define SWAPPENDING (0x00200000 + 0x24C)
+#define LEFTOVBUF (0x00200000 + 0x250)
+#define RIGHTOVBUF (0x00200000 + 0x254)
+#define FBISWAPBUFHIST (0x00200000 + 0x258)
/* register bitfields (not all, only as needed) */
@@ -268,44 +268,44 @@ typedef struct voodoo_yuv_fb_t voodoo_yuv_fb;
#define AUTOINC_DSTY BIT(11)
-#define COMMAND_2D_S2S_BITBLT 0x01 // screen to screen
-#define COMMAND_2D_S2S_STRECH_BLT 0x02 // BLT + Strech
+#define COMMAND_2D_S2S_BITBLT 0x01 // screen to screen
+#define COMMAND_2D_S2S_STRECH_BLT 0x02 // BLT + Strech
#define COMMAND_2D_H2S_BITBLT 0x03 // host to screen
-#define COMMAND_2D_FILLRECT 0x05
-
-#define COMMAND_2D_DO_IMMED BIT(8) // Do it immediatly
-
-
-
-#define COMMAND_3D_NOP 0x00
-#define STATUS_RETRACE BIT(6)
-#define STATUS_BUSY BIT(9)
-#define MISCINIT1_CLUT_INV BIT(0)
-#define MISCINIT1_2DBLOCK_DIS BIT(15)
-#define DRAMINIT0_SGRAM_NUM BIT(26)
-#define DRAMINIT0_SGRAM_TYPE BIT(27)
-#define DRAMINIT1_MEM_SDRAM BIT(30)
-#define VGAINIT0_VGA_DISABLE BIT(0)
-#define VGAINIT0_EXT_TIMING BIT(1)
-#define VGAINIT0_8BIT_DAC BIT(2)
-#define VGAINIT0_EXT_ENABLE BIT(6)
-#define VGAINIT0_WAKEUP_3C3 BIT(8)
-#define VGAINIT0_LEGACY_DISABLE BIT(9)
-#define VGAINIT0_ALT_READBACK BIT(10)
-#define VGAINIT0_FAST_BLINK BIT(11)
-#define VGAINIT0_EXTSHIFTOUT BIT(12)
-#define VGAINIT0_DECODE_3C6 BIT(13)
-#define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22)
-#define VGAINIT1_MASK 0x1fffff
-#define VIDCFG_VIDPROC_ENABLE BIT(0)
-#define VIDCFG_CURS_X11 BIT(1)
-#define VIDCFG_HALF_MODE BIT(4)
-#define VIDCFG_DESK_ENABLE BIT(7)
-#define VIDCFG_CLUT_BYPASS BIT(10)
-#define VIDCFG_2X BIT(26)
-#define VIDCFG_HWCURSOR_ENABLE BIT(27)
-#define VIDCFG_PIXFMT_SHIFT 18
-#define DACMODE_2X BIT(0)
+#define COMMAND_2D_FILLRECT 0x05
+
+#define COMMAND_2D_DO_IMMED BIT(8) // Do it immediatly
+
+
+
+#define COMMAND_3D_NOP 0x00
+#define STATUS_RETRACE BIT(6)
+#define STATUS_BUSY BIT(9)
+#define MISCINIT1_CLUT_INV BIT(0)
+#define MISCINIT1_2DBLOCK_DIS BIT(15)
+#define DRAMINIT0_SGRAM_NUM BIT(26)
+#define DRAMINIT0_SGRAM_TYPE BIT(27)
+#define DRAMINIT1_MEM_SDRAM BIT(30)
+#define VGAINIT0_VGA_DISABLE BIT(0)
+#define VGAINIT0_EXT_TIMING BIT(1)
+#define VGAINIT0_8BIT_DAC BIT(2)
+#define VGAINIT0_EXT_ENABLE BIT(6)
+#define VGAINIT0_WAKEUP_3C3 BIT(8)
+#define VGAINIT0_LEGACY_DISABLE BIT(9)
+#define VGAINIT0_ALT_READBACK BIT(10)
+#define VGAINIT0_FAST_BLINK BIT(11)
+#define VGAINIT0_EXTSHIFTOUT BIT(12)
+#define VGAINIT0_DECODE_3C6 BIT(13)
+#define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22)
+#define VGAINIT1_MASK 0x1fffff
+#define VIDCFG_VIDPROC_ENABLE BIT(0)
+#define VIDCFG_CURS_X11 BIT(1)
+#define VIDCFG_HALF_MODE BIT(4)
+#define VIDCFG_DESK_ENABLE BIT(7)
+#define VIDCFG_CLUT_BYPASS BIT(10)
+#define VIDCFG_2X BIT(26)
+#define VIDCFG_HWCURSOR_ENABLE BIT(27)
+#define VIDCFG_PIXFMT_SHIFT 18
+#define DACMODE_2X BIT(0)
/* AGP registers */
#define AGPREQSIZE (0x0080000 + 0x00)
@@ -332,35 +332,35 @@ typedef struct voodoo_yuv_fb_t voodoo_yuv_fb;
#define YUVSTRIDE (0x0080000 + 0x104)
/* VGA rubbish, need to change this for multihead support */
-#define MISC_W 0x3c2
-#define MISC_R 0x3cc
-#define SEQ_I 0x3c4
-#define SEQ_D 0x3c5
-#define CRT_I 0x3d4
-#define CRT_D 0x3d5
-#define ATT_IW 0x3c0
+#define MISC_W 0x3c2
+#define MISC_R 0x3cc
+#define SEQ_I 0x3c4
+#define SEQ_D 0x3c5
+#define CRT_I 0x3d4
+#define CRT_D 0x3d5
+#define ATT_IW 0x3c0
#define RAMDAC_R 0x3c7
#define RAMDAC_W 0x3c8
#define RAMDAC_D 0x3c9
-#define IS1_R 0x3da
-#define GRA_I 0x3ce
-#define GRA_D 0x3cf
+#define IS1_R 0x3da
+#define GRA_I 0x3ce
+#define GRA_D 0x3cf
#ifndef FB_ACCEL_3DFX_BANSHEE
#define FB_ACCEL_3DFX_BANSHEE 31
#endif
-#define TDFXF_HSYNC_ACT_HIGH 0x01
-#define TDFXF_HSYNC_ACT_LOW 0x02
-#define TDFXF_VSYNC_ACT_HIGH 0x04
-#define TDFXF_VSYNC_ACT_LOW 0x08
-#define TDFXF_LINE_DOUBLE 0x10
-#define TDFXF_VIDEO_ENABLE 0x20
+#define TDFXF_HSYNC_ACT_HIGH 0x01
+#define TDFXF_HSYNC_ACT_LOW 0x02
+#define TDFXF_VSYNC_ACT_HIGH 0x04
+#define TDFXF_VSYNC_ACT_LOW 0x08
+#define TDFXF_LINE_DOUBLE 0x10
+#define TDFXF_VIDEO_ENABLE 0x20
-#define TDFXF_HSYNC_MASK 0x03
-#define TDFXF_VSYNC_MASK 0x0c
+#define TDFXF_HSYNC_MASK 0x03
+#define TDFXF_VSYNC_MASK 0x0c
-#define XYREG(x,y) (((((unsigned long)y) & 0x1FFF) << 16) | (((unsigned long)x) & 0x1FFF))
+#define XYREG(x,y) (((((unsigned long)y) & 0x1FFF) << 16) | (((unsigned long)x) & 0x1FFF))
//#define TDFXFB_DEBUG
#ifdef TDFXFB_DEBUG
diff --git a/drivers/README.Ati b/drivers/README.Ati
index 640107f56c..077b6ffff2 100644
--- a/drivers/README.Ati
+++ b/drivers/README.Ati
@@ -1,5 +1,5 @@
- framebuffer driver for ATI Radeon chipset video boards
- ======================================================
+ framebuffer driver for ATI Radeon chipset video boards
+ ======================================================
These files are replacement for linux-2.4.x-ac.y drivers.
To use this driver you should have at least linux-2.4.5-ac.1
@@ -21,7 +21,7 @@ and at least '8bpp packed pixel support' compiled and installed as module.
Radeon video overlay
- ====================
+ ====================
It was designed for MPlayer and currently can be used only by MPlayer.
It's RGB-YUV BES for Radeon cards (althrough there is experimental
@@ -93,7 +93,7 @@ List of driver parameters:
~~~~~~~~~~~~~~~~~~~~~~~~~~
mtrr=1/0 Configures MTRR (if available), default = 1.
swap_fourcc=1/0 Performs byte swapping of passed fourcc.
- (It's required for compatibility with -vo mga.)
+ (It's required for compatibility with -vo mga.)
To know more about driver parameters execute:
modinfo radeon_vid
diff --git a/drivers/README.Matrox b/drivers/README.Matrox
index ae641ab452..48a37ed057 100644
--- a/drivers/README.Matrox
+++ b/drivers/README.Matrox
@@ -7,12 +7,12 @@ http://attila.kinali.ch/mga/
mga_vid - MGA G200/G400 YUV Overlay kernel module
- Author:
- Aaron Holtzman <aholtzma@ess.engr.uvic.ca>, Oct 1999
+ Author:
+ Aaron Holtzman <aholtzma@ess.engr.uvic.ca>, Oct 1999
- Contributions by:
- Fredrik Vraalsen <vraalsen@cs.uiuc.edu>
- Alan Cox <alan@lxorguk.ukuu.org.uk>
+ Contributions by:
+ Fredrik Vraalsen <vraalsen@cs.uiuc.edu>
+ Alan Cox <alan@lxorguk.ukuu.org.uk>
WARNING ----- WARNING
@@ -24,23 +24,23 @@ MAX to spout 6 inch flames. You have been warned.
What does this code do?
- mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550
- video scaler/overlay unit to perform YUV->RGB colorspace conversion
- and arbitrary video scaling.
+ mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550
+ video scaler/overlay unit to perform YUV->RGB colorspace conversion
+ and arbitrary video scaling.
- mga_vid is also a monster hack.
+ mga_vid is also a monster hack.
How does mga_vid work?
- This kernel module sets up the BES (backend scaler) with appropriate
- values based on parameters supplied via ioctl. It also maps a chunk of
- video memory into userspace via mmap. This memory is stolen from X
- (which may decide to write to it later). The application can then write
- image data directly to the framebuffer (if it knows the right padding,
- etc).
+ This kernel module sets up the BES (backend scaler) with appropriate
+ values based on parameters supplied via ioctl. It also maps a chunk of
+ video memory into userspace via mmap. This memory is stolen from X
+ (which may decide to write to it later). The application can then write
+ image data directly to the framebuffer (if it knows the right padding,
+ etc).
How do I know if mga_vid works on my system?
- There is a test application called mga_vid_test. This test code should
- draw some nice 256x256 images for you if all is working well.
+ There is a test application called mga_vid_test. This test code should
+ draw some nice 256x256 images for you if all is working well.
diff --git a/drivers/generic_math.h b/drivers/generic_math.h
index f606cce3d8..00a0e976f8 100644
--- a/drivers/generic_math.h
+++ b/drivers/generic_math.h
@@ -233,7 +233,7 @@ static gen_sincos_t g_sincos[201] = {
{ 3.141600e+00, -7.346410e-06, -1.000000e-00 }
};
-# define M_PI 3.14159265358979323846 /* pi */
+#define M_PI 3.14159265358979323846 /* pi */
static double inline gen_sin(double x)
{
diff --git a/drivers/hacking.ati b/drivers/hacking.ati
index 518c3a8f90..20c9bfa8ea 100644
--- a/drivers/hacking.ati
+++ b/drivers/hacking.ati
@@ -1,6 +1,6 @@
ATI chips hacking
=================
- Dedicated to ATI's hackers.
+ Dedicated to ATI's hackers.
Preface
~~~~~~~
@@ -11,20 +11,20 @@ This document doesn't include information about ATI AIW (All In Wonder) chips.
What are units on modern ATI chips:
DAC - (Digital to Analog Convertor) controls CRTC, LCD, DFP monitor's output
- Consists from:
- PLL - (Programable line length) registers
- CRTC - CRT controller
- LCD/DFP scaler
- surface control
+ Consists from:
+ PLL - (Programable line length) registers
+ CRTC - CRT controller
+ LCD/DFP scaler
+ surface control
DAC2 - controls CRTC, LCD, DFP monitor's output on second head
TVDAC - controls Composite Video and Super Video output ports
- Consists from:
- TV_PLL
- TV scaler & sync unit
- TV format convertor (PAL/NTSC)
+ Consists from:
+ TV_PLL
+ TV scaler & sync unit
+ TV format convertor (PAL/NTSC)
TVCAP - controls Video-In port
MPP - Miscellaneous peripheral port. (includes macrovision's filter - copy
- protection mechanism)
+ protection mechanism)
OV - Video overlay (YUV BES) (include subpictures, gamma correction and
adaptive deinterlacing)
CAP0 - Video capturing
@@ -61,100 +61,100 @@ of this question:
3. Mach32
4. Mach64.
- It's first chip which has support from side of open
- source drivers. Set of mach64 chips is:
- mach64GX (ATI888GX00)
- mach64CX (ATI888CX00)
- mach64CT (ATI264CT)
- mach64ET (ATI264ET)
- mach64VTA3 (ATI264VT)
- mach64VTA4 (ATI264VT)
- mach64VTB (ATI264VTB)
- mach64VT4 (ATI264VT4)
+ It's first chip which has support from side of open
+ source drivers. Set of mach64 chips is:
+ mach64GX (ATI888GX00)
+ mach64CX (ATI888CX00)
+ mach64CT (ATI264CT)
+ mach64ET (ATI264ET)
+ mach64VTA3 (ATI264VT)
+ mach64VTA4 (ATI264VT)
+ mach64VTB (ATI264VTB)
+ mach64VT4 (ATI264VT4)
5. 3D rage chips.
- It seems that these chips have fully compatible by GPU with Mach64
- which is extended by 3D possibilities. Set of 3D rage chips is:
- 3D RAGE (GT)
- 3D RAGE II+ (GTB)
- 3D RAGE IIC (PCI)
- 3D RAGE IIC (AGP)
- 3D RAGE LT
- 3D RAGE LT-G
- 3D RAGE PRO (BGA, AGP)
- 3D RAGE PRO (BGA, AGP, 1x only)
- 3D RAGE PRO (BGA, PCI)
- 3D RAGE PRO (PQFP, PCI)
- 3D RAGE PRO (PQFP, PCI, limited 3D)
- 3D RAGE (XL)
- 3D RAGE LT PRO (AGP)
- 3D RAGE LT PRO (PCI)
- 3D RAGE Mobility (PCI)
- 3D RAGE Mobility (AGP)
+ It seems that these chips have fully compatible by GPU with Mach64
+ which is extended by 3D possibilities. Set of 3D rage chips is:
+ 3D RAGE (GT)
+ 3D RAGE II+ (GTB)
+ 3D RAGE IIC (PCI)
+ 3D RAGE IIC (AGP)
+ 3D RAGE LT
+ 3D RAGE LT-G
+ 3D RAGE PRO (BGA, AGP)
+ 3D RAGE PRO (BGA, AGP, 1x only)
+ 3D RAGE PRO (BGA, PCI)
+ 3D RAGE PRO (PQFP, PCI)
+ 3D RAGE PRO (PQFP, PCI, limited 3D)
+ 3D RAGE (XL)
+ 3D RAGE LT PRO (AGP)
+ 3D RAGE LT PRO (PCI)
+ 3D RAGE Mobility (PCI)
+ 3D RAGE Mobility (AGP)
6. Rage128 chips.
- These chips have perfectly new GPU which supports memory mapped IO
- space for accelerating port access (It's main cause of incompatibility
- with mach64). Set of Rage128 chips is:
- Rage128 GL RE
- Rage128 GL RF
- Rage128 GL RG
- Rage128 GL RH
- Rage128 GL RI
- Rage128 VR RK
- Rage128 VR RL
- Rage128 VR RM
- Rage128 VR RN
- Rage128 VR RO
- Rage128 Mobility M3 LE
- Rage128 Mobility M3 LF
+ These chips have perfectly new GPU which supports memory mapped IO
+ space for accelerating port access (It's main cause of incompatibility
+ with mach64). Set of Rage128 chips is:
+ Rage128 GL RE
+ Rage128 GL RF
+ Rage128 GL RG
+ Rage128 GL RH
+ Rage128 GL RI
+ Rage128 VR RK
+ Rage128 VR RL
+ Rage128 VR RM
+ Rage128 VR RN
+ Rage128 VR RO
+ Rage128 Mobility M3 LE
+ Rage128 Mobility M3 LF
7. Rage128Pro chips.
- These chips are successors of Rage128 ones.
- Rage128Pro GL PA
- Rage128Pro GL PB
- Rage128Pro GL PC
- Rage128Pro GL PD
- Rage128Pro GL PE
- Rage128Pro GL PF
- Rage128Pro VR PG
- Rage128Pro VR PH
- Rage128Pro VR PI
- Rage128Pro VR PJ
- Rage128Pro VR PK
- Rage128Pro VR PL
- Rage128Pro VR PM
- Rage128Pro VR PN
- Rage128Pro VR PO
- Rage128Pro VR PP
- Rage128Pro VR PQ
- Rage128Pro VR PR
- Rage128Pro VR TR
- Rage128Pro VR PS
- Rage128Pro VR PT
- Rage128Pro VR PU
- Rage128Pro VR PV
- Rage128Pro VR PW
- Rage128Pro VR PX
- Rage128Pro Ultra U1
- Rage128Pro Ultra U2
- Rage128Pro Ultra U3
+ These chips are successors of Rage128 ones.
+ Rage128Pro GL PA
+ Rage128Pro GL PB
+ Rage128Pro GL PC
+ Rage128Pro GL PD
+ Rage128Pro GL PE
+ Rage128Pro GL PF
+ Rage128Pro VR PG
+ Rage128Pro VR PH
+ Rage128Pro VR PI
+ Rage128Pro VR PJ
+ Rage128Pro VR PK
+ Rage128Pro VR PL
+ Rage128Pro VR PM
+ Rage128Pro VR PN
+ Rage128Pro VR PO
+ Rage128Pro VR PP
+ Rage128Pro VR PQ
+ Rage128Pro VR PR
+ Rage128Pro VR TR
+ Rage128Pro VR PS
+ Rage128Pro VR PT
+ Rage128Pro VR PU
+ Rage128Pro VR PV
+ Rage128Pro VR PW
+ Rage128Pro VR PX
+ Rage128Pro Ultra U1
+ Rage128Pro Ultra U2
+ Rage128Pro Ultra U3
8. Radeon chips.
- Indeed they could be named Rage256 Pro. (With minor changes is fully
- compatible with Rage128 chips).
- Radeon QD
- Radeon QE
- Radeon QF
- Radeon QG
- Radeon VE QY
- Radeon VE QZ
- Radeon M6 LY
- Radeon M6 LZ
- Radeon M7 LW
+ Indeed they could be named Rage256 Pro. (With minor changes is fully
+ compatible with Rage128 chips).
+ Radeon QD
+ Radeon QE
+ Radeon QF
+ Radeon QG
+ Radeon VE QY
+ Radeon VE QZ
+ Radeon M6 LY
+ Radeon M6 LZ
+ Radeon M7 LW
9. Radeon2 chips.
- Indeed they could be named Rage512 Pro.
- Radeon2 8500 QL
- Radeon2 7500 QW
+ Indeed they could be named Rage512 Pro.
+ Radeon2 8500 QL
+ Radeon2 7500 QW
10. Radeon3 and newest are cooming soon, but I hope that they will be fully
compatible with Radeon1 chips.
@@ -185,31 +185,31 @@ Please compare:
Sample for Mach64 compatible chips:
***********************************
-#define SPARSE_IO_BASE 0x03fcu
-#define SPARSE_IO_SELECT 0xfc00u
+#define SPARSE_IO_BASE 0x03fcu
+#define SPARSE_IO_SELECT 0xfc00u
-#define BLOCK_IO_BASE 0xff00u
-#define BLOCK_IO_SELECT 0x00fcu
+#define BLOCK_IO_BASE 0xff00u
+#define BLOCK_IO_SELECT 0x00fcu
-#define MM_IO_SELECT 0x03fcu
-#define BLOCK_SELECT 0x0400u
-#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT)
+#define MM_IO_SELECT 0x03fcu
+#define BLOCK_SELECT 0x0400u
+#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT)
-#define IO_BYTE_SELECT 0x0003u
+#define IO_BYTE_SELECT 0x0003u
-#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT)
-#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT)
+#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT)
+#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT)
-#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \
- (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \
- SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT))
-#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0)
-#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect)
+#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \
+ (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \
+ SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT))
+#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0)
+#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect)
...
-#define OVERLAY_Y_X_START BlockIOTag(0x100u)
-#define OVERLAY_Y_X_END BlockIOTag(0x101u)
+#define OVERLAY_Y_X_START BlockIOTag(0x100u)
+#define OVERLAY_Y_X_END BlockIOTag(0x101u)
...
@@ -231,8 +231,8 @@ OUTREG(OVERLAY_Y_X_END,((drw_x+drw_w)<<16)|(drw_y+drw_h));
...
-#define INREG(addr) readl((rage_mmio_base)+addr)
-#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr)
+#define INREG(addr) readl((rage_mmio_base)+addr)
+#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr)
...
@@ -263,7 +263,7 @@ GATOS was designed and introduced as General ATI TV and Overlay Sowfware.
You will be able to find out there a lots of useful hacking utilities
(at location gatos-ati/gatos):
gfxdump - Program for dumping graphics chips registers on Linux and Windows 9X.
- (it's more useful for Win9x to hack their values).
+ (it's more useful for Win9x to hack their values).
xatitv - For working with tv-in (currently is under hard development)
atitvout- For working with tv-out
and lot of other stuff.
@@ -271,11 +271,11 @@ BUT: After studing of Gatos and X11 stuffs I've found that they are bad
optimized for movie playback.
Please compare:
radeon_vid - configures video overlay only once and provides DGA to it.
- (doesn't require to be MMX optimized)
+ (doesn't require to be MMX optimized)
gatos and X11 - configures video overlay at every slice of frame, then
performs unoptimized copying of source stuff to video memory
- often with using CopyMungedData (it's C-analog of YV12_to_YUY2)
- since there are lacks in yv12 support.
+ often with using CopyMungedData (it's C-analog of YV12_to_YUY2)
+ since there are lacks in yv12 support.
(is not MMX optimized that's gladly accepted, but probably
will be never optimized due portability).
diff --git a/drivers/mga_vid.c b/drivers/mga_vid.c
index 8330be29d6..de96aa1b0a 100644
--- a/drivers/mga_vid.c
+++ b/drivers/mga_vid.c
@@ -131,130 +131,130 @@ MODULE_LICENSE("GPL");
static unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
{
- unsigned long result = 0,value;
-
- if (!base) {
- base = 10;
- if (*cp == '0') {
- base = 8;
- cp++;
- if ((*cp == 'x') && isxdigit(cp[1])) {
- cp++;
- base = 16;
- }
- }
- }
- while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
- ? toupper(*cp) : *cp)-'A'+10) < base) {
- result = result*base + value;
+ unsigned long result = 0,value;
+
+ if (!base) {
+ base = 10;
+ if (*cp == '0') {
+ base = 8;
+ cp++;
+ if ((*cp == 'x') && isxdigit(cp[1])) {
cp++;
+ base = 16;
+ }
}
- if (endp)
- *endp = (char *)cp;
- return result;
+ }
+ while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
+ ? toupper(*cp) : *cp)-'A'+10) < base) {
+ result = result*base + value;
+ cp++;
+ }
+ if (endp)
+ *endp = (char *)cp;
+ return result;
}
static long simple_strtol(const char *cp,char **endp,unsigned int base)
{
- if(*cp=='-')
- return -simple_strtoul(cp+1,endp,base);
- return simple_strtoul(cp,endp,base);
+ if(*cp=='-')
+ return -simple_strtoul(cp+1,endp,base);
+ return simple_strtoul(cp,endp,base);
}
#endif
typedef struct bes_registers_s
{
- //BES Control
- uint32_t besctl;
- //BES Global control
- uint32_t besglobctl;
- //Luma control (brightness and contrast)
- uint32_t beslumactl;
- //Line pitch
- uint32_t bespitch;
-
- //Buffer A-1 Chroma 3 plane org
- uint32_t besa1c3org;
- //Buffer A-1 Chroma org
- uint32_t besa1corg;
- //Buffer A-1 Luma org
- uint32_t besa1org;
-
- //Buffer A-2 Chroma 3 plane org
- uint32_t besa2c3org;
- //Buffer A-2 Chroma org
- uint32_t besa2corg;
- //Buffer A-2 Luma org
- uint32_t besa2org;
-
- //Buffer B-1 Chroma 3 plane org
- uint32_t besb1c3org;
- //Buffer B-1 Chroma org
- uint32_t besb1corg;
- //Buffer B-1 Luma org
- uint32_t besb1org;
-
- //Buffer B-2 Chroma 3 plane org
- uint32_t besb2c3org;
- //Buffer B-2 Chroma org
- uint32_t besb2corg;
- //Buffer B-2 Luma org
- uint32_t besb2org;
-
- //BES Horizontal coord
- uint32_t beshcoord;
- //BES Horizontal inverse scaling [5.14]
- uint32_t beshiscal;
- //BES Horizontal source start [10.14] (for scaling)
- uint32_t beshsrcst;
- //BES Horizontal source ending [10.14] (for scaling)
- uint32_t beshsrcend;
- //BES Horizontal source last
- uint32_t beshsrclst;
-
-
- //BES Vertical coord
- uint32_t besvcoord;
- //BES Vertical inverse scaling [5.14]
- uint32_t besviscal;
- //BES Field 1 vertical source last position
- uint32_t besv1srclst;
- //BES Field 1 weight start
- uint32_t besv1wght;
- //BES Field 2 vertical source last position
- uint32_t besv2srclst;
- //BES Field 2 weight start
- uint32_t besv2wght;
-
-
- //configurable stuff
- int blackie;
+ //BES Control
+ uint32_t besctl;
+ //BES Global control
+ uint32_t besglobctl;
+ //Luma control (brightness and contrast)
+ uint32_t beslumactl;
+ //Line pitch
+ uint32_t bespitch;
+
+ //Buffer A-1 Chroma 3 plane org
+ uint32_t besa1c3org;
+ //Buffer A-1 Chroma org
+ uint32_t besa1corg;
+ //Buffer A-1 Luma org
+ uint32_t besa1org;
+
+ //Buffer A-2 Chroma 3 plane org
+ uint32_t besa2c3org;
+ //Buffer A-2 Chroma org
+ uint32_t besa2corg;
+ //Buffer A-2 Luma org
+ uint32_t besa2org;
+
+ //Buffer B-1 Chroma 3 plane org
+ uint32_t besb1c3org;
+ //Buffer B-1 Chroma org
+ uint32_t besb1corg;
+ //Buffer B-1 Luma org
+ uint32_t besb1org;
+
+ //Buffer B-2 Chroma 3 plane org
+ uint32_t besb2c3org;
+ //Buffer B-2 Chroma org
+ uint32_t besb2corg;
+ //Buffer B-2 Luma org
+ uint32_t besb2org;
+
+ //BES Horizontal coord
+ uint32_t beshcoord;
+ //BES Horizontal inverse scaling [5.14]
+ uint32_t beshiscal;
+ //BES Horizontal source start [10.14] (for scaling)
+ uint32_t beshsrcst;
+ //BES Horizontal source ending [10.14] (for scaling)
+ uint32_t beshsrcend;
+ //BES Horizontal source last
+ uint32_t beshsrclst;
+
+
+ //BES Vertical coord
+ uint32_t besvcoord;
+ //BES Vertical inverse scaling [5.14]
+ uint32_t besviscal;
+ //BES Field 1 vertical source last position
+ uint32_t besv1srclst;
+ //BES Field 1 weight start
+ uint32_t besv1wght;
+ //BES Field 2 vertical source last position
+ uint32_t besv2srclst;
+ //BES Field 2 weight start
+ uint32_t besv2wght;
+
+
+ //configurable stuff
+ int blackie;
} bes_registers_t;
#ifdef CRTC2
typedef struct crtc2_registers_s
{
- uint32_t c2ctl;
- uint32_t c2datactl;
- uint32_t c2misc;
- uint32_t c2hparam;
- uint32_t c2hsync;
- uint32_t c2offset;
- uint32_t c2pl2startadd0;
- uint32_t c2pl2startadd1;
- uint32_t c2pl3startadd0;
- uint32_t c2pl3startadd1;
- uint32_t c2preload;
- uint32_t c2spicstartadd0;
- uint32_t c2spicstartadd1;
- uint32_t c2startadd0;
- uint32_t c2startadd1;
- uint32_t c2subpiclut;
- uint32_t c2vcount;
- uint32_t c2vparam;
- uint32_t c2vsync;
+ uint32_t c2ctl;
+ uint32_t c2datactl;
+ uint32_t c2misc;
+ uint32_t c2hparam;
+ uint32_t c2hsync;
+ uint32_t c2offset;
+ uint32_t c2pl2startadd0;
+ uint32_t c2pl2startadd1;
+ uint32_t c2pl3startadd0;
+ uint32_t c2pl3startadd1;
+ uint32_t c2preload;
+ uint32_t c2spicstartadd0;
+ uint32_t c2spicstartadd1;
+ uint32_t c2startadd0;
+ uint32_t c2startadd1;
+ uint32_t c2subpiclut;
+ uint32_t c2vcount;
+ uint32_t c2vparam;
+ uint32_t c2vsync;
} crtc2_registers_t;
#endif
@@ -348,10 +348,10 @@ typedef struct crtc2_registers_s
#define BESVCOORD 0x3d2c
#define BESSTATUS 0x3dc4
-#define CRTCX 0x1fd4
-#define CRTCD 0x1fd5
-#define IEN 0x1e1c
-#define ICLEAR 0x1e18
+#define CRTCX 0x1fd4
+#define CRTCD 0x1fd5
+#define IEN 0x1e1c
+#define ICLEAR 0x1e18
#define STATUS 0x1e14
@@ -365,42 +365,42 @@ typedef struct mga_card_s {
// local devfs handle for /dev/mga_vidX
#ifdef CONFIG_DEVFS_FS
- devfs_handle_t dev_handle;
+ devfs_handle_t dev_handle;
#endif
- uint8_t *param_buff; // buffer for read()
- uint32_t param_buff_size;
- uint32_t param_buff_len;
- bes_registers_t regs;
+ uint8_t *param_buff; // buffer for read()
+ uint32_t param_buff_size;
+ uint32_t param_buff_len;
+ bes_registers_t regs;
#ifdef CRTC2
- crtc2_registers_t cregs;
+ crtc2_registers_t cregs;
#endif
- uint32_t vid_in_use;
- uint32_t is_g400;
- uint32_t vid_src_ready;
- uint32_t vid_overlay_on;
+ uint32_t vid_in_use;
+ uint32_t is_g400;
+ uint32_t vid_src_ready;
+ uint32_t vid_overlay_on;
- uint8_t *mmio_base;
- uint32_t mem_base;
- int src_base; // YUV buffer position in video memory
- uint32_t ram_size; // how much megabytes videoram we have
- uint32_t top_reserved; // reserved space for console font (matroxfb + fastfont)
+ uint8_t *mmio_base;
+ uint32_t mem_base;
+ int src_base; // YUV buffer position in video memory
+ uint32_t ram_size; // how much megabytes videoram we have
+ uint32_t top_reserved; // reserved space for console font (matroxfb + fastfont)
- int brightness; // initial brightness
- int contrast; // initial contrast
+ int brightness; // initial brightness
+ int contrast; // initial contrast
- struct pci_dev *pci_dev;
+ struct pci_dev *pci_dev;
- mga_vid_config_t config;
- int configured; // set to 1 when the card is configured over ioctl
+ mga_vid_config_t config;
+ int configured; // set to 1 when the card is configured over ioctl
- int colkey_saved;
- int colkey_on;
- unsigned char colkey_color[4];
- unsigned char colkey_mask[4];
+ int colkey_saved;
+ int colkey_on;
+ unsigned char colkey_color[4];
+ unsigned char colkey_mask[4];
- int irq; // = -1
- int next_frame;
+ int irq; // = -1
+ int next_frame;
} mga_card_t;
#define MGA_MAX_CARDS 16
@@ -428,48 +428,48 @@ static void crtc2_frame_sel(mga_card_t * card, int frame)
{
switch(frame) {
case 0:
- card->cregs.c2pl2startadd0=card->regs.besa1corg;
- card->cregs.c2pl3startadd0=card->regs.besa1c3org;
- card->cregs.c2startadd0=card->regs.besa1org;
- break;
+ card->cregs.c2pl2startadd0=card->regs.besa1corg;
+ card->cregs.c2pl3startadd0=card->regs.besa1c3org;
+ card->cregs.c2startadd0=card->regs.besa1org;
+ break;
case 1:
- card->cregs.c2pl2startadd0=card->regs.besa2corg;
- card->cregs.c2pl3startadd0=card->regs.besa2c3org;
- card->cregs.c2startadd0=card->regs.besa2org;
- break;
+ card->cregs.c2pl2startadd0=card->regs.besa2corg;
+ card->cregs.c2pl3startadd0=card->regs.besa2c3org;
+ card->cregs.c2startadd0=card->regs.besa2org;
+ break;
case 2:
- card->cregs.c2pl2startadd0=card->regs.besb1corg;
- card->cregs.c2pl3startadd0=card->regs.besb1c3org;
- card->cregs.c2startadd0=card->regs.besb1org;
- break;
+ card->cregs.c2pl2startadd0=card->regs.besb1corg;
+ card->cregs.c2pl3startadd0=card->regs.besb1c3org;
+ card->cregs.c2startadd0=card->regs.besb1org;
+ break;
case 3:
- card->cregs.c2pl2startadd0=card->regs.besb2corg;
- card->cregs.c2pl3startadd0=card->regs.besb2c3org;
- card->cregs.c2startadd0=card->regs.besb2org;
- break;
+ card->cregs.c2pl2startadd0=card->regs.besb2corg;
+ card->cregs.c2pl3startadd0=card->regs.besb2c3org;
+ card->cregs.c2startadd0=card->regs.besb2org;
+ break;
}
- writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0);
- writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0);
- writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0);
+ writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0);
+ writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0);
+ writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0);
}
#endif
static void mga_vid_frame_sel(mga_card_t * card, int frame)
{
if ( card->irq != -1 ) {
- card->next_frame=frame;
+ card->next_frame=frame;
} else {
- //we don't need the vcount protection as we're only hitting
- //one register (and it doesn't seem to be double buffered)
- card->regs.besctl = (card->regs.besctl & ~0x07000000) + (frame << 25);
- writel( card->regs.besctl, card->mmio_base + BESCTL );
+ //we don't need the vcount protection as we're only hitting
+ //one register (and it doesn't seem to be double buffered)
+ card->regs.besctl = (card->regs.besctl & ~0x07000000) + (frame << 25);
+ writel( card->regs.besctl, card->mmio_base + BESCTL );
-// writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16),
- writel( card->regs.besglobctl + (MGA_VSYNC_POS<<16),
- card->mmio_base + BESGLOBCTL);
+// writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16),
+ writel( card->regs.besglobctl + (MGA_VSYNC_POS<<16),
+ card->mmio_base + BESGLOBCTL);
#ifdef CRTC2
- crtc2_frame_sel(card, frame);
+ crtc2_frame_sel(card, frame);
#endif
}
@@ -478,236 +478,235 @@ static void mga_vid_frame_sel(mga_card_t * card, int frame)
static void mga_vid_write_regs(mga_card_t * card, int restore)
{
- //Make sure internal registers don't get updated until we're done
- writel( (readl(card->mmio_base + VCOUNT)-1)<<16,
- card->mmio_base + BESGLOBCTL);
+ //Make sure internal registers don't get updated until we're done
+ writel( (readl(card->mmio_base + VCOUNT)-1)<<16,
+ card->mmio_base + BESGLOBCTL);
- // color or coordinate keying
+ // color or coordinate keying
- if(restore && card->colkey_saved){
- // restore it
- card->colkey_saved=0;
+ if(restore && card->colkey_saved){
+ // restore it
+ card->colkey_saved=0;
#ifdef MP_DEBUG
- printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n",
- card->colkey_on,card->colkey_color[0],card->colkey_color[1],card->colkey_color[2]);
+ printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n",
+ card->colkey_on,card->colkey_color[0],card->colkey_color[1],card->colkey_color[2]);
#endif
- // Set color key registers:
- writeb( XKEYOPMODE, card->mmio_base + PALWTADD);
- writeb( card->colkey_on, card->mmio_base + X_DATAREG);
-
- writeb( XCOLKEY0RED, card->mmio_base + PALWTADD);
- writeb( card->colkey_color[0], card->mmio_base + X_DATAREG);
- writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD);
- writeb( card->colkey_color[1], card->mmio_base + X_DATAREG);
- writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD);
- writeb( card->colkey_color[2], card->mmio_base + X_DATAREG);
- writeb( X_COLKEY, card->mmio_base + PALWTADD);
- writeb( card->colkey_color[3], card->mmio_base + X_DATAREG);
-
- writeb( XCOLMSK0RED, card->mmio_base + PALWTADD);
- writeb( card->colkey_mask[0], card->mmio_base + X_DATAREG);
- writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD);
- writeb( card->colkey_mask[1], card->mmio_base + X_DATAREG);
- writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD);
- writeb( card->colkey_mask[2], card->mmio_base + X_DATAREG);
- writeb( XCOLMSK, card->mmio_base + PALWTADD);
- writeb( card->colkey_mask[3], card->mmio_base + X_DATAREG);
-
- } else if(!card->colkey_saved){
- // save it
- card->colkey_saved=1;
- // Get color key registers:
- writeb( XKEYOPMODE, card->mmio_base + PALWTADD);
- card->colkey_on=(unsigned char)readb(card->mmio_base + X_DATAREG) & 1;
-
- writeb( XCOLKEY0RED, card->mmio_base + PALWTADD);
- card->colkey_color[0]=(unsigned char)readb(card->mmio_base + X_DATAREG);
- writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD);
- card->colkey_color[1]=(unsigned char)readb(card->mmio_base + X_DATAREG);
- writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD);
- card->colkey_color[2]=(unsigned char)readb(card->mmio_base + X_DATAREG);
- writeb( X_COLKEY, card->mmio_base + PALWTADD);
- card->colkey_color[3]=(unsigned char)readb(card->mmio_base + X_DATAREG);
-
- writeb( XCOLMSK0RED, card->mmio_base + PALWTADD);
- card->colkey_mask[0]=(unsigned char)readb(card->mmio_base + X_DATAREG);
- writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD);
- card->colkey_mask[1]=(unsigned char)readb(card->mmio_base + X_DATAREG);
- writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD);
- card->colkey_mask[2]=(unsigned char)readb(card->mmio_base + X_DATAREG);
- writeb( XCOLMSK, card->mmio_base + PALWTADD);
- card->colkey_mask[3]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+ // Set color key registers:
+ writeb( XKEYOPMODE, card->mmio_base + PALWTADD);
+ writeb( card->colkey_on, card->mmio_base + X_DATAREG);
+
+ writeb( XCOLKEY0RED, card->mmio_base + PALWTADD);
+ writeb( card->colkey_color[0], card->mmio_base + X_DATAREG);
+ writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD);
+ writeb( card->colkey_color[1], card->mmio_base + X_DATAREG);
+ writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD);
+ writeb( card->colkey_color[2], card->mmio_base + X_DATAREG);
+ writeb( X_COLKEY, card->mmio_base + PALWTADD);
+ writeb( card->colkey_color[3], card->mmio_base + X_DATAREG);
+
+ writeb( XCOLMSK0RED, card->mmio_base + PALWTADD);
+ writeb( card->colkey_mask[0], card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD);
+ writeb( card->colkey_mask[1], card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD);
+ writeb( card->colkey_mask[2], card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK, card->mmio_base + PALWTADD);
+ writeb( card->colkey_mask[3], card->mmio_base + X_DATAREG);
+
+ } else if(!card->colkey_saved){
+ // save it
+ card->colkey_saved=1;
+ // Get color key registers:
+ writeb( XKEYOPMODE, card->mmio_base + PALWTADD);
+ card->colkey_on=(unsigned char)readb(card->mmio_base + X_DATAREG) & 1;
+
+ writeb( XCOLKEY0RED, card->mmio_base + PALWTADD);
+ card->colkey_color[0]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+ writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD);
+ card->colkey_color[1]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+ writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD);
+ card->colkey_color[2]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+ writeb( X_COLKEY, card->mmio_base + PALWTADD);
+ card->colkey_color[3]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+
+ writeb( XCOLMSK0RED, card->mmio_base + PALWTADD);
+ card->colkey_mask[0]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD);
+ card->colkey_mask[1]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD);
+ card->colkey_mask[2]=(unsigned char)readb(card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK, card->mmio_base + PALWTADD);
+ card->colkey_mask[3]=(unsigned char)readb(card->mmio_base + X_DATAREG);
#ifdef MP_DEBUG
- printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n",
- card->colkey_on, card->colkey_color[0], card->colkey_color[1], card->colkey_color[2]);
+ printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n",
+ card->colkey_on, card->colkey_color[0], card->colkey_color[1], card->colkey_color[2]);
#endif
- }
-
-if(!restore){
- writeb( XKEYOPMODE, card->mmio_base + PALWTADD);
- writeb( card->config.colkey_on, card->mmio_base + X_DATAREG);
- if ( card->config.colkey_on )
- {
- uint32_t r=0, g=0, b=0;
-
- writeb( XMULCTRL, card->mmio_base + PALWTADD);
- switch (readb (card->mmio_base + X_DATAREG))
- {
- case BPP_8:
- /* Need to look up the color index, just using color 0 for now. */
- break;
-
- case BPP_15:
- r = card->config.colkey_red >> 3;
- g = card->config.colkey_green >> 3;
- b = card->config.colkey_blue >> 3;
- break;
-
- case BPP_16:
- r = card->config.colkey_red >> 3;
- g = card->config.colkey_green >> 2;
- b = card->config.colkey_blue >> 3;
- break;
-
- case BPP_24:
- case BPP_32_DIR:
- case BPP_32_PAL:
- r = card->config.colkey_red;
- g = card->config.colkey_green;
- b = card->config.colkey_blue;
- break;
- }
-
- // Disable color keying on alpha channel
- writeb( XCOLMSK, card->mmio_base + PALWTADD);
- writeb( 0x00, card->mmio_base + X_DATAREG);
- writeb( X_COLKEY, card->mmio_base + PALWTADD);
- writeb( 0x00, card->mmio_base + X_DATAREG);
-
-
- // Set up color key registers
- writeb( XCOLKEY0RED, card->mmio_base + PALWTADD);
- writeb( r, card->mmio_base + X_DATAREG);
- writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD);
- writeb( g, card->mmio_base + X_DATAREG);
- writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD);
- writeb( b, card->mmio_base + X_DATAREG);
-
- // Set up color key mask registers
- writeb( XCOLMSK0RED, card->mmio_base + PALWTADD);
- writeb( 0xff, card->mmio_base + X_DATAREG);
- writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD);
- writeb( 0xff, card->mmio_base + X_DATAREG);
- writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD);
- writeb( 0xff, card->mmio_base + X_DATAREG);
- }
+ }
-}
+ if(!restore){
+ writeb( XKEYOPMODE, card->mmio_base + PALWTADD);
+ writeb( card->config.colkey_on, card->mmio_base + X_DATAREG);
+ if ( card->config.colkey_on )
+ {
+ uint32_t r=0, g=0, b=0;
+
+ writeb( XMULCTRL, card->mmio_base + PALWTADD);
+ switch (readb (card->mmio_base + X_DATAREG))
+ {
+ case BPP_8:
+ /* Need to look up the color index, just using color 0 for now. */
+ break;
+
+ case BPP_15:
+ r = card->config.colkey_red >> 3;
+ g = card->config.colkey_green >> 3;
+ b = card->config.colkey_blue >> 3;
+ break;
+
+ case BPP_16:
+ r = card->config.colkey_red >> 3;
+ g = card->config.colkey_green >> 2;
+ b = card->config.colkey_blue >> 3;
+ break;
+
+ case BPP_24:
+ case BPP_32_DIR:
+ case BPP_32_PAL:
+ r = card->config.colkey_red;
+ g = card->config.colkey_green;
+ b = card->config.colkey_blue;
+ break;
+ }
+
+ // Disable color keying on alpha channel
+ writeb( XCOLMSK, card->mmio_base + PALWTADD);
+ writeb( 0x00, card->mmio_base + X_DATAREG);
+ writeb( X_COLKEY, card->mmio_base + PALWTADD);
+ writeb( 0x00, card->mmio_base + X_DATAREG);
+
+
+ // Set up color key registers
+ writeb( XCOLKEY0RED, card->mmio_base + PALWTADD);
+ writeb( r, card->mmio_base + X_DATAREG);
+ writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD);
+ writeb( g, card->mmio_base + X_DATAREG);
+ writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD);
+ writeb( b, card->mmio_base + X_DATAREG);
+
+ // Set up color key mask registers
+ writeb( XCOLMSK0RED, card->mmio_base + PALWTADD);
+ writeb( 0xff, card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD);
+ writeb( 0xff, card->mmio_base + X_DATAREG);
+ writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD);
+ writeb( 0xff, card->mmio_base + X_DATAREG);
+ }
+ }
+
+ // Backend Scaler
+ writel( card->regs.besctl, card->mmio_base + BESCTL);
+ if(card->is_g400)
+ writel( card->regs.beslumactl, card->mmio_base + BESLUMACTL);
+ writel( card->regs.bespitch, card->mmio_base + BESPITCH);
+
+ writel( card->regs.besa1org, card->mmio_base + BESA1ORG);
+ writel( card->regs.besa1corg, card->mmio_base + BESA1CORG);
+ writel( card->regs.besa2org, card->mmio_base + BESA2ORG);
+ writel( card->regs.besa2corg, card->mmio_base + BESA2CORG);
+ writel( card->regs.besb1org, card->mmio_base + BESB1ORG);
+ writel( card->regs.besb1corg, card->mmio_base + BESB1CORG);
+ writel( card->regs.besb2org, card->mmio_base + BESB2ORG);
+ writel( card->regs.besb2corg, card->mmio_base + BESB2CORG);
+ if(card->is_g400)
+ {
+ writel( card->regs.besa1c3org, card->mmio_base + BESA1C3ORG);
+ writel( card->regs.besa2c3org, card->mmio_base + BESA2C3ORG);
+ writel( card->regs.besb1c3org, card->mmio_base + BESB1C3ORG);
+ writel( card->regs.besb2c3org, card->mmio_base + BESB2C3ORG);
+ }
+
+ writel( card->regs.beshcoord, card->mmio_base + BESHCOORD);
+ writel( card->regs.beshiscal, card->mmio_base + BESHISCAL);
+ writel( card->regs.beshsrcst, card->mmio_base + BESHSRCST);
+ writel( card->regs.beshsrcend, card->mmio_base + BESHSRCEND);
+ writel( card->regs.beshsrclst, card->mmio_base + BESHSRCLST);
+
+ writel( card->regs.besvcoord, card->mmio_base + BESVCOORD);
+ writel( card->regs.besviscal, card->mmio_base + BESVISCAL);
- // Backend Scaler
- writel( card->regs.besctl, card->mmio_base + BESCTL);
- if(card->is_g400)
- writel( card->regs.beslumactl, card->mmio_base + BESLUMACTL);
- writel( card->regs.bespitch, card->mmio_base + BESPITCH);
-
- writel( card->regs.besa1org, card->mmio_base + BESA1ORG);
- writel( card->regs.besa1corg, card->mmio_base + BESA1CORG);
- writel( card->regs.besa2org, card->mmio_base + BESA2ORG);
- writel( card->regs.besa2corg, card->mmio_base + BESA2CORG);
- writel( card->regs.besb1org, card->mmio_base + BESB1ORG);
- writel( card->regs.besb1corg, card->mmio_base + BESB1CORG);
- writel( card->regs.besb2org, card->mmio_base + BESB2ORG);
- writel( card->regs.besb2corg, card->mmio_base + BESB2CORG);
- if(card->is_g400)
- {
- writel( card->regs.besa1c3org, card->mmio_base + BESA1C3ORG);
- writel( card->regs.besa2c3org, card->mmio_base + BESA2C3ORG);
- writel( card->regs.besb1c3org, card->mmio_base + BESB1C3ORG);
- writel( card->regs.besb2c3org, card->mmio_base + BESB2C3ORG);
- }
-
- writel( card->regs.beshcoord, card->mmio_base + BESHCOORD);
- writel( card->regs.beshiscal, card->mmio_base + BESHISCAL);
- writel( card->regs.beshsrcst, card->mmio_base + BESHSRCST);
- writel( card->regs.beshsrcend, card->mmio_base + BESHSRCEND);
- writel( card->regs.beshsrclst, card->mmio_base + BESHSRCLST);
-
- writel( card->regs.besvcoord, card->mmio_base + BESVCOORD);
- writel( card->regs.besviscal, card->mmio_base + BESVISCAL);
-
- writel( card->regs.besv1srclst, card->mmio_base + BESV1SRCLST);
- writel( card->regs.besv1wght, card->mmio_base + BESV1WGHT);
- writel( card->regs.besv2srclst, card->mmio_base + BESV2SRCLST);
- writel( card->regs.besv2wght, card->mmio_base + BESV2WGHT);
-
- //update the registers somewhere between 1 and 2 frames from now.
- writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16),
- card->mmio_base + BESGLOBCTL);
+ writel( card->regs.besv1srclst, card->mmio_base + BESV1SRCLST);
+ writel( card->regs.besv1wght, card->mmio_base + BESV1WGHT);
+ writel( card->regs.besv2srclst, card->mmio_base + BESV2SRCLST);
+ writel( card->regs.besv2wght, card->mmio_base + BESV2WGHT);
+
+ //update the registers somewhere between 1 and 2 frames from now.
+ writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16),
+ card->mmio_base + BESGLOBCTL);
#if 0
- printk(KERN_DEBUG "mga_vid: wrote BES registers\n");
- printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n",
- readl(card->mmio_base + BESCTL));
- printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n",
- readl(card->mmio_base + BESGLOBCTL));
- printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n",
- readl(card->mmio_base + BESSTATUS));
+ printk(KERN_DEBUG "mga_vid: wrote BES registers\n");
+ printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n",
+ readl(card->mmio_base + BESCTL));
+ printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n",
+ readl(card->mmio_base + BESGLOBCTL));
+ printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n",
+ readl(card->mmio_base + BESSTATUS));
#endif
#ifdef CRTC2
-// printk("c2ctl:0x%08x c2datactl:0x%08x\n", readl(card->mmio_base + C2CTL), readl(card->mmio_base + C2DATACTL));
-// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC));
-// printk("c2ctl:0x%08x c2datactl:0x%08x\n", card->cregs.c2ctl, card->cregs.c2datactl);
+// printk("c2ctl:0x%08x c2datactl:0x%08x\n", readl(card->mmio_base + C2CTL), readl(card->mmio_base + C2DATACTL));
+// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC));
+// printk("c2ctl:0x%08x c2datactl:0x%08x\n", card->cregs.c2ctl, card->cregs.c2datactl);
-// writel(card->cregs.c2ctl, card->mmio_base + C2CTL);
+// writel(card->cregs.c2ctl, card->mmio_base + C2CTL);
- writel(((readl(card->mmio_base + C2CTL) & ~0x03e00000) + (card->cregs.c2ctl & 0x03e00000)), card->mmio_base + C2CTL);
- writel(((readl(card->mmio_base + C2DATACTL) & ~0x000000ff) + (card->cregs.c2datactl & 0x000000ff)), card->mmio_base + C2DATACTL);
- // ctrc2
- // disable CRTC2 acording to specs
-// writel(card->cregs.c2ctl & 0xfffffff0, card->mmio_base + C2CTL);
+ writel(((readl(card->mmio_base + C2CTL) & ~0x03e00000) + (card->cregs.c2ctl & 0x03e00000)), card->mmio_base + C2CTL);
+ writel(((readl(card->mmio_base + C2DATACTL) & ~0x000000ff) + (card->cregs.c2datactl & 0x000000ff)), card->mmio_base + C2DATACTL);
+ // ctrc2
+ // disable CRTC2 acording to specs
+// writel(card->cregs.c2ctl & 0xfffffff0, card->mmio_base + C2CTL);
// je to treba ???
-// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0xa2, card->mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel
-// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0x92, card->mmio_base + XMISCCTRL);
-// writeb((readb(card->mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, card->mmio_base + XMISCCTRL);
-// writel(card->cregs.c2datactl, card->mmio_base + C2DATACTL);
-// writel(card->cregs.c2hparam, card->mmio_base + C2HPARAM);
-// writel(card->cregs.c2hsync, card->mmio_base + C2HSYNC);
-// writel(card->cregs.c2vparam, card->mmio_base + C2VPARAM);
-// writel(card->cregs.c2vsync, card->mmio_base + C2VSYNC);
- writel(card->cregs.c2misc, card->mmio_base + C2MISC);
+// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0xa2, card->mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel
+// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0x92, card->mmio_base + XMISCCTRL);
+// writeb((readb(card->mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, card->mmio_base + XMISCCTRL);
+// writel(card->cregs.c2datactl, card->mmio_base + C2DATACTL);
+// writel(card->cregs.c2hparam, card->mmio_base + C2HPARAM);
+// writel(card->cregs.c2hsync, card->mmio_base + C2HSYNC);
+// writel(card->cregs.c2vparam, card->mmio_base + C2VPARAM);
+// writel(card->cregs.c2vsync, card->mmio_base + C2VSYNC);
+ writel(card->cregs.c2misc, card->mmio_base + C2MISC);
#ifdef MP_DEBUG
- printk("c2offset = %d\n",card->cregs.c2offset);
+ printk("c2offset = %d\n",card->cregs.c2offset);
#endif
- writel(card->cregs.c2offset, card->mmio_base + C2OFFSET);
- writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0);
-// writel(card->cregs.c2startadd1, card->mmio_base + C2STARTADD1);
- writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0);
-// writel(card->cregs.c2pl2startadd1, card->mmio_base + C2PL2STARTADD1);
- writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0);
-// writel(card->cregs.c2pl3startadd1, card->mmio_base + C2PL3STARTADD1);
- writel(card->cregs.c2spicstartadd0, card->mmio_base + C2SPICSTARTADD0);
-// writel(card->cregs.c2spicstartadd1, card->mmio_base + C2SPICSTARTADD1);
-// writel(card->cregs.c2subpiclut, card->mmio_base + C2SUBPICLUT);
-// writel(card->cregs.c2preload, card->mmio_base + C2PRELOAD);
- // finaly enable everything
-// writel(card->cregs.c2ctl, card->mmio_base + C2CTL);
-// printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(card->mmio_base + C2CTL),readl(card->mmio_base + C2DATACTL));
-// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC));
+ writel(card->cregs.c2offset, card->mmio_base + C2OFFSET);
+ writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0);
+// writel(card->cregs.c2startadd1, card->mmio_base + C2STARTADD1);
+ writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0);
+// writel(card->cregs.c2pl2startadd1, card->mmio_base + C2PL2STARTADD1);
+ writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0);
+// writel(card->cregs.c2pl3startadd1, card->mmio_base + C2PL3STARTADD1);
+ writel(card->cregs.c2spicstartadd0, card->mmio_base + C2SPICSTARTADD0);
+// writel(card->cregs.c2spicstartadd1, card->mmio_base + C2SPICSTARTADD1);
+// writel(card->cregs.c2subpiclut, card->mmio_base + C2SUBPICLUT);
+// writel(card->cregs.c2preload, card->mmio_base + C2PRELOAD);
+ // finaly enable everything
+// writel(card->cregs.c2ctl, card->mmio_base + C2CTL);
+// printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(card->mmio_base + C2CTL),readl(card->mmio_base + C2DATACTL));
+// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC));
#endif
}
static int mga_vid_set_config(mga_card_t * card)
{
- int x, y, sw, sh, dw, dh;
- int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
- mga_vid_config_t *config = &card->config;
- int frame_size = card->config.frame_size;
+ int x, y, sw, sh, dw, dh;
+ int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
+ mga_vid_config_t *config = &card->config;
+ int frame_size = card->config.frame_size;
#ifdef CRTC2
#define right_margin 0
@@ -717,615 +716,609 @@ static int mga_vid_set_config(mga_card_t * card)
#define vsync_len 4
#define upper_margin 39
- unsigned int hdispend = (config->src_width + 31) & ~31;
- unsigned int hsyncstart = hdispend + (right_margin & ~7);
- unsigned int hsyncend = hsyncstart + (hsync_len & ~7);
- unsigned int htotal = hsyncend + (left_margin & ~7);
- unsigned int vdispend = config->src_height;
- unsigned int vsyncstart = vdispend + lower_margin;
- unsigned int vsyncend = vsyncstart + vsync_len;
- unsigned int vtotal = vsyncend + upper_margin;
+ unsigned int hdispend = (config->src_width + 31) & ~31;
+ unsigned int hsyncstart = hdispend + (right_margin & ~7);
+ unsigned int hsyncend = hsyncstart + (hsync_len & ~7);
+ unsigned int htotal = hsyncend + (left_margin & ~7);
+ unsigned int vdispend = config->src_height;
+ unsigned int vsyncstart = vdispend + lower_margin;
+ unsigned int vsyncend = vsyncstart + vsync_len;
+ unsigned int vtotal = vsyncend + upper_margin;
#endif
- x = config->x_org;
- y = config->y_org;
- sw = config->src_width;
- sh = config->src_height;
- dw = config->dest_width;
- dh = config->dest_height;
+ x = config->x_org;
+ y = config->y_org;
+ sw = config->src_width;
+ sh = config->src_height;
+ dw = config->dest_width;
+ dh = config->dest_height;
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n",
- dw, dh, x, y, sw, sh, config->format);
+ printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n",
+ dw, dh, x, y, sw, sh, config->format);
#endif
- if(sw<4 || sh<4 || dw<4 || dh<4){
- printk(KERN_ERR "mga_vid: Invalid src/dest dimenstions\n");
- return -1;
- }
+ if(sw<4 || sh<4 || dw<4 || dh<4){
+ printk(KERN_ERR "mga_vid: Invalid src/dest dimenstions\n");
+ return -1;
+ }
- //FIXME check that window is valid and inside desktop
+ //FIXME check that window is valid and inside desktop
- //Setup the BES registers for a three plane 4:2:0 video source
+ //Setup the BES registers for a three plane 4:2:0 video source
- card->regs.besglobctl = 0;
+ card->regs.besglobctl = 0;
-switch(config->format){
+ switch(config->format){
case MGA_VID_FORMAT_YV12:
case MGA_VID_FORMAT_I420:
case MGA_VID_FORMAT_IYUV:
- card->regs.besctl = 1 // BES enabled
- + (0<<6) // even start polarity
- + (1<<10) // x filtering enabled
- + (1<<11) // y filtering enabled
- + (1<<16) // chroma upsampling
- + (1<<17) // 4:2:0 mode
- + (1<<18); // dither enabled
+ card->regs.besctl = 1 // BES enabled
+ + (0<<6) // even start polarity
+ + (1<<10) // x filtering enabled
+ + (1<<11) // y filtering enabled
+ + (1<<16) // chroma upsampling
+ + (1<<17) // 4:2:0 mode
+ + (1<<18); // dither enabled
#if 0
- if(card->is_g400)
- {
- //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp
- //disabled, rgb mode disabled
- card->regs.besglobctl = (1<<5);
- }
- else
- {
- //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr
- //in 1357, BES register update on besvcnt
- card->regs.besglobctl = 0;
- }
+ if(card->is_g400)
+ {
+ //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp
+ //disabled, rgb mode disabled
+ card->regs.besglobctl = (1<<5);
+ }
+ else
+ {
+ //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr
+ //in 1357, BES register update on besvcnt
+ card->regs.besglobctl = 0;
+ }
#endif
break;
case MGA_VID_FORMAT_YUY2:
- card->regs.besctl = 1 // BES enabled
- + (0<<6) // even start polarity
- + (1<<10) // x filtering enabled
- + (1<<11) // y filtering enabled
- + (1<<16) // chroma upsampling
- + (0<<17) // 4:2:2 mode
- + (1<<18); // dither enabled
-
- card->regs.besglobctl = 0; // YUY2 format selected
+ card->regs.besctl = 1 // BES enabled
+ + (0<<6) // even start polarity
+ + (1<<10) // x filtering enabled
+ + (1<<11) // y filtering enabled
+ + (1<<16) // chroma upsampling
+ + (0<<17) // 4:2:2 mode
+ + (1<<18); // dither enabled
+
+ card->regs.besglobctl = 0; // YUY2 format selected
break;
case MGA_VID_FORMAT_UYVY:
- card->regs.besctl = 1 // BES enabled
- + (0<<6) // even start polarity
- + (1<<10) // x filtering enabled
- + (1<<11) // y filtering enabled
- + (1<<16) // chroma upsampling
- + (0<<17) // 4:2:2 mode
- + (1<<18); // dither enabled
-
- card->regs.besglobctl = 1<<6; // UYVY format selected
+ card->regs.besctl = 1 // BES enabled
+ + (0<<6) // even start polarity
+ + (1<<10) // x filtering enabled
+ + (1<<11) // y filtering enabled
+ + (1<<16) // chroma upsampling
+ + (0<<17) // 4:2:2 mode
+ + (1<<18); // dither enabled
+
+ card->regs.besglobctl = 1<<6; // UYVY format selected
break;
default:
- printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format);
- return -1;
+ printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format);
+ return -1;
}
- // setting black&white mode
- card->regs.besctl|=(card->regs.blackie<<20);
+ // setting black&white mode
+ card->regs.besctl|=(card->regs.blackie<<20);
- //Enable contrast and brightness control
- card->regs.besglobctl |= (1<<5) + (1<<7);
+ //Enable contrast and brightness control
+ card->regs.besglobctl |= (1<<5) + (1<<7);
- // brightness (-128..127) && contrast (0..255)
- card->regs.beslumactl = (card->brightness << 16) | ((card->contrast+0x80)&0xFFFF);
+ // brightness (-128..127) && contrast (0..255)
+ card->regs.beslumactl = (card->brightness << 16) | ((card->contrast+0x80)&0xFFFF);
- //Setup destination window boundaries
- besleft = x > 0 ? x : 0;
- bestop = y > 0 ? y : 0;
- card->regs.beshcoord = (besleft<<16) + (x + dw-1);
- card->regs.besvcoord = (bestop<<16) + (y + dh-1);
+ //Setup destination window boundaries
+ besleft = x > 0 ? x : 0;
+ bestop = y > 0 ? y : 0;
+ card->regs.beshcoord = (besleft<<16) + (x + dw-1);
+ card->regs.besvcoord = (bestop<<16) + (y + dh-1);
- //Setup source dimensions
- card->regs.beshsrclst = (sw - 1) << 16;
- card->regs.bespitch = (sw + 31) & ~31 ;
+ //Setup source dimensions
+ card->regs.beshsrclst = (sw - 1) << 16;
+ card->regs.bespitch = (sw + 31) & ~31 ;
- //Setup horizontal scaling
- ifactor = ((sw-1)<<14)/(dw-1);
- ofsleft = besleft - x;
+ //Setup horizontal scaling
+ ifactor = ((sw-1)<<14)/(dw-1);
+ ofsleft = besleft - x;
- card->regs.beshiscal = ifactor<<2;
- card->regs.beshsrcst = (ofsleft*ifactor)<<2;
- card->regs.beshsrcend = card->regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
+ card->regs.beshiscal = ifactor<<2;
+ card->regs.beshsrcst = (ofsleft*ifactor)<<2;
+ card->regs.beshsrcend = card->regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
- //Setup vertical scaling
- ifactor = ((sh-1)<<14)/(dh-1);
- ofstop = bestop - y;
+ //Setup vertical scaling
+ ifactor = ((sh-1)<<14)/(dh-1);
+ ofstop = bestop - y;
- card->regs.besviscal = ifactor<<2;
+ card->regs.besviscal = ifactor<<2;
- baseadrofs = ( (ofstop * card->regs.besviscal) >>16) * card->regs.bespitch;
- //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
- card->regs.besa1org = (uint32_t) card->src_base + baseadrofs;
- card->regs.besa2org = (uint32_t) card->src_base + baseadrofs + 1*frame_size;
- card->regs.besb1org = (uint32_t) card->src_base + baseadrofs + 2*frame_size;
- card->regs.besb2org = (uint32_t) card->src_base + baseadrofs + 3*frame_size;
+ baseadrofs = ( (ofstop * card->regs.besviscal) >>16) * card->regs.bespitch;
+ //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
+ card->regs.besa1org = (uint32_t) card->src_base + baseadrofs;
+ card->regs.besa2org = (uint32_t) card->src_base + baseadrofs + 1*frame_size;
+ card->regs.besb1org = (uint32_t) card->src_base + baseadrofs + 2*frame_size;
+ card->regs.besb2org = (uint32_t) card->src_base + baseadrofs + 3*frame_size;
-if(config->format==MGA_VID_FORMAT_YV12
- ||config->format==MGA_VID_FORMAT_IYUV
- ||config->format==MGA_VID_FORMAT_I420
- ){
+ if(config->format==MGA_VID_FORMAT_YV12
+ ||config->format==MGA_VID_FORMAT_IYUV
+ ||config->format==MGA_VID_FORMAT_I420
+ ){
// planar YUV frames:
- if (card->is_g400)
- baseadrofs = ( ( (ofstop * card->regs.besviscal ) / 4 ) >> 16 ) * card->regs.bespitch;
- else
- baseadrofs = ( ( ( ofstop * card->regs.besviscal ) / 2 ) >> 16 ) * card->regs.bespitch;
-
- if(config->format==MGA_VID_FORMAT_YV12 || !card->is_g400){
- card->regs.besa1corg = (uint32_t) card->src_base + baseadrofs + card->regs.bespitch * sh ;
- card->regs.besa2corg = (uint32_t) card->src_base + baseadrofs + 1*frame_size + card->regs.bespitch * sh;
- card->regs.besb1corg = (uint32_t) card->src_base + baseadrofs + 2*frame_size + card->regs.bespitch * sh;
- card->regs.besb2corg = (uint32_t) card->src_base + baseadrofs + 3*frame_size + card->regs.bespitch * sh;
- card->regs.besa1c3org = card->regs.besa1corg + ( (card->regs.bespitch * sh) / 4);
- card->regs.besa2c3org = card->regs.besa2corg + ( (card->regs.bespitch * sh) / 4);
- card->regs.besb1c3org = card->regs.besb1corg + ( (card->regs.bespitch * sh) / 4);
- card->regs.besb2c3org = card->regs.besb2corg + ( (card->regs.bespitch * sh) / 4);
- } else {
- card->regs.besa1c3org = (uint32_t) card->src_base + baseadrofs + card->regs.bespitch * sh ;
- card->regs.besa2c3org = (uint32_t) card->src_base + baseadrofs + 1*frame_size + card->regs.bespitch * sh;
- card->regs.besb1c3org = (uint32_t) card->src_base + baseadrofs + 2*frame_size + card->regs.bespitch * sh;
- card->regs.besb2c3org = (uint32_t) card->src_base + baseadrofs + 3*frame_size + card->regs.bespitch * sh;
- card->regs.besa1corg = card->regs.besa1c3org + ((card->regs.bespitch * sh) / 4);
- card->regs.besa2corg = card->regs.besa2c3org + ((card->regs.bespitch * sh) / 4);
- card->regs.besb1corg = card->regs.besb1c3org + ((card->regs.bespitch * sh) / 4);
- card->regs.besb2corg = card->regs.besb2c3org + ((card->regs.bespitch * sh) / 4);
+ if (card->is_g400)
+ baseadrofs = ( ( (ofstop * card->regs.besviscal ) / 4 ) >> 16 ) * card->regs.bespitch;
+ else
+ baseadrofs = ( ( ( ofstop * card->regs.besviscal ) / 2 ) >> 16 ) * card->regs.bespitch;
+
+ if(config->format==MGA_VID_FORMAT_YV12 || !card->is_g400){
+ card->regs.besa1corg = (uint32_t) card->src_base + baseadrofs + card->regs.bespitch * sh ;
+ card->regs.besa2corg = (uint32_t) card->src_base + baseadrofs + 1*frame_size + card->regs.bespitch * sh;
+ card->regs.besb1corg = (uint32_t) card->src_base + baseadrofs + 2*frame_size + card->regs.bespitch * sh;
+ card->regs.besb2corg = (uint32_t) card->src_base + baseadrofs + 3*frame_size + card->regs.bespitch * sh;
+ card->regs.besa1c3org = card->regs.besa1corg + ( (card->regs.bespitch * sh) / 4);
+ card->regs.besa2c3org = card->regs.besa2corg + ( (card->regs.bespitch * sh) / 4);
+ card->regs.besb1c3org = card->regs.besb1corg + ( (card->regs.bespitch * sh) / 4);
+ card->regs.besb2c3org = card->regs.besb2corg + ( (card->regs.bespitch * sh) / 4);
+ } else {
+ card->regs.besa1c3org = (uint32_t) card->src_base + baseadrofs + card->regs.bespitch * sh ;
+ card->regs.besa2c3org = (uint32_t) card->src_base + baseadrofs + 1*frame_size + card->regs.bespitch * sh;
+ card->regs.besb1c3org = (uint32_t) card->src_base + baseadrofs + 2*frame_size + card->regs.bespitch * sh;
+ card->regs.besb2c3org = (uint32_t) card->src_base + baseadrofs + 3*frame_size + card->regs.bespitch * sh;
+ card->regs.besa1corg = card->regs.besa1c3org + ((card->regs.bespitch * sh) / 4);
+ card->regs.besa2corg = card->regs.besa2c3org + ((card->regs.bespitch * sh) / 4);
+ card->regs.besb1corg = card->regs.besb1c3org + ((card->regs.bespitch * sh) / 4);
+ card->regs.besb2corg = card->regs.besb2c3org + ((card->regs.bespitch * sh) / 4);
+ }
}
-}
-
- weight = ofstop * (card->regs.besviscal >> 2);
- weights = weight < 0 ? 1 : 0;
- card->regs.besv2wght = card->regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
- card->regs.besv2srclst = card->regs.besv1srclst = sh - 1 - (((ofstop * card->regs.besviscal) >> 16) & 0x03FF);
+ weight = ofstop * (card->regs.besviscal >> 2);
+ weights = weight < 0 ? 1 : 0;
+ card->regs.besv2wght = card->regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
+ card->regs.besv2srclst = card->regs.besv1srclst = sh - 1 - (((ofstop * card->regs.besviscal) >> 16) & 0x03FF);
#ifdef CRTC2
- // pridat hlavni registry - tj. casovani ...
+ // pridat hlavni registry - tj. casovani ...
-switch(config->format){
+ switch(config->format){
case MGA_VID_FORMAT_YV12:
case MGA_VID_FORMAT_I420:
case MGA_VID_FORMAT_IYUV:
- card->cregs.c2ctl = 1 // CRTC2 enabled
- + (1<<1) // external clock
- + (0<<2) // external clock
- + (1<<3) // pixel clock enable - not needed ???
- + (0<<4) // high prioryty req
- + (1<<5) // high prioryty req
- + (0<<6) // high prioryty req
- + (1<<8) // high prioryty req max
- + (0<<9) // high prioryty req max
- + (0<<10) // high prioryty req max
- + (0<<20) // CRTC1 to DAC
- + (1<<21) // 420 mode
- + (1<<22) // 420 mode
- + (1<<23) // 420 mode
- + (0<<24) // single chroma line for 420 mode - need to be corrected
- + (0<<25) /*/ interlace mode - need to be corrected*/
- + (0<<26) // field legth polariry
- + (0<<27) // field identification polariry
- + (1<<28) // VIDRST detection mode
- + (0<<29) // VIDRST detection mode
- + (1<<30) // Horizontal counter preload
- + (1<<31) // Vertical counter preload
- ;
- card->cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
- + (1<<1) // Y filter enable
- + (1<<2) // CbCr filter enable
- + (0<<3) // subpicture enable (disabled)
- + (0<<4) // NTSC enable (disabled - PAL)
- + (0<<5) // C2 static subpicture enable (disabled)
- + (0<<6) // C2 subpicture offset division (disabled)
- + (0<<7) // 422 subformat selection !
-/* + (0<<8) // 15 bpp high alpha
- + (0<<9) // 15 bpp high alpha
- + (0<<10) // 15 bpp high alpha
- + (0<<11) // 15 bpp high alpha
- + (0<<12) // 15 bpp high alpha
- + (0<<13) // 15 bpp high alpha
- + (0<<14) // 15 bpp high alpha
- + (0<<15) // 15 bpp high alpha
- + (0<<16) // 15 bpp low alpha
- + (0<<17) // 15 bpp low alpha
- + (0<<18) // 15 bpp low alpha
- + (0<<19) // 15 bpp low alpha
- + (0<<20) // 15 bpp low alpha
- + (0<<21) // 15 bpp low alpha
- + (0<<22) // 15 bpp low alpha
- + (0<<23) // 15 bpp low alpha
- + (0<<24) // static subpicture key
- + (0<<25) // static subpicture key
- + (0<<26) // static subpicture key
- + (0<<27) // static subpicture key
- + (0<<28) // static subpicture key
-*/ ;
+ card->cregs.c2ctl = 1 // CRTC2 enabled
+ + (1<<1) // external clock
+ + (0<<2) // external clock
+ + (1<<3) // pixel clock enable - not needed ???
+ + (0<<4) // high prioryty req
+ + (1<<5) // high prioryty req
+ + (0<<6) // high prioryty req
+ + (1<<8) // high prioryty req max
+ + (0<<9) // high prioryty req max
+ + (0<<10) // high prioryty req max
+ + (0<<20) // CRTC1 to DAC
+ + (1<<21) // 420 mode
+ + (1<<22) // 420 mode
+ + (1<<23) // 420 mode
+ + (0<<24) // single chroma line for 420 mode - need to be corrected
+ + (0<<25) /*/ interlace mode - need to be corrected*/
+ + (0<<26) // field legth polariry
+ + (0<<27) // field identification polariry
+ + (1<<28) // VIDRST detection mode
+ + (0<<29) // VIDRST detection mode
+ + (1<<30) // Horizontal counter preload
+ + (1<<31) // Vertical counter preload
+ ;
+ card->cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
+ + (1<<1) // Y filter enable
+ + (1<<2) // CbCr filter enable
+ + (0<<3) // subpicture enable (disabled)
+ + (0<<4) // NTSC enable (disabled - PAL)
+ + (0<<5) // C2 static subpicture enable (disabled)
+ + (0<<6) // C2 subpicture offset division (disabled)
+ + (0<<7) // 422 subformat selection !
+/* + (0<<8) // 15 bpp high alpha
+ + (0<<9) // 15 bpp high alpha
+ + (0<<10) // 15 bpp high alpha
+ + (0<<11) // 15 bpp high alpha
+ + (0<<12) // 15 bpp high alpha
+ + (0<<13) // 15 bpp high alpha
+ + (0<<14) // 15 bpp high alpha
+ + (0<<15) // 15 bpp high alpha
+ + (0<<16) // 15 bpp low alpha
+ + (0<<17) // 15 bpp low alpha
+ + (0<<18) // 15 bpp low alpha
+ + (0<<19) // 15 bpp low alpha
+ + (0<<20) // 15 bpp low alpha
+ + (0<<21) // 15 bpp low alpha
+ + (0<<22) // 15 bpp low alpha
+ + (0<<23) // 15 bpp low alpha
+ + (0<<24) // static subpicture key
+ + (0<<25) // static subpicture key
+ + (0<<26) // static subpicture key
+ + (0<<27) // static subpicture key
+ + (0<<28) // static subpicture key
+*/ ;
break;
case MGA_VID_FORMAT_YUY2:
- card->cregs.c2ctl = 1 // CRTC2 enabled
- + (1<<1) // external clock
- + (0<<2) // external clock
- + (1<<3) // pixel clock enable - not needed ???
- + (0<<4) // high prioryty req - acc to spec
- + (1<<5) // high prioryty req
- + (0<<6) // high prioryty req
- // 7 reserved
- + (1<<8) // high prioryty req max
- + (0<<9) // high prioryty req max
- + (0<<10) // high prioryty req max
- // 11-19 reserved
- + (0<<20) // CRTC1 to DAC
- + (1<<21) // 422 mode
- + (0<<22) // 422 mode
- + (1<<23) // 422 mode
- + (0<<24) // single chroma line for 420 mode - need to be corrected
- + (0<<25) /*/ interlace mode - need to be corrected*/
- + (0<<26) // field legth polariry
- + (0<<27) // field identification polariry
- + (1<<28) // VIDRST detection mode
- + (0<<29) // VIDRST detection mode
- + (1<<30) // Horizontal counter preload
- + (1<<31) // Vertical counter preload
- ;
- card->cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
- + (1<<1) // Y filter enable
- + (1<<2) // CbCr filter enable
- + (0<<3) // subpicture enable (disabled)
- + (0<<4) // NTSC enable (disabled - PAL)
- + (0<<5) // C2 static subpicture enable (disabled)
- + (0<<6) // C2 subpicture offset division (disabled)
- + (0<<7) // 422 subformat selection !
-/* + (0<<8) // 15 bpp high alpha
- + (0<<9) // 15 bpp high alpha
- + (0<<10) // 15 bpp high alpha
- + (0<<11) // 15 bpp high alpha
- + (0<<12) // 15 bpp high alpha
- + (0<<13) // 15 bpp high alpha
- + (0<<14) // 15 bpp high alpha
- + (0<<15) // 15 bpp high alpha
- + (0<<16) // 15 bpp low alpha
- + (0<<17) // 15 bpp low alpha
- + (0<<18) // 15 bpp low alpha
- + (0<<19) // 15 bpp low alpha
- + (0<<20) // 15 bpp low alpha
- + (0<<21) // 15 bpp low alpha
- + (0<<22) // 15 bpp low alpha
- + (0<<23) // 15 bpp low alpha
- + (0<<24) // static subpicture key
- + (0<<25) // static subpicture key
- + (0<<26) // static subpicture key
- + (0<<27) // static subpicture key
- + (0<<28) // static subpicture key
-*/ ;
+ card->cregs.c2ctl = 1 // CRTC2 enabled
+ + (1<<1) // external clock
+ + (0<<2) // external clock
+ + (1<<3) // pixel clock enable - not needed ???
+ + (0<<4) // high prioryty req - acc to spec
+ + (1<<5) // high prioryty req
+ + (0<<6) // high prioryty req
+ // 7 reserved
+ + (1<<8) // high prioryty req max
+ + (0<<9) // high prioryty req max
+ + (0<<10) // high prioryty req max
+ // 11-19 reserved
+ + (0<<20) // CRTC1 to DAC
+ + (1<<21) // 422 mode
+ + (0<<22) // 422 mode
+ + (1<<23) // 422 mode
+ + (0<<24) // single chroma line for 420 mode - need to be corrected
+ + (0<<25) /*/ interlace mode - need to be corrected*/
+ + (0<<26) // field legth polariry
+ + (0<<27) // field identification polariry
+ + (1<<28) // VIDRST detection mode
+ + (0<<29) // VIDRST detection mode
+ + (1<<30) // Horizontal counter preload
+ + (1<<31) // Vertical counter preload
+ ;
+ card->cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
+ + (1<<1) // Y filter enable
+ + (1<<2) // CbCr filter enable
+ + (0<<3) // subpicture enable (disabled)
+ + (0<<4) // NTSC enable (disabled - PAL)
+ + (0<<5) // C2 static subpicture enable (disabled)
+ + (0<<6) // C2 subpicture offset division (disabled)
+ + (0<<7) // 422 subformat selection !
+/* + (0<<8) // 15 bpp high alpha
+ + (0<<9) // 15 bpp high alpha
+ + (0<<10) // 15 bpp high alpha
+ + (0<<11) // 15 bpp high alpha
+ + (0<<12) // 15 bpp high alpha
+ + (0<<13) // 15 bpp high alpha
+ + (0<<14) // 15 bpp high alpha
+ + (0<<15) // 15 bpp high alpha
+ + (0<<16) // 15 bpp low alpha
+ + (0<<17) // 15 bpp low alpha
+ + (0<<18) // 15 bpp low alpha
+ + (0<<19) // 15 bpp low alpha
+ + (0<<20) // 15 bpp low alpha
+ + (0<<21) // 15 bpp low alpha
+ + (0<<22) // 15 bpp low alpha
+ + (0<<23) // 15 bpp low alpha
+ + (0<<24) // static subpicture key
+ + (0<<25) // static subpicture key
+ + (0<<26) // static subpicture key
+ + (0<<27) // static subpicture key
+ + (0<<28) // static subpicture key
+*/ ;
break;
case MGA_VID_FORMAT_UYVY:
- card->cregs.c2ctl = 1 // CRTC2 enabled
- + (1<<1) // external clock
- + (0<<2) // external clock
- + (1<<3) // pixel clock enable - not needed ???
- + (0<<4) // high prioryty req
- + (1<<5) // high prioryty req
- + (0<<6) // high prioryty req
- + (1<<8) // high prioryty req max
- + (0<<9) // high prioryty req max
- + (0<<10) // high prioryty req max
- + (0<<20) // CRTC1 to DAC
- + (1<<21) // 422 mode
- + (0<<22) // 422 mode
- + (1<<23) // 422 mode
- + (1<<24) // single chroma line for 420 mode - need to be corrected
- + (1<<25) /*/ interlace mode - need to be corrected*/
- + (0<<26) // field legth polariry
- + (0<<27) // field identification polariry
- + (1<<28) // VIDRST detection mode
- + (0<<29) // VIDRST detection mode
- + (1<<30) // Horizontal counter preload
- + (1<<31) // Vertical counter preload
- ;
- card->cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode
- + (1<<1) // Y filter enable
- + (1<<2) // CbCr filter enable
- + (0<<3) // subpicture enable (disabled)
- + (0<<4) // NTSC enable (disabled - PAL)
- + (0<<5) // C2 static subpicture enable (disabled)
- + (0<<6) // C2 subpicture offset division (disabled)
- + (1<<7) // 422 subformat selection !
-/* + (0<<8) // 15 bpp high alpha
- + (0<<9) // 15 bpp high alpha
- + (0<<10) // 15 bpp high alpha
- + (0<<11) // 15 bpp high alpha
- + (0<<12) // 15 bpp high alpha
- + (0<<13) // 15 bpp high alpha
- + (0<<14) // 15 bpp high alpha
- + (0<<15) // 15 bpp high alpha
- + (0<<16) // 15 bpp low alpha
- + (0<<17) // 15 bpp low alpha
- + (0<<18) // 15 bpp low alpha
- + (0<<19) // 15 bpp low alpha
- + (0<<20) // 15 bpp low alpha
- + (0<<21) // 15 bpp low alpha
- + (0<<22) // 15 bpp low alpha
- + (0<<23) // 15 bpp low alpha
- + (0<<24) // static subpicture key
- + (0<<25) // static subpicture key
- + (0<<26) // static subpicture key
- + (0<<27) // static subpicture key
- + (0<<28) // static subpicture key
-*/ ;
+ card->cregs.c2ctl = 1 // CRTC2 enabled
+ + (1<<1) // external clock
+ + (0<<2) // external clock
+ + (1<<3) // pixel clock enable - not needed ???
+ + (0<<4) // high prioryty req
+ + (1<<5) // high prioryty req
+ + (0<<6) // high prioryty req
+ + (1<<8) // high prioryty req max
+ + (0<<9) // high prioryty req max
+ + (0<<10) // high prioryty req max
+ + (0<<20) // CRTC1 to DAC
+ + (1<<21) // 422 mode
+ + (0<<22) // 422 mode
+ + (1<<23) // 422 mode
+ + (1<<24) // single chroma line for 420 mode - need to be corrected
+ + (1<<25) /*/ interlace mode - need to be corrected*/
+ + (0<<26) // field legth polariry
+ + (0<<27) // field identification polariry
+ + (1<<28) // VIDRST detection mode
+ + (0<<29) // VIDRST detection mode
+ + (1<<30) // Horizontal counter preload
+ + (1<<31) // Vertical counter preload
+ ;
+ card->cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode
+ + (1<<1) // Y filter enable
+ + (1<<2) // CbCr filter enable
+ + (0<<3) // subpicture enable (disabled)
+ + (0<<4) // NTSC enable (disabled - PAL)
+ + (0<<5) // C2 static subpicture enable (disabled)
+ + (0<<6) // C2 subpicture offset division (disabled)
+ + (1<<7) // 422 subformat selection !
+/* + (0<<8) // 15 bpp high alpha
+ + (0<<9) // 15 bpp high alpha
+ + (0<<10) // 15 bpp high alpha
+ + (0<<11) // 15 bpp high alpha
+ + (0<<12) // 15 bpp high alpha
+ + (0<<13) // 15 bpp high alpha
+ + (0<<14) // 15 bpp high alpha
+ + (0<<15) // 15 bpp high alpha
+ + (0<<16) // 15 bpp low alpha
+ + (0<<17) // 15 bpp low alpha
+ + (0<<18) // 15 bpp low alpha
+ + (0<<19) // 15 bpp low alpha
+ + (0<<20) // 15 bpp low alpha
+ + (0<<21) // 15 bpp low alpha
+ + (0<<22) // 15 bpp low alpha
+ + (0<<23) // 15 bpp low alpha
+ + (0<<24) // static subpicture key
+ + (0<<25) // static subpicture key
+ + (0<<26) // static subpicture key
+ + (0<<27) // static subpicture key
+ + (0<<28) // static subpicture key
+*/ ;
break;
default:
- printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format);
- return -1;
+ printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format);
+ return -1;
}
- card->cregs.c2hparam = ( (hdispend - 8) << 16) | (htotal - 8);
- card->cregs.c2hsync = ( (hsyncend - 8) << 16) | (hsyncstart - 8);
+ card->cregs.c2hparam = ( (hdispend - 8) << 16) | (htotal - 8);
+ card->cregs.c2hsync = ( (hsyncend - 8) << 16) | (hsyncstart - 8);
- card->cregs.c2misc=0 // CRTCV2 656 togg f0
- +(0<<1) // CRTCV2 656 togg f0
- +(0<<2) // CRTCV2 656 togg f0
- +(0<<4) // CRTCV2 656 togg f1
- +(0<<5) // CRTCV2 656 togg f1
- +(0<<6) // CRTCV2 656 togg f1
- +(0<<8) // Hsync active high
- +(0<<9) // Vsync active high
- // 16-27 c2vlinecomp - nevim co tam dat
- ;
- card->cregs.c2offset=(card->regs.bespitch << 1);
+ card->cregs.c2misc = 0 // CRTCV2 656 togg f0
+ + (0<<1) // CRTCV2 656 togg f0
+ + (0<<2) // CRTCV2 656 togg f0
+ + (0<<4) // CRTCV2 656 togg f1
+ + (0<<5) // CRTCV2 656 togg f1
+ + (0<<6) // CRTCV2 656 togg f1
+ + (0<<8) // Hsync active high
+ + (0<<9) // Vsync active high
+ // 16-27 c2vlinecomp - nevim co tam dat
+ ;
+ card->cregs.c2offset=(card->regs.bespitch << 1);
- card->cregs.c2pl2startadd0=card->regs.besa1corg;
-// card->cregs.c2pl2startadd1=card->regs.besa2corg;
- card->cregs.c2pl3startadd0=card->regs.besa1c3org;
-// card->cregs.c2pl3startadd1=card->regs.besa2c3org;
+ card->cregs.c2pl2startadd0=card->regs.besa1corg;
+// card->cregs.c2pl2startadd1=card->regs.besa2corg;
+ card->cregs.c2pl3startadd0=card->regs.besa1c3org;
+// card->cregs.c2pl3startadd1=card->regs.besa2c3org;
- card->cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from
+ card->cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from
- card->cregs.c2spicstartadd0=0; // not used
-// card->cregs.c2spicstartadd1=0; // not used
+ card->cregs.c2spicstartadd0=0; // not used
+// card->cregs.c2spicstartadd1=0; // not used
- card->cregs.c2startadd0=card->regs.besa1org;
-// card->cregs.c2startadd1=card->regs.besa2org;
+ card->cregs.c2startadd0=card->regs.besa1org;
+// card->cregs.c2startadd1=card->regs.besa2org;
- card->cregs.c2subpiclut=0; //not used
+ card->cregs.c2subpiclut=0; //not used
- card->cregs.c2vparam = ( (vdispend - 1) << 16) | (vtotal - 1);
- card->cregs.c2vsync = ( (vsyncend - 1) << 16) | (vsyncstart - 1);
+ card->cregs.c2vparam = ( (vdispend - 1) << 16) | (vtotal - 1);
+ card->cregs.c2vsync = ( (vsyncend - 1) << 16) | (vsyncstart - 1);
#endif
- mga_vid_write_regs(card, 0);
- return 0;
+ mga_vid_write_regs(card, 0);
+ return 0;
}
#ifdef MGA_ALLOW_IRQ
static void enable_irq(mga_card_t * card){
- long int cc;
-
- cc = readl(card->mmio_base + IEN);
-// printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff));
+ long int cc;
- writeb(0x11, card->mmio_base + CRTCX);
+ cc = readl(card->mmio_base + IEN);
+// printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff));
- writeb(0x20, card->mmio_base + CRTCD); /* clear 0, enable off */
- writeb(0x00, card->mmio_base + CRTCD); /* enable on */
- writeb(0x10, card->mmio_base + CRTCD); /* clear = 1 */
+ writeb(0x11, card->mmio_base + CRTCX);
- writel(card->regs.besglobctl , card->mmio_base + BESGLOBCTL);
+ writeb(0x20, card->mmio_base + CRTCD); /* clear 0, enable off */
+ writeb(0x00, card->mmio_base + CRTCD); /* enable on */
+ writeb(0x10, card->mmio_base + CRTCD); /* clear = 1 */
+ writel(card->regs.besglobctl , card->mmio_base + BESGLOBCTL);
}
static void disable_irq(mga_card_t * card){
-
- writeb(0x11, card->mmio_base + CRTCX);
- writeb(0x20, card->mmio_base + CRTCD); /* clear 0, enable off */
-
+ writeb(0x11, card->mmio_base + CRTCX);
+ writeb(0x20, card->mmio_base + CRTCD); /* clear 0, enable off */
}
static void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) {
-// static int frame=0;
-// static int counter=0;
- long int cc;
- mga_card_t * card = dev_id;
+// static int frame=0;
+// static int counter=0;
+ long int cc;
+ mga_card_t * card = dev_id;
-// printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT));
+// printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT));
- //printk("mga_interrupt #%d\n", irq);
+ //printk("mga_interrupt #%d\n", irq);
- // check whether the interrupt is really for us (irq sharing)
- if ( irq != -1 ) {
- cc = readl(card->mmio_base + STATUS);
- if ( ! (cc & 0x10) ) return; /* vsyncpen */
-// debug_irqcnt++;
- }
+ // check whether the interrupt is really for us (irq sharing)
+ if ( irq != -1 ) {
+ cc = readl(card->mmio_base + STATUS);
+ if ( ! (cc & 0x10) ) return; /* vsyncpen */
+// debug_irqcnt++;
+ }
-// if ( debug_irqignore ) {
-// debug_irqignore = 0;
+// if ( debug_irqignore ) {
+// debug_irqignore = 0;
-// frame=(frame+1)&1;
- card->regs.besctl = (card->regs.besctl & ~0x07000000) + (card->next_frame << 25);
- writel( card->regs.besctl, card->mmio_base + BESCTL );
+// frame=(frame+1)&1;
+ card->regs.besctl = (card->regs.besctl & ~0x07000000) + (card->next_frame << 25);
+ writel( card->regs.besctl, card->mmio_base + BESCTL );
#ifdef CRTC2
// sem pridat vyber obrazku !!!!
// i han echt kei ahnig was das obe heisse söll
- crtc2_frame_sel(card->next_frame);
+ crtc2_frame_sel(card->next_frame);
#endif
#if 0
- ++counter;
- if(!(counter&63)){
- printk("mga irq counter = %d\n",counter);
- }
+ ++counter;
+ if(!(counter&63)){
+ printk("mga irq counter = %d\n",counter);
+ }
#endif
-// } else {
-// debug_irqignore = 1;
-// }
-
- if ( irq != -1 ) {
- writeb( 0x11, card->mmio_base + CRTCX);
- writeb( 0, card->mmio_base + CRTCD );
- writeb( 0x10, card->mmio_base + CRTCD );
- }
-
-// writel( card->regs.besglobctl, card->mmio_base + BESGLOBCTL);
+// } else {
+// debug_irqignore = 1;
+// }
+ if ( irq != -1 ) {
+ writeb( 0x11, card->mmio_base + CRTCX);
+ writeb( 0, card->mmio_base + CRTCD );
+ writeb( 0x10, card->mmio_base + CRTCD );
+ }
- return;
+// writel( card->regs.besglobctl, card->mmio_base + BESGLOBCTL);
+ return;
}
#endif
static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
- int frame, result;
- uint32_t tmp;
- mga_card_t * card = (mga_card_t *) file->private_data;
-
- switch(cmd)
- {
- case MGA_VID_GET_VERSION:
- tmp = MGA_VID_VERSION;
- if (copy_to_user((uint32_t *) arg, &tmp, sizeof(uint32_t))) {
- printk(KERN_ERR "mga_vid: failed copy %p to userspace %p\n", &tmp, (uint32_t *) arg);
- return -EFAULT;
- }
- break;
-
- case MGA_VID_CONFIG:
- //FIXME remove
-// printk(KERN_DEBUG "mga_vid: vcount = %d\n",readl(card->mmio_base + VCOUNT));
+ int frame, result;
+ uint32_t tmp;
+ mga_card_t * card = (mga_card_t *) file->private_data;
+
+ switch(cmd)
+ {
+ case MGA_VID_GET_VERSION:
+ tmp = MGA_VID_VERSION;
+ if (copy_to_user((uint32_t *) arg, &tmp, sizeof(uint32_t))) {
+ printk(KERN_ERR "mga_vid: failed copy %p to userspace %p\n", &tmp, (uint32_t *) arg);
+ return -EFAULT;
+ }
+ break;
+
+ case MGA_VID_CONFIG:
+ //FIXME remove
+// printk(KERN_DEBUG "mga_vid: vcount = %d\n",readl(card->mmio_base + VCOUNT));
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga_vid: mmio_base = %p\n",card->mmio_base);
- printk(KERN_DEBUG "mga_vid: mem_base = %08x\n",card->mem_base);
- //FIXME remove
+ printk(KERN_DEBUG "mga_vid: mmio_base = %p\n",card->mmio_base);
+ printk(KERN_DEBUG "mga_vid: mem_base = %08x\n",card->mem_base);
+ //FIXME remove
- printk(KERN_DEBUG "mga_vid: Received configuration\n");
+ printk(KERN_DEBUG "mga_vid: Received configuration\n");
#endif
- if(copy_from_user(&card->config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t)))
- {
- printk(KERN_ERR "mga_vid: failed copy from userspace\n");
- return -EFAULT;
- }
- if(card->config.version != MGA_VID_VERSION){
- printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,card->config.version);
- return -EFAULT;
- }
-
- if(card->config.frame_size==0 || card->config.frame_size>1024*768*2){
- printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",card->config.frame_size);
- return -EFAULT;
- }
-
- if(card->config.num_frames<1 || card->config.num_frames>4){
- printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",card->config.num_frames);
- return -EFAULT;
- }
-
- card->src_base = (card->ram_size * 0x100000 - card->config.num_frames * card->config.frame_size - card->top_reserved);
- if(card->src_base<0){
- printk(KERN_ERR "mga_vid: not enough memory for frames!\n");
- return -EFAULT;
- }
- card->src_base &= (~0xFFFF); // 64k boundary
+ if(copy_from_user(&card->config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t)))
+ {
+ printk(KERN_ERR "mga_vid: failed copy from userspace\n");
+ return -EFAULT;
+ }
+ if(card->config.version != MGA_VID_VERSION){
+ printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,card->config.version);
+ return -EFAULT;
+ }
+
+ if(card->config.frame_size==0 || card->config.frame_size>1024*768*2){
+ printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",card->config.frame_size);
+ return -EFAULT;
+ }
+
+ if(card->config.num_frames<1 || card->config.num_frames>4){
+ printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",card->config.num_frames);
+ return -EFAULT;
+ }
+
+ card->src_base = (card->ram_size * 0x100000 - card->config.num_frames * card->config.frame_size - card->top_reserved);
+ if(card->src_base<0){
+ printk(KERN_ERR "mga_vid: not enough memory for frames!\n");
+ return -EFAULT;
+ }
+ card->src_base &= (~0xFFFF); // 64k boundary
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", card->src_base);
+ printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", card->src_base);
#endif
- if (card->is_g400)
- card->config.card_type = MGA_G400;
- else
- card->config.card_type = MGA_G200;
+ if (card->is_g400)
+ card->config.card_type = MGA_G400;
+ else
+ card->config.card_type = MGA_G200;
- card->config.ram_size = card->ram_size;
+ card->config.ram_size = card->ram_size;
- if (copy_to_user((mga_vid_config_t *) arg, &card->config, sizeof(mga_vid_config_t)))
- {
- printk(KERN_ERR "mga_vid: failed copy to userspace\n");
- return -EFAULT;
- }
+ if (copy_to_user((mga_vid_config_t *) arg, &card->config, sizeof(mga_vid_config_t)))
+ {
+ printk(KERN_ERR "mga_vid: failed copy to userspace\n");
+ return -EFAULT;
+ }
- result = mga_vid_set_config(card);
- if(!result) card->configured=1;
- return result;
- break;
+ result = mga_vid_set_config(card);
+ if(!result) card->configured=1;
+ return result;
+ break;
- case MGA_VID_ON:
+ case MGA_VID_ON:
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga_vid: Video ON\n");
+ printk(KERN_DEBUG "mga_vid: Video ON\n");
#endif
- card->vid_src_ready = 1;
- if(card->vid_overlay_on)
- {
- card->regs.besctl |= 1;
- mga_vid_write_regs(card, 0);
- }
+ card->vid_src_ready = 1;
+ if(card->vid_overlay_on)
+ {
+ card->regs.besctl |= 1;
+ mga_vid_write_regs(card, 0);
+ }
#ifdef MGA_ALLOW_IRQ
- if ( card->irq != -1 ) enable_irq(card);
+ if ( card->irq != -1 ) enable_irq(card);
#endif
- card->next_frame=0;
- break;
+ card->next_frame=0;
+ break;
- case MGA_VID_OFF:
+ case MGA_VID_OFF:
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n");
+ printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n");
#endif
- card->vid_src_ready = 0;
+ card->vid_src_ready = 0;
#ifdef MGA_ALLOW_IRQ
- if ( card->irq != -1 ) disable_irq(card);
+ if ( card->irq != -1 ) disable_irq(card);
#endif
- card->regs.besctl &= ~1;
- card->regs.besglobctl &= ~(1<<6); // UYVY format selected
- mga_vid_write_regs(card, 0);
- break;
-
- case MGA_VID_FSEL:
- if(copy_from_user(&frame,(int *) arg,sizeof(int)))
- {
- printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n");
- return -EFAULT;
- }
-
- mga_vid_frame_sel(card, frame);
- break;
-
- case MGA_VID_GET_LUMA:
- //tmp = card->regs.beslumactl;
- //tmp = (tmp&0xFFFF0000) | (((tmp&0xFFFF) - 0x80)&0xFFFF);
- tmp = (card->brightness << 16) | (card->contrast&0xFFFF);
-
- if (copy_to_user((uint32_t *) arg, &tmp, sizeof(uint32_t)))
- {
- printk(KERN_ERR "mga_vid: failed copy %p to userspace %p\n",
- &tmp, (uint32_t *) arg);
- return -EFAULT;
- }
- break;
-
- case MGA_VID_SET_LUMA:
- tmp = arg;
- card->brightness=tmp>>16; card->contrast=tmp&0xFFFF;
- //card->regs.beslumactl = (tmp&0xFFFF0000) | ((tmp + 0x80)&0xFFFF);
- card->regs.beslumactl = (card->brightness << 16) | ((card->contrast+0x80)&0xFFFF);
- mga_vid_write_regs(card, 0);
- break;
-
- default:
- printk(KERN_ERR "mga_vid: Invalid ioctl\n");
- return -EINVAL;
- }
-
- return 0;
+ card->regs.besctl &= ~1;
+ card->regs.besglobctl &= ~(1<<6); // UYVY format selected
+ mga_vid_write_regs(card, 0);
+ break;
+
+ case MGA_VID_FSEL:
+ if(copy_from_user(&frame,(int *) arg,sizeof(int)))
+ {
+ printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n");
+ return -EFAULT;
+ }
+
+ mga_vid_frame_sel(card, frame);
+ break;
+
+ case MGA_VID_GET_LUMA:
+ //tmp = card->regs.beslumactl;
+ //tmp = (tmp&0xFFFF0000) | (((tmp&0xFFFF) - 0x80)&0xFFFF);
+ tmp = (card->brightness << 16) | (card->contrast&0xFFFF);
+
+ if (copy_to_user((uint32_t *) arg, &tmp, sizeof(uint32_t)))
+ {
+ printk(KERN_ERR "mga_vid: failed copy %p to userspace %p\n",
+ &tmp, (uint32_t *) arg);
+ return -EFAULT;
+ }
+ break;
+
+ case MGA_VID_SET_LUMA:
+ tmp = arg;
+ card->brightness=tmp>>16; card->contrast=tmp&0xFFFF;
+ //card->regs.beslumactl = (tmp&0xFFFF0000) | ((tmp + 0x80)&0xFFFF);
+ card->regs.beslumactl = (card->brightness << 16) | ((card->contrast+0x80)&0xFFFF);
+ mga_vid_write_regs(card, 0);
+ break;
+
+ default:
+ printk(KERN_ERR "mga_vid: Invalid ioctl\n");
+ return -EINVAL;
+ }
+
+ return 0;
}
static void cards_init(mga_card_t * card, struct pci_dev * dev, int card_number, int is_g400);
@@ -1333,67 +1326,67 @@ static void cards_init(mga_card_t * card, struct pci_dev * dev, int card_number,
// returns the number of found cards
static int mga_vid_find_card(void)
{
- struct pci_dev *dev = NULL;
- char *mga_dev_name;
- mga_card_t * card;
-
- while((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_ANY_ID, dev)))
- {
- mga_dev_name = "";
- mga_cards_num++;
- if(mga_cards_num == MGA_MAX_CARDS)
- {
- printk(KERN_WARNING "mga_vid: Trying to initialize more than %d cards\n",MGA_MAX_CARDS);
- mga_cards_num--;
- break;
- }
-
- card = kmalloc(sizeof(mga_card_t), GFP_KERNEL);
- if(!card)
- {
- printk(KERN_ERR "mga_vid: memory allocation failed\n");
- mga_cards_num--;
- break;
- }
-
- mga_cards[mga_cards_num - 1] = card;
-
- switch(dev->device) {
- case PCI_DEVICE_ID_MATROX_G550:
- mga_dev_name = "MGA G550";
- printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
- cards_init(card, dev, mga_cards_num - 1, 1);
- break;
- case PCI_DEVICE_ID_MATROX_G400:
- mga_dev_name = "MGA G400/G450";
- printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
- cards_init(card, dev, mga_cards_num - 1, 1);
- break;
- case PCI_DEVICE_ID_MATROX_G200_AGP:
- mga_dev_name = "MGA G200 AGP";
- printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
- cards_init(card, dev, mga_cards_num - 1, 0);
- break;
- case PCI_DEVICE_ID_MATROX_G200_PCI:
- mga_dev_name = "MGA G200";
- printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
- cards_init(card, dev, mga_cards_num - 1, 0);
- break;
- default:
- mga_cards_num--;
- printk(KERN_INFO "mga_vid: ignoring matrox device (%d) at %s [%s]\n", dev->device, dev->slot_name, dev->name);
- break;
- }
- }
-
- if(!mga_cards_num)
- {
- printk(KERN_ERR "mga_vid: No supported cards found\n");
- } else {
- printk(KERN_INFO "mga_vid: %d supported cards found\n", mga_cards_num);
- }
-
- return mga_cards_num;
+ struct pci_dev *dev = NULL;
+ char *mga_dev_name;
+ mga_card_t * card;
+
+ while((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_ANY_ID, dev)))
+ {
+ mga_dev_name = "";
+ mga_cards_num++;
+ if(mga_cards_num == MGA_MAX_CARDS)
+ {
+ printk(KERN_WARNING "mga_vid: Trying to initialize more than %d cards\n",MGA_MAX_CARDS);
+ mga_cards_num--;
+ break;
+ }
+
+ card = kmalloc(sizeof(mga_card_t), GFP_KERNEL);
+ if(!card)
+ {
+ printk(KERN_ERR "mga_vid: memory allocation failed\n");
+ mga_cards_num--;
+ break;
+ }
+
+ mga_cards[mga_cards_num - 1] = card;
+
+ switch(dev->device) {
+ case PCI_DEVICE_ID_MATROX_G550:
+ mga_dev_name = "MGA G550";
+ printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
+ cards_init(card, dev, mga_cards_num - 1, 1);
+ break;
+ case PCI_DEVICE_ID_MATROX_G400:
+ mga_dev_name = "MGA G400/G450";
+ printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
+ cards_init(card, dev, mga_cards_num - 1, 1);
+ break;
+ case PCI_DEVICE_ID_MATROX_G200_AGP:
+ mga_dev_name = "MGA G200 AGP";
+ printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
+ cards_init(card, dev, mga_cards_num - 1, 0);
+ break;
+ case PCI_DEVICE_ID_MATROX_G200_PCI:
+ mga_dev_name = "MGA G200";
+ printk(KERN_INFO "mga_vid: Found %s at %s [%s]\n", mga_dev_name, dev->slot_name, dev->name);
+ cards_init(card, dev, mga_cards_num - 1, 0);
+ break;
+ default:
+ mga_cards_num--;
+ printk(KERN_INFO "mga_vid: ignoring matrox device (%d) at %s [%s]\n", dev->device, dev->slot_name, dev->name);
+ break;
+ }
+ }
+
+ if(!mga_cards_num)
+ {
+ printk(KERN_ERR "mga_vid: No supported cards found\n");
+ } else {
+ printk(KERN_INFO "mga_vid: %d supported cards found\n", mga_cards_num);
+ }
+
+ return mga_cards_num;
}
static void mga_param_buff_fill( mga_card_t * card )
@@ -1417,287 +1410,284 @@ static void mga_param_buff_fill( mga_card_t * card )
static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos)
{
- uint32_t size;
- mga_card_t * card = (mga_card_t *) file->private_data;
-
- if(!card->param_buff) return -ESPIPE;
- if(!(*ppos)) mga_param_buff_fill(card);
- if(*ppos >= card->param_buff_len) return 0;
- size = min(count,card->param_buff_len-(uint32_t)(*ppos));
- memcpy(buf,card->param_buff,size);
- *ppos += size;
- return size;
+ uint32_t size;
+ mga_card_t * card = (mga_card_t *) file->private_data;
+
+ if(!card->param_buff) return -ESPIPE;
+ if(!(*ppos)) mga_param_buff_fill(card);
+ if(*ppos >= card->param_buff_len) return 0;
+ size = min(count,card->param_buff_len-(uint32_t)(*ppos));
+ memcpy(buf,card->param_buff,size);
+ *ppos += size;
+ return size;
}
static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
{
- mga_card_t * card = (mga_card_t *) file->private_data;
-
- if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0)
- {
- short brightness;
- brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10);
- if (brightness>127 || brightness<-128) { brightness=0;}
-// printk(KERN_DEBUG "mga_vid: brightness modified ( %d ) \n",brightness);
- card->brightness=brightness;
- } else
- if(memcmp(buf,PARAM_CONTRAST,min(count,strlen(PARAM_CONTRAST))) == 0)
- {
- short contrast;
- contrast=simple_strtol(&buf[strlen(PARAM_CONTRAST)],NULL,10);
- if (contrast>127 || contrast<-128) { contrast=0;}
-// printk(KERN_DEBUG "mga_vid: contrast modified ( %d ) \n",contrast);
- card->contrast=contrast;
- } else
-
- if(memcmp(buf,PARAM_BLACKIE,min(count,strlen(PARAM_BLACKIE))) == 0)
- {
- short blackie;
- blackie=simple_strtol(&buf[strlen(PARAM_BLACKIE)],NULL,10);
-// printk(KERN_DEBUG "mga_vid: shadow mode: ( %d ) \n",blackie);
- card->regs.blackie=(blackie>0)?1:0;
- } else count = -EIO;
- // TODO: reset settings
- return count;
+ mga_card_t * card = (mga_card_t *) file->private_data;
+
+ if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0)
+ {
+ short brightness;
+ brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10);
+ if (brightness>127 || brightness<-128) { brightness=0;}
+// printk(KERN_DEBUG "mga_vid: brightness modified ( %d ) \n",brightness);
+ card->brightness=brightness;
+ } else
+ if(memcmp(buf,PARAM_CONTRAST,min(count,strlen(PARAM_CONTRAST))) == 0)
+ {
+ short contrast;
+ contrast=simple_strtol(&buf[strlen(PARAM_CONTRAST)],NULL,10);
+ if (contrast>127 || contrast<-128) { contrast=0;}
+// printk(KERN_DEBUG "mga_vid: contrast modified ( %d ) \n",contrast);
+ card->contrast=contrast;
+ } else
+
+ if(memcmp(buf,PARAM_BLACKIE,min(count,strlen(PARAM_BLACKIE))) == 0)
+ {
+ short blackie;
+ blackie=simple_strtol(&buf[strlen(PARAM_BLACKIE)],NULL,10);
+// printk(KERN_DEBUG "mga_vid: shadow mode: ( %d ) \n",blackie);
+ card->regs.blackie=(blackie>0)?1:0;
+ } else count = -EIO;
+ // TODO: reset settings
+ return count;
}
static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma)
{
- mga_card_t * card = (mga_card_t *) file->private_data;
+ mga_card_t * card = (mga_card_t *) file->private_data;
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n");
+ printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n");
#endif
- if(!card->configured)
- {
- printk(KERN_ERR "mga_vid: card is not configured, cannot mmap\n");
- return -EAGAIN;
- }
+ if(!card->configured)
+ {
+ printk(KERN_ERR "mga_vid: card is not configured, cannot mmap\n");
+ return -EAGAIN;
+ }
- if(remap_page_range(vma->vm_start, card->mem_base + card->src_base,
- vma->vm_end - vma->vm_start, vma->vm_page_prot))
- {
- printk(KERN_ERR "mga_vid: error mapping video memory\n");
- return -EAGAIN;
- }
+ if(remap_page_range(vma->vm_start, card->mem_base + card->src_base,
+ vma->vm_end - vma->vm_start, vma->vm_page_prot))
+ {
+ printk(KERN_ERR "mga_vid: error mapping video memory\n");
+ return -EAGAIN;
+ }
- return 0;
+ return 0;
}
static int mga_vid_release(struct inode *inode, struct file *file)
{
- mga_card_t * card;
+ mga_card_t * card;
- //Close the window just in case
+ //Close the window just in case
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga_vid: Video OFF (release)\n");
+ printk(KERN_DEBUG "mga_vid: Video OFF (release)\n");
#endif
- card = (mga_card_t *) file->private_data;
+ card = (mga_card_t *) file->private_data;
- card->vid_src_ready = 0;
- card->regs.besctl &= ~1;
- card->regs.besglobctl &= ~(1<<6); // UYVY format selected
-// card->config.colkey_on=0; //!!!
- mga_vid_write_regs(card, 1);
- card->vid_in_use = 0;
+ card->vid_src_ready = 0;
+ card->regs.besctl &= ~1;
+ card->regs.besglobctl &= ~(1<<6); // UYVY format selected
+// card->config.colkey_on=0; //!!!
+ mga_vid_write_regs(card, 1);
+ card->vid_in_use = 0;
- MOD_DEC_USE_COUNT;
- return 0;
+ MOD_DEC_USE_COUNT;
+ return 0;
}
static long long mga_vid_lseek(struct file *file, long long offset, int origin)
{
- return -ESPIPE;
+ return -ESPIPE;
}
static int mga_vid_open(struct inode *inode, struct file *file)
{
- mga_card_t * card;
+ mga_card_t * card;
- int minor = MINOR(inode->i_rdev);
+ int minor = MINOR(inode->i_rdev);
- if(!file->private_data)
- {
- // we are not using devfs, use the minor
- // number to specify the card we are using
+ if(!file->private_data)
+ {
+ // we are not using devfs, use the minor
+ // number to specify the card we are using
- // we don't have that many cards
- if(minor >= mga_cards_num)
- return -ENXIO;
+ // we don't have that many cards
+ if(minor >= mga_cards_num)
+ return -ENXIO;
- file->private_data = mga_cards[minor];
+ file->private_data = mga_cards[minor];
#ifdef MP_DEBUG
- printk(KERN_DEBUG "mga_vid: Not using devfs\n");
+ printk(KERN_DEBUG "mga_vid: Not using devfs\n");
#endif
- }
+ }
#ifdef MP_DEBUG
- else {
- printk(KERN_DEBUG "mga_vid: Using devfs\n");
- }
+ else {
+ printk(KERN_DEBUG "mga_vid: Using devfs\n");
+ }
#endif
- card = (mga_card_t *) file->private_data;
+ card = (mga_card_t *) file->private_data;
- if(card->vid_in_use == 1)
- return -EBUSY;
+ if(card->vid_in_use == 1)
+ return -EBUSY;
- card->vid_in_use = 1;
- MOD_INC_USE_COUNT;
- return 0;
+ card->vid_in_use = 1;
+ MOD_INC_USE_COUNT;
+ return 0;
}
#if LINUX_VERSION_CODE >= 0x020400
static struct file_operations mga_vid_fops =
{
- llseek: mga_vid_lseek,
- read: mga_vid_read,
- write: mga_vid_write,
- ioctl: mga_vid_ioctl,
- mmap: mga_vid_mmap,
- open: mga_vid_open,
- release: mga_vid_release
+ llseek: mga_vid_lseek,
+ read: mga_vid_read,
+ write: mga_vid_write,
+ ioctl: mga_vid_ioctl,
+ mmap: mga_vid_mmap,
+ open: mga_vid_open,
+ release: mga_vid_release
};
#else
static struct file_operations mga_vid_fops =
{
- mga_vid_lseek,
- mga_vid_read,
- mga_vid_write,
- NULL,
- NULL,
- mga_vid_ioctl,
- mga_vid_mmap,
- mga_vid_open,
- NULL,
- mga_vid_release
+ mga_vid_lseek,
+ mga_vid_read,
+ mga_vid_write,
+ NULL,
+ NULL,
+ mga_vid_ioctl,
+ mga_vid_mmap,
+ mga_vid_open,
+ NULL,
+ mga_vid_release
};
#endif
static void cards_init(mga_card_t * card, struct pci_dev * dev, int card_number, int is_g400)
{
- unsigned int card_option;
+ unsigned int card_option;
// temp buffer for device filename creation used only by devfs
#ifdef CONFIG_DEVFS_FS
- char buffer[16];
+ char buffer[16];
#endif
- memset(card,0,sizeof(mga_card_t));
- card->irq = -1;
+ memset(card,0,sizeof(mga_card_t));
+ card->irq = -1;
- card->pci_dev = dev;
- card->irq = dev->irq;
- card->is_g400 = is_g400;
+ card->pci_dev = dev;
+ card->irq = dev->irq;
+ card->is_g400 = is_g400;
- card->param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL);
- if(card->param_buff) card->param_buff_size = PARAM_BUFF_SIZE;
+ card->param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL);
+ if(card->param_buff) card->param_buff_size = PARAM_BUFF_SIZE;
- card->brightness = mga_brightness[card_number];
- card->contrast = mga_contrast[card_number];
- card->top_reserved = mga_top_reserved[card_number];
+ card->brightness = mga_brightness[card_number];
+ card->contrast = mga_contrast[card_number];
+ card->top_reserved = mga_top_reserved[card_number];
#if LINUX_VERSION_CODE >= 0x020300
- card->mmio_base = ioremap_nocache(dev->resource[1].start,0x4000);
- card->mem_base = dev->resource[0].start;
+ card->mmio_base = ioremap_nocache(dev->resource[1].start,0x4000);
+ card->mem_base = dev->resource[0].start;
#else
- card->mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000);
- card->mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK;
+ card->mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000);
+ card->mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK;
#endif
- printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08X\n", card->mmio_base, card->irq, card->mem_base);
+ printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08X\n", card->mmio_base, card->irq, card->mem_base);
- pci_read_config_dword(dev, 0x40, &card_option);
- printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
- (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
+ pci_read_config_dword(dev, 0x40, &card_option);
+ printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
+ (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
- if (mga_ram_size[card_number]) {
- printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size[card_number]);
- card->ram_size=mga_ram_size[card_number];
- } else {
+ if (mga_ram_size[card_number]) {
+ printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size[card_number]);
+ card->ram_size=mga_ram_size[card_number];
+ } else {
#ifdef MGA_MEMORY_SIZE
- card->ram_size = MGA_MEMORY_SIZE;
- printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) card->ram_size);
-
+ card->ram_size = MGA_MEMORY_SIZE;
+ printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) card->ram_size);
#else
-
- if (card->is_g400){
- switch((card_option>>10)&0x17){
- // SDRAM:
- case 0x00:
- case 0x04: card->ram_size = 16; break;
- case 0x03:
- case 0x05: card->ram_size = 32; break;
- // SGRAM:
- case 0x10:
- case 0x14: card->ram_size = 32; break;
- case 0x11:
- case 0x12: card->ram_size = 16; break;
- default:
- card->ram_size = 16;
- printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!");
- }
- /* Check for buggy 16MB cards reporting 32 MB */
- if(card->ram_size != 16 &&
- (dev->subsystem_device == PCI_SUBSYSTEM_ID_MATROX_G400_16MB_SDRAM ||
- dev->subsystem_device == PCI_SUBSYSTEM_ID_MATROX_G400_16MB_SGRAM ||
- dev->subsystem_device == PCI_SUBSYSTEM_ID_MATROX_G400_DH_16MB))
- {
- printk(KERN_INFO "mga_vid: Detected 16MB card reporting %d MB RAMSIZE, overriding\n", card->ram_size);
- card->ram_size = 16;
- }
- }else{
- switch((card_option>>10)&0x17){
-// case 0x10:
-// case 0x13: card->ram_size = 8; break;
- default: card->ram_size = 8;
- }
- }
+ if (card->is_g400){
+ switch((card_option>>10)&0x17){
+ // SDRAM:
+ case 0x00:
+ case 0x04: card->ram_size = 16; break;
+ case 0x03:
+ case 0x05: card->ram_size = 32; break;
+ // SGRAM:
+ case 0x10:
+ case 0x14: card->ram_size = 32; break;
+ case 0x11:
+ case 0x12: card->ram_size = 16; break;
+ default:
+ card->ram_size = 16;
+ printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!");
+ }
+ /* Check for buggy 16MB cards reporting 32 MB */
+ if(card->ram_size != 16 &&
+ (dev->subsystem_device == PCI_SUBSYSTEM_ID_MATROX_G400_16MB_SDRAM ||
+ dev->subsystem_device == PCI_SUBSYSTEM_ID_MATROX_G400_16MB_SGRAM ||
+ dev->subsystem_device == PCI_SUBSYSTEM_ID_MATROX_G400_DH_16MB))
+ {
+ printk(KERN_INFO "mga_vid: Detected 16MB card reporting %d MB RAMSIZE, overriding\n", card->ram_size);
+ card->ram_size = 16;
+ }
+ }else{
+ switch((card_option>>10)&0x17){
+// case 0x10:
+// case 0x13: card->ram_size = 8; break;
+ default: card->ram_size = 8;
+ }
+ }
#if 0
-// printk("List resources -----------\n");
- for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){
- struct resource *res=&dev->resource[temp];
- if(res->flags){
- int size=(1+res->end-res->start)>>20;
- printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags);
- if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){
- if(size>card->ram_size && size<=64) card->ram_size=size;
- }
- }
- }
+// printk("List resources -----------\n");
+ for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){
+ struct resource *res=&dev->resource[temp];
+ if(res->flags){
+ int size=(1+res->end-res->start)>>20;
+ printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags);
+ if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){
+ if(size>card->ram_size && size<=64) card->ram_size=size;
+ }
+ }
+ }
#endif
- printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) card->ram_size);
+ printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) card->ram_size);
#endif
- }
+ }
#ifdef MGA_ALLOW_IRQ
- if ( card->irq != -1 ) {
- int tmp = request_irq(card->irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", card);
- if ( tmp ) {
- printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", card->irq, tmp);
- card->irq=-1;
- } else {
- printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", card->irq);
- }
- } else {
- printk(KERN_INFO "syncfb (mga): No valid irq was found\n");
- card->irq=-1;
- }
+ if ( card->irq != -1 ) {
+ int tmp = request_irq(card->irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", card);
+ if ( tmp ) {
+ printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", card->irq, tmp);
+ card->irq=-1;
+ } else {
+ printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", card->irq);
+ }
+ } else {
+ printk(KERN_INFO "syncfb (mga): No valid irq was found\n");
+ card->irq=-1;
+ }
#else
- printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n");
- card->irq=-1;
+ printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n");
+ card->irq=-1;
#endif
- // register devfs, let the kernel give us major and minor numbers
+ // register devfs, let the kernel give us major and minor numbers
#ifdef CONFIG_DEVFS_FS
- snprintf(buffer, 16, "mga_vid%d", card_number);
- card->dev_handle = devfs_register(NULL, buffer, DEVFS_FL_AUTO_DEVNUM,
- 0, 0,
- S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IFCHR,
- &mga_vid_fops, card);
+ snprintf(buffer, 16, "mga_vid%d", card_number);
+ card->dev_handle = devfs_register(NULL, buffer, DEVFS_FL_AUTO_DEVNUM,
+ 0, 0,
+ S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IFCHR,
+ &mga_vid_fops, card);
#endif
-
}
/*
@@ -1706,83 +1696,83 @@ static void cards_init(mga_card_t * card, struct pci_dev * dev, int card_number,
static int mga_vid_initialize(void)
{
- int i;
-
-// printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n");
- printk(KERN_INFO "Matrox MGA G200/G400/G450/G550 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
-
- for(i = 0; i < MGA_MAX_CARDS; i++)
- {
- if (mga_ram_size[i]) {
- if (mga_ram_size[i]<4 || mga_ram_size[i]>64) {
- printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size[i]);
- return -EINVAL;
- }
- }
- }
-
- if(register_chrdev(major, "mga_vid", &mga_vid_fops))
- {
- printk(KERN_ERR "mga_vid: unable to get major: %d\n", major);
- return -EIO;
- }
-
- if (!mga_vid_find_card())
- {
- printk(KERN_ERR "mga_vid: no supported devices found\n");
- unregister_chrdev(major, "mga_vid");
- return -EINVAL;
- }
+ int i;
+
+// printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n");
+ printk(KERN_INFO "Matrox MGA G200/G400/G450/G550 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
+
+ for(i = 0; i < MGA_MAX_CARDS; i++)
+ {
+ if (mga_ram_size[i]) {
+ if (mga_ram_size[i]<4 || mga_ram_size[i]>64) {
+ printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size[i]);
+ return -EINVAL;
+ }
+ }
+ }
+
+ if(register_chrdev(major, "mga_vid", &mga_vid_fops))
+ {
+ printk(KERN_ERR "mga_vid: unable to get major: %d\n", major);
+ return -EIO;
+ }
+
+ if (!mga_vid_find_card())
+ {
+ printk(KERN_ERR "mga_vid: no supported devices found\n");
+ unregister_chrdev(major, "mga_vid");
+ return -EINVAL;
+ }
#ifdef CONFIG_DEVFS_FS
- else {
- // we assume that this always succeedes
- dev_handle = devfs_register(NULL, "mga_vid", DEVFS_FL_AUTO_DEVNUM,
- 0,0,
- S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IFCHR,
- &mga_vid_fops, mga_cards[0]);
- }
+ else {
+ // we assume that this always succeedes
+ dev_handle = devfs_register(NULL, "mga_vid", DEVFS_FL_AUTO_DEVNUM,
+ 0,0,
+ S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IFCHR,
+ &mga_vid_fops, mga_cards[0]);
+ }
#endif
- return 0;
+ return 0;
}
int init_module(void)
{
- return mga_vid_initialize();
+ return mga_vid_initialize();
}
void cleanup_module(void)
{
- int i;
- mga_card_t * card;
-
- for (i = 0; i < MGA_MAX_CARDS; i++)
- {
- card = mga_cards[i];
- if(card)
- {
+ int i;
+ mga_card_t * card;
+
+ for (i = 0; i < MGA_MAX_CARDS; i++)
+ {
+ card = mga_cards[i];
+ if(card)
+ {
#ifdef MGA_ALLOW_IRQ
- if (card->irq != -1)
- free_irq(card->irq, &(card->irq));
+ if (card->irq != -1)
+ free_irq(card->irq, &(card->irq));
#endif
- if(card->mmio_base)
- iounmap(card->mmio_base);
- if(card->param_buff)
- kfree(card->param_buff);
+ if(card->mmio_base)
+ iounmap(card->mmio_base);
+ if(card->param_buff)
+ kfree(card->param_buff);
#ifdef CONFIG_DEVFS_FS
- if(card->dev_handle) devfs_unregister(card->dev_handle);
+ if(card->dev_handle) devfs_unregister(card->dev_handle);
#endif
- kfree(card);
- mga_cards[i]=NULL;
- }
- }
+ kfree(card);
+ mga_cards[i]=NULL;
+ }
+ }
- //FIXME turn off BES
- printk(KERN_INFO "mga_vid: Cleaning up module\n");
+ //FIXME turn off BES
+ printk(KERN_INFO "mga_vid: Cleaning up module\n");
#ifdef CONFIG_DEVFS_FS
- if(dev_handle) devfs_unregister(dev_handle);
+ if(dev_handle) devfs_unregister(dev_handle);
#endif
- unregister_chrdev(major, "mga_vid");
+ unregister_chrdev(major, "mga_vid");
}
diff --git a/drivers/mga_vid_test.c b/drivers/mga_vid_test.c
index 05f41dbdf2..8555905a46 100644
--- a/drivers/mga_vid_test.c
+++ b/drivers/mga_vid_test.c
@@ -44,192 +44,192 @@ uint8_t cb_image[SRC_IMAGE_WIDTH * SRC_IMAGE_HEIGHT];
void
write_frame_g200(uint8_t *y,uint8_t *cr, uint8_t *cb)
{
- uint8_t *dest;
- uint32_t bespitch,h,w;
-
- dest = mga_vid_base;
- bespitch = (config.src_width + 31) & ~31;
-
- for(h=0; h < config.src_height; h++)
- {
- memcpy(dest, y, config.src_width);
- y += config.src_width;
- dest += bespitch;
- }
-
- for(h=0; h < config.src_height/2; h++)
- {
- for(w=0; w < config.src_width/2; w++)
- {
- *dest++ = *cb++;
- *dest++ = *cr++;
- }
- dest += bespitch - config.src_width;
- }
+ uint8_t *dest;
+ uint32_t bespitch,h,w;
+
+ dest = mga_vid_base;
+ bespitch = (config.src_width + 31) & ~31;
+
+ for(h=0; h < config.src_height; h++)
+ {
+ memcpy(dest, y, config.src_width);
+ y += config.src_width;
+ dest += bespitch;
+ }
+
+ for(h=0; h < config.src_height/2; h++)
+ {
+ for(w=0; w < config.src_width/2; w++)
+ {
+ *dest++ = *cb++;
+ *dest++ = *cr++;
+ }
+ dest += bespitch - config.src_width;
+ }
}
void
write_frame_g400(uint8_t *y,uint8_t *cr, uint8_t *cb)
{
- uint8_t *dest;
- uint32_t bespitch,h;
-
- dest = mga_vid_base;
- bespitch = (config.src_width + 31) & ~31;
-
- for(h=0; h < config.src_height; h++)
- {
- memcpy(dest, y, config.src_width);
- y += config.src_width;
- dest += bespitch;
- }
-
- for(h=0; h < config.src_height/2; h++)
- {
- memcpy(dest, cb, config.src_width/2);
- cb += config.src_width/2;
- dest += bespitch/2;
- }
-
- for(h=0; h < config.src_height/2; h++)
- {
- memcpy(dest, cr, config.src_width/2);
- cr += config.src_width/2;
- dest += bespitch/2;
- }
+ uint8_t *dest;
+ uint32_t bespitch,h;
+
+ dest = mga_vid_base;
+ bespitch = (config.src_width + 31) & ~31;
+
+ for(h=0; h < config.src_height; h++)
+ {
+ memcpy(dest, y, config.src_width);
+ y += config.src_width;
+ dest += bespitch;
+ }
+
+ for(h=0; h < config.src_height/2; h++)
+ {
+ memcpy(dest, cb, config.src_width/2);
+ cb += config.src_width/2;
+ dest += bespitch/2;
+ }
+
+ for(h=0; h < config.src_height/2; h++)
+ {
+ memcpy(dest, cr, config.src_width/2);
+ cr += config.src_width/2;
+ dest += bespitch/2;
+ }
}
void write_frame(uint8_t *y,uint8_t *cr, uint8_t *cb)
{
- if(is_g400)
- write_frame_g400(y,cr,cb);
- else
- write_frame_g200(y,cr,cb);
+ if(is_g400)
+ write_frame_g400(y,cr,cb);
+ else
+ write_frame_g200(y,cr,cb);
}
void
draw_cool_pattern(void)
{
- int i,x,y;
-
- i = 0;
- for (y=0; y<config.src_height; y++) {
- for (x=0; x<config.src_width; x++) {
- y_image[i++] = x*x/2 + y*y/2 - 128;
- }
- }
-
- i = 0;
- for (y=0; y<config.src_height/2; y++)
- for (x=0; x<config.src_width/2; x++)
- {
- cr_image[i++] = x - 128;
- }
-
- i = 0;
- for (y=0; y<config.src_height/2; y++)
- for (x=0; x<config.src_width/2; x++)
- {
- cb_image[i++] = y - 128;
- }
+ int i,x,y;
+
+ i = 0;
+ for (y=0; y<config.src_height; y++) {
+ for (x=0; x<config.src_width; x++) {
+ y_image[i++] = x*x/2 + y*y/2 - 128;
+ }
+ }
+
+ i = 0;
+ for (y=0; y<config.src_height/2; y++)
+ for (x=0; x<config.src_width/2; x++)
+ {
+ cr_image[i++] = x - 128;
+ }
+
+ i = 0;
+ for (y=0; y<config.src_height/2; y++)
+ for (x=0; x<config.src_width/2; x++)
+ {
+ cb_image[i++] = y - 128;
+ }
}
void
draw_color_blend(void)
{
- int i,x,y;
-
- i = 0;
- for (y=0; y<config.src_height; y++) {
- for (x=0; x<config.src_width; x++) {
- y_image[i++] = 0;
- }
- }
-
- i = 0;
- for (y=0; y<config.src_height/2; y++)
- for (x=0; x<config.src_width/2; x++)
- {
- cr_image[i++] = x - 128;
- }
-
- i = 0;
- for (y=0; y<config.src_height/2; y++)
- for (x=0; x<config.src_width/2; x++)
- {
- cb_image[i++] = y - 128;
- }
+ int i,x,y;
+
+ i = 0;
+ for (y=0; y<config.src_height; y++) {
+ for (x=0; x<config.src_width; x++) {
+ y_image[i++] = 0;
+ }
+ }
+
+ i = 0;
+ for (y=0; y<config.src_height/2; y++)
+ for (x=0; x<config.src_width/2; x++)
+ {
+ cr_image[i++] = x - 128;
+ }
+
+ i = 0;
+ for (y=0; y<config.src_height/2; y++)
+ for (x=0; x<config.src_width/2; x++)
+ {
+ cb_image[i++] = y - 128;
+ }
}
int
main(void)
{
- int f;
-
- f = open("/dev/mga_vid",O_RDWR);
-
- if(f == -1)
- {
- fprintf(stderr,"Couldn't open driver\n");
- exit(1);
- }
-
- config.version = MGA_VID_VERSION;
- config.src_width = SRC_IMAGE_WIDTH;
- config.src_height= SRC_IMAGE_HEIGHT;
- config.dest_width = SRC_IMAGE_WIDTH;
- config.dest_height = SRC_IMAGE_HEIGHT;
- config.x_org= 10;
- config.y_org= 10;
- config.colkey_on = 0;
- config.format = MGA_VID_FORMAT_YV12;
- config.frame_size=SRC_IMAGE_WIDTH*SRC_IMAGE_HEIGHT*2;
- config.num_frames=1;
-
- if (ioctl(f,MGA_VID_CONFIG,&config))
- {
- perror("Error in config ioctl");
- }
-
- if (config.card_type == MGA_G200)
- {
- printf("Testing MGA G200 Backend Scaler with %d MB of RAM\n", config.ram_size);
- is_g400 = 0;
- }
- else
- {
- printf("Testing MGA G400 Backend Scaler with %d MB of RAM\n", config.ram_size);
- is_g400 = 1;
- }
-
- ioctl(f,MGA_VID_ON,0);
- mga_vid_base = (uint8_t*)mmap(0,256 * 4096,PROT_WRITE,MAP_SHARED,f,0);
- printf("mga_vid_base = %8p\n",mga_vid_base);
-
-
- //memset(y_image,80,256 * 128);
- //memset(cr_image,80,256/2 * 20);
- //memset(cb_image,80,256/2 * 20);
- write_frame(y_image,cr_image,cb_image);
- printf("(1) There should be a green square, offset by 10 pixels from\n"
- " the upper left corner displayed\n");
- sleep(3);
-
-
- draw_cool_pattern();
- write_frame(y_image,cr_image,cb_image);
- printf("(2) There should be a cool mosaic like pattern now.\n");
- sleep(3);
-
- draw_color_blend();
- write_frame(y_image,cr_image,cb_image);
- printf("(3) There should be a color blend with black, red, purple, blue\n"
- " corners (starting top left going CW)\n");
- sleep(3);
-
- ioctl(f,MGA_VID_OFF,0);
-
- close(f);
- return 0;
+ int f;
+
+ f = open("/dev/mga_vid",O_RDWR);
+
+ if(f == -1)
+ {
+ fprintf(stderr,"Couldn't open driver\n");
+ exit(1);
+ }
+
+ config.version = MGA_VID_VERSION;
+ config.src_width = SRC_IMAGE_WIDTH;
+ config.src_height= SRC_IMAGE_HEIGHT;
+ config.dest_width = SRC_IMAGE_WIDTH;
+ config.dest_height = SRC_IMAGE_HEIGHT;
+ config.x_org= 10;
+ config.y_org= 10;
+ config.colkey_on = 0;
+ config.format = MGA_VID_FORMAT_YV12;
+ config.frame_size=SRC_IMAGE_WIDTH*SRC_IMAGE_HEIGHT*2;
+ config.num_frames=1;
+
+ if (ioctl(f,MGA_VID_CONFIG,&config))
+ {
+ perror("Error in config ioctl");
+ }
+
+ if (config.card_type == MGA_G200)
+ {
+ printf("Testing MGA G200 Backend Scaler with %d MB of RAM\n", config.ram_size);
+ is_g400 = 0;
+ }
+ else
+ {
+ printf("Testing MGA G400 Backend Scaler with %d MB of RAM\n", config.ram_size);
+ is_g400 = 1;
+ }
+
+ ioctl(f,MGA_VID_ON,0);
+ mga_vid_base = (uint8_t*)mmap(0,256 * 4096,PROT_WRITE,MAP_SHARED,f,0);
+ printf("mga_vid_base = %8p\n",mga_vid_base);
+
+
+ //memset(y_image,80,256 * 128);
+ //memset(cr_image,80,256/2 * 20);
+ //memset(cb_image,80,256/2 * 20);
+ write_frame(y_image,cr_image,cb_image);
+ printf("(1) There should be a green square, offset by 10 pixels from\n"
+ " the upper left corner displayed\n");
+ sleep(3);
+
+
+ draw_cool_pattern();
+ write_frame(y_image,cr_image,cb_image);
+ printf("(2) There should be a cool mosaic like pattern now.\n");
+ sleep(3);
+
+ draw_color_blend();
+ write_frame(y_image,cr_image,cb_image);
+ printf("(3) There should be a color blend with black, red, purple, blue\n"
+ " corners (starting top left going CW)\n");
+ sleep(3);
+
+ ioctl(f,MGA_VID_OFF,0);
+
+ close(f);
+ return 0;
}
diff --git a/drivers/radeon.h b/drivers/radeon.h
index de04b54270..1fb2fd245c 100644
--- a/drivers/radeon.h
+++ b/drivers/radeon.h
@@ -20,645 +20,645 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
-#ifndef MPLAYER_RADEON_H
-#define MPLAYER_RADEON_H
+#ifndef MPLAYER_RADEON_H
+#define MPLAYER_RADEON_H
/* radeon PCI ids */
-#define PCI_DEVICE_ID_RADEON_QD 0x5144
-#define PCI_DEVICE_ID_RADEON_QE 0x5145
-#define PCI_DEVICE_ID_RADEON_QF 0x5146
-#define PCI_DEVICE_ID_RADEON_QG 0x5147
-#define PCI_DEVICE_ID_RADEON_QY 0x5159
-#define PCI_DEVICE_ID_RADEON_QZ 0x515A
-#define PCI_DEVICE_ID_RADEON_LY 0x4C59
-#define PCI_DEVICE_ID_RADEON_LZ 0x4C5A
-#define PCI_DEVICE_ID_RADEON_LW 0x4C57
-#define PCI_DEVICE_ID_R200_QL 0x514C
-#define PCI_DEVICE_ID_RV200_QW 0x5157
-#define PCI_DEVICE_ID_R200_BB 0x4242
-
-#define RADEON_REGSIZE 0x4000
-
-
-#define MM_INDEX 0x0000
-/* MM_INDEX bit constants */
-# define MM_APER 0x80000000
-#define MM_DATA 0x0004
-#define BUS_CNTL 0x0030
-/* BUS_CNTL bit constants */
-# define BUS_DBL_RESYNC 0x00000001
-# define BUS_MSTR_RESET 0x00000002
-# define BUS_FLUSH_BUF 0x00000004
-# define BUS_STOP_REQ_DIS 0x00000008
-# define BUS_ROTATION_DIS 0x00000010
-# define BUS_MASTER_DIS 0x00000040
-# define BUS_ROM_WRT_EN 0x00000080
-# define BUS_DIS_ROM 0x00001000
-# define BUS_PCI_READ_RETRY_EN 0x00002000
-# define BUS_AGP_AD_STEPPING_EN 0x00004000
-# define BUS_PCI_WRT_RETRY_EN 0x00008000
-# define BUS_MSTR_RD_MULT 0x00100000
-# define BUS_MSTR_RD_LINE 0x00200000
-# define BUS_SUSPEND 0x00400000
-# define LAT_16X 0x00800000
-# define BUS_RD_DISCARD_EN 0x01000000
-# define BUS_RD_ABORT_EN 0x02000000
-# define BUS_MSTR_WS 0x04000000
-# define BUS_PARKING_DIS 0x08000000
-# define BUS_MSTR_DISCONNECT_EN 0x10000000
-# define BUS_WRT_BURST 0x20000000
-# define BUS_READ_BURST 0x40000000
-# define BUS_RDY_READ_DLY 0x80000000
-#define HI_STAT 0x004C
-#define BUS_CNTL1 0x0034
-# define BUS_WAIT_ON_LOCK_EN (1 << 4)
-#define I2C_CNTL_0 0x0090
-# define I2C_DONE (1<<0)
-# define I2C_NACK (1<<1)
-# define I2C_HALT (1<<2)
-# define I2C_SOFT_RST (1<<5)
-# define I2C_DRIVE_EN (1<<6)
-# define I2C_DRIVE_SEL (1<<7)
-# define I2C_START (1<<8)
-# define I2C_STOP (1<<9)
-# define I2C_RECEIVE (1<<10)
-# define I2C_ABORT (1<<11)
-# define I2C_GO (1<<12)
-# define I2C_SEL (1<<16)
-# define I2C_EN (1<<17)
-#define I2C_CNTL_1 0x0094
-#define I2C_DATA 0x0098
-#define CONFIG_CNTL 0x00E0
+#define PCI_DEVICE_ID_RADEON_QD 0x5144
+#define PCI_DEVICE_ID_RADEON_QE 0x5145
+#define PCI_DEVICE_ID_RADEON_QF 0x5146
+#define PCI_DEVICE_ID_RADEON_QG 0x5147
+#define PCI_DEVICE_ID_RADEON_QY 0x5159
+#define PCI_DEVICE_ID_RADEON_QZ 0x515A
+#define PCI_DEVICE_ID_RADEON_LY 0x4C59
+#define PCI_DEVICE_ID_RADEON_LZ 0x4C5A
+#define PCI_DEVICE_ID_RADEON_LW 0x4C57
+#define PCI_DEVICE_ID_R200_QL 0x514C
+#define PCI_DEVICE_ID_RV200_QW 0x5157
+#define PCI_DEVICE_ID_R200_BB 0x4242
+
+#define RADEON_REGSIZE 0x4000
+
+
+#define MM_INDEX 0x0000
+/* MM_INDEX bit constants */
+# define MM_APER 0x80000000
+#define MM_DATA 0x0004
+#define BUS_CNTL 0x0030
+/* BUS_CNTL bit constants */
+# define BUS_DBL_RESYNC 0x00000001
+# define BUS_MSTR_RESET 0x00000002
+# define BUS_FLUSH_BUF 0x00000004
+# define BUS_STOP_REQ_DIS 0x00000008
+# define BUS_ROTATION_DIS 0x00000010
+# define BUS_MASTER_DIS 0x00000040
+# define BUS_ROM_WRT_EN 0x00000080
+# define BUS_DIS_ROM 0x00001000
+# define BUS_PCI_READ_RETRY_EN 0x00002000
+# define BUS_AGP_AD_STEPPING_EN 0x00004000
+# define BUS_PCI_WRT_RETRY_EN 0x00008000
+# define BUS_MSTR_RD_MULT 0x00100000
+# define BUS_MSTR_RD_LINE 0x00200000
+# define BUS_SUSPEND 0x00400000
+# define LAT_16X 0x00800000
+# define BUS_RD_DISCARD_EN 0x01000000
+# define BUS_RD_ABORT_EN 0x02000000
+# define BUS_MSTR_WS 0x04000000
+# define BUS_PARKING_DIS 0x08000000
+# define BUS_MSTR_DISCONNECT_EN 0x10000000
+# define BUS_WRT_BURST 0x20000000
+# define BUS_READ_BURST 0x40000000
+# define BUS_RDY_READ_DLY 0x80000000
+#define HI_STAT 0x004C
+#define BUS_CNTL1 0x0034
+# define BUS_WAIT_ON_LOCK_EN (1 << 4)
+#define I2C_CNTL_0 0x0090
+# define I2C_DONE (1<<0)
+# define I2C_NACK (1<<1)
+# define I2C_HALT (1<<2)
+# define I2C_SOFT_RST (1<<5)
+# define I2C_DRIVE_EN (1<<6)
+# define I2C_DRIVE_SEL (1<<7)
+# define I2C_START (1<<8)
+# define I2C_STOP (1<<9)
+# define I2C_RECEIVE (1<<10)
+# define I2C_ABORT (1<<11)
+# define I2C_GO (1<<12)
+# define I2C_SEL (1<<16)
+# define I2C_EN (1<<17)
+#define I2C_CNTL_1 0x0094
+#define I2C_DATA 0x0098
+#define CONFIG_CNTL 0x00E0
/* CONFIG_CNTL bit constants */
-# define CFG_VGA_RAM_EN 0x00000100
-#define CONFIG_MEMSIZE 0x00F8
-#define CONFIG_APER_0_BASE 0x0100
-#define CONFIG_APER_1_BASE 0x0104
-#define CONFIG_APER_SIZE 0x0108
-#define CONFIG_REG_1_BASE 0x010C
-#define CONFIG_REG_APER_SIZE 0x0110
-#define PAD_AGPINPUT_DELAY 0x0164
-#define PAD_CTLR_STRENGTH 0x0168
-#define PAD_CTLR_UPDATE 0x016C
-#define AGP_CNTL 0x0174
-# define AGP_APER_SIZE_256MB (0x00 << 0)
-# define AGP_APER_SIZE_128MB (0x20 << 0)
-# define AGP_APER_SIZE_64MB (0x30 << 0)
-# define AGP_APER_SIZE_32MB (0x38 << 0)
-# define AGP_APER_SIZE_16MB (0x3c << 0)
-# define AGP_APER_SIZE_8MB (0x3e << 0)
-# define AGP_APER_SIZE_4MB (0x3f << 0)
-# define AGP_APER_SIZE_MASK (0x3f << 0)
-#define AMCGPIO_A_REG 0x01a0
-#define AMCGPIO_EN_REG 0x01a8
-#define AMCGPIO_MASK 0x0194
-#define AMCGPIO_Y_REG 0x01a4
-#define BM_STATUS 0x0160
-#define MPP_TB_CONFIG 0x01c0 /* ? */
-#define MPP_GP_CONFIG 0x01c8 /* ? */
-#define VENDOR_ID 0x0F00
-#define DEVICE_ID 0x0F02
-#define COMMAND 0x0F04
-#define STATUS 0x0F06
-#define REVISION_ID 0x0F08
-#define REGPROG_INF 0x0F09
-#define SUB_CLASS 0x0F0A
-#define CACHE_LINE 0x0F0C
-#define LATENCY 0x0F0D
-#define HEADER 0x0F0E
-#define BIST 0x0F0F
-#define REG_MEM_BASE 0x0F10
-#define REG_IO_BASE 0x0F14
-#define REG_REG_BASE 0x0F18
-#define ADAPTER_ID 0x0F2C
-#define BIOS_ROM 0x0F30
-#define CAPABILITIES_PTR 0x0F34
-#define INTERRUPT_LINE 0x0F3C
-#define INTERRUPT_PIN 0x0F3D
-#define MIN_GRANT 0x0F3E
-#define MAX_LATENCY 0x0F3F
-#define ADAPTER_ID_W 0x0F4C
-#define PMI_CAP_ID 0x0F50
-#define PMI_NXT_CAP_PTR 0x0F51
-#define PMI_PMC_REG 0x0F52
-#define PM_STATUS 0x0F54
-#define PMI_DATA 0x0F57
-#define AGP_CAP_ID 0x0F58
-#define AGP_STATUS 0x0F5C
-# define AGP_1X_MODE 0x01
-# define AGP_2X_MODE 0x02
-# define AGP_4X_MODE 0x04
-# define AGP_MODE_MASK 0x07
-#define AGP_COMMAND 0x0F60
+# define CFG_VGA_RAM_EN 0x00000100
+#define CONFIG_MEMSIZE 0x00F8
+#define CONFIG_APER_0_BASE 0x0100
+#define CONFIG_APER_1_BASE 0x0104
+#define CONFIG_APER_SIZE 0x0108
+#define CONFIG_REG_1_BASE 0x010C
+#define CONFIG_REG_APER_SIZE 0x0110
+#define PAD_AGPINPUT_DELAY 0x0164
+#define PAD_CTLR_STRENGTH 0x0168
+#define PAD_CTLR_UPDATE 0x016C
+#define AGP_CNTL 0x0174
+# define AGP_APER_SIZE_256MB (0x00 << 0)
+# define AGP_APER_SIZE_128MB (0x20 << 0)
+# define AGP_APER_SIZE_64MB (0x30 << 0)
+# define AGP_APER_SIZE_32MB (0x38 << 0)
+# define AGP_APER_SIZE_16MB (0x3c << 0)
+# define AGP_APER_SIZE_8MB (0x3e << 0)
+# define AGP_APER_SIZE_4MB (0x3f << 0)
+# define AGP_APER_SIZE_MASK (0x3f << 0)
+#define AMCGPIO_A_REG 0x01a0
+#define AMCGPIO_EN_REG 0x01a8
+#define AMCGPIO_MASK 0x0194
+#define AMCGPIO_Y_REG 0x01a4
+#define BM_STATUS 0x0160
+#define MPP_TB_CONFIG 0x01c0 /* ? */
+#define MPP_GP_CONFIG 0x01c8 /* ? */
+#define VENDOR_ID 0x0F00
+#define DEVICE_ID 0x0F02
+#define COMMAND 0x0F04
+#define STATUS 0x0F06
+#define REVISION_ID 0x0F08
+#define REGPROG_INF 0x0F09
+#define SUB_CLASS 0x0F0A
+#define CACHE_LINE 0x0F0C
+#define LATENCY 0x0F0D
+#define HEADER 0x0F0E
+#define BIST 0x0F0F
+#define REG_MEM_BASE 0x0F10
+#define REG_IO_BASE 0x0F14
+#define REG_REG_BASE 0x0F18
+#define ADAPTER_ID 0x0F2C
+#define BIOS_ROM 0x0F30
+#define CAPABILITIES_PTR 0x0F34
+#define INTERRUPT_LINE 0x0F3C
+#define INTERRUPT_PIN 0x0F3D
+#define MIN_GRANT 0x0F3E
+#define MAX_LATENCY 0x0F3F
+#define ADAPTER_ID_W 0x0F4C
+#define PMI_CAP_ID 0x0F50
+#define PMI_NXT_CAP_PTR 0x0F51
+#define PMI_PMC_REG 0x0F52
+#define PM_STATUS 0x0F54
+#define PMI_DATA 0x0F57
+#define AGP_CAP_ID 0x0F58
+#define AGP_STATUS 0x0F5C
+# define AGP_1X_MODE 0x01
+# define AGP_2X_MODE 0x02
+# define AGP_4X_MODE 0x04
+# define AGP_MODE_MASK 0x07
+#define AGP_COMMAND 0x0F60
/* Video muxer unit */
-#define VIDEOMUX_CNTL 0x0190
-#define VIPPAD_MASK 0x0198
-#define VIPPAD1_A 0x01AC
-#define VIPPAD1_EN 0x01B0
-#define VIPPAD1_Y 0x01B4
-
-#define AIC_CTRL 0x01D0
-#define AIC_STAT 0x01D4
-#define AIC_PT_BASE 0x01D8
-#define AIC_LO_ADDR 0x01DC
-#define AIC_HI_ADDR 0x01E0
-#define AIC_TLB_ADDR 0x01E4
-#define AIC_TLB_DATA 0x01E8
-#define DAC_CNTL 0x0058
-/* DAC_CNTL bit constants */
-# define DAC_8BIT_EN 0x00000100
-# define DAC_4BPP_PIX_ORDER 0x00000200
-# define DAC_CRC_EN 0x00080000
-# define DAC_MASK_ALL (0xff << 24)
-# define DAC_VGA_ADR_EN (1 << 13)
-# define DAC_RANGE_CNTL (3 << 0)
-# define DAC_BLANKING (1 << 2)
-#define DAC_CNTL2 0x007c
+#define VIDEOMUX_CNTL 0x0190
+#define VIPPAD_MASK 0x0198
+#define VIPPAD1_A 0x01AC
+#define VIPPAD1_EN 0x01B0
+#define VIPPAD1_Y 0x01B4
+
+#define AIC_CTRL 0x01D0
+#define AIC_STAT 0x01D4
+#define AIC_PT_BASE 0x01D8
+#define AIC_LO_ADDR 0x01DC
+#define AIC_HI_ADDR 0x01E0
+#define AIC_TLB_ADDR 0x01E4
+#define AIC_TLB_DATA 0x01E8
+#define DAC_CNTL 0x0058
+/* DAC_CNTL bit constants */
+# define DAC_8BIT_EN 0x00000100
+# define DAC_4BPP_PIX_ORDER 0x00000200
+# define DAC_CRC_EN 0x00080000
+# define DAC_MASK_ALL (0xff << 24)
+# define DAC_VGA_ADR_EN (1 << 13)
+# define DAC_RANGE_CNTL (3 << 0)
+# define DAC_BLANKING (1 << 2)
+#define DAC_CNTL2 0x007c
/* DAC_CNTL2 bit constants */
-# define DAC2_DAC_CLK_SEL (1 << 0)
-# define DAC2_DAC2_CLK_SEL (1 << 1)
-# define DAC2_PALETTE_ACC_CTL (1 << 5)
-#define TV_DAC_CNTL 0x088c
+# define DAC2_DAC_CLK_SEL (1 << 0)
+# define DAC2_DAC2_CLK_SEL (1 << 1)
+# define DAC2_PALETTE_ACC_CTL (1 << 5)
+#define TV_DAC_CNTL 0x088c
/* TV_DAC_CNTL bit constants */
-# define TV_DAC_STD_MASK 0x0300
-# define TV_DAC_RDACPD (1 << 24)
-# define TV_DAC_GDACPD (1 << 25)
-# define TV_DAC_BDACPD (1 << 26)
-#define CRTC_GEN_CNTL 0x0050
+# define TV_DAC_STD_MASK 0x0300
+# define TV_DAC_RDACPD (1 << 24)
+# define TV_DAC_GDACPD (1 << 25)
+# define TV_DAC_BDACPD (1 << 26)
+#define CRTC_GEN_CNTL 0x0050
/* CRTC_GEN_CNTL bit constants */
-# define CRTC_DBL_SCAN_EN 0x00000001
-# define CRTC_INTERLACE_EN (1 << 1)
-# define CRTC_CSYNC_EN (1 << 4)
-# define CRTC_CUR_EN 0x00010000
-# define CRTC_CUR_MODE_MASK (7 << 17)
-# define CRTC_ICON_EN (1 << 20)
-# define CRTC_EXT_DISP_EN (1 << 24)
-# define CRTC_EN (1 << 25)
-# define CRTC_DISP_REQ_EN_B (1 << 26)
-#define CRTC2_GEN_CNTL 0x03f8
-/* CRTC2_GEN_CNTL bit constants */
-# define CRTC2_DBL_SCAN_EN (1 << 0)
-# define CRTC2_INTERLACE_EN (1 << 1)
-# define CRTC2_SYNC_TRISTAT (1 << 4)
-# define CRTC2_HSYNC_TRISTAT (1 << 5)
-# define CRTC2_VSYNC_TRISTAT (1 << 6)
-# define CRTC2_CRT2_ON (1 << 7)
-# define CRTC2_ICON_EN (1 << 15)
-# define CRTC2_CUR_EN (1 << 16)
-# define CRTC2_CUR_MODE_MASK (7 << 20)
-# define CRTC2_DISP_DIS (1 << 23)
-# define CRTC2_EN (1 << 25)
-# define CRTC2_DISP_REQ_EN_B (1 << 26)
-# define CRTC2_HSYNC_DIS (1 << 28)
-# define CRTC2_VSYNC_DIS (1 << 29)
-#define MEM_CNTL 0x0140
-/* MEM_CNTL bit constants */
-# define MEM_CTLR_STATUS_IDLE 0x00000000
-# define MEM_CTLR_STATUS_BUSY 0x00100000
-# define MEM_SEQNCR_STATUS_IDLE 0x00000000
-# define MEM_SEQNCR_STATUS_BUSY 0x00200000
-# define MEM_ARBITER_STATUS_IDLE 0x00000000
-# define MEM_ARBITER_STATUS_BUSY 0x00400000
-# define MEM_REQ_UNLOCK 0x00000000
-# define MEM_REQ_LOCK 0x00800000
-#define EXT_MEM_CNTL 0x0144
-#define MC_AGP_LOCATION 0x014C
-#define MEM_IO_CNTL_A0 0x0178
-#define MEM_INIT_LATENCY_TIMER 0x0154
-#define MEM_SDRAM_MODE_REG 0x0158
-#define AGP_BASE 0x0170
-#define MEM_IO_CNTL_A1 0x017C
-#define MEM_IO_CNTL_B0 0x0180
-#define MEM_IO_CNTL_B1 0x0184
-#define MC_DEBUG 0x0188
-#define MC_STATUS 0x0150
-#define MEM_IO_OE_CNTL 0x018C
-#define MC_FB_LOCATION 0x0148
-#define HOST_PATH_CNTL 0x0130
-#define MEM_VGA_WP_SEL 0x0038
-#define MEM_VGA_RP_SEL 0x003C
-#define HDP_DEBUG 0x0138
-#define SW_SEMAPHORE 0x013C
-#define SURFACE_CNTL 0x0B00
-/* SURFACE_CNTL bit constants */
-# define SURF_TRANSLATION_DIS (1 << 8)
-# define NONSURF_AP0_SWP_16BPP (1 << 20)
-# define NONSURF_AP0_SWP_32BPP (2 << 20)
-#define SURFACE0_LOWER_BOUND 0x0B04
-#define SURFACE1_LOWER_BOUND 0x0B14
-#define SURFACE2_LOWER_BOUND 0x0B24
-#define SURFACE3_LOWER_BOUND 0x0B34
-#define SURFACE4_LOWER_BOUND 0x0B44
-#define SURFACE5_LOWER_BOUND 0x0B54
-#define SURFACE6_LOWER_BOUND 0x0B64
-#define SURFACE7_LOWER_BOUND 0x0B74
-#define SURFACE0_UPPER_BOUND 0x0B08
-#define SURFACE1_UPPER_BOUND 0x0B18
-#define SURFACE2_UPPER_BOUND 0x0B28
-#define SURFACE3_UPPER_BOUND 0x0B38
-#define SURFACE4_UPPER_BOUND 0x0B48
-#define SURFACE5_UPPER_BOUND 0x0B58
-#define SURFACE6_UPPER_BOUND 0x0B68
-#define SURFACE7_UPPER_BOUND 0x0B78
-#define SURFACE0_INFO 0x0B0C
-#define SURFACE1_INFO 0x0B1C
-#define SURFACE2_INFO 0x0B2C
-#define SURFACE3_INFO 0x0B3C
-#define SURFACE4_INFO 0x0B4C
-#define SURFACE5_INFO 0x0B5C
-#define SURFACE6_INFO 0x0B6C
-#define SURFACE7_INFO 0x0B7C
-#define SURFACE_ACCESS_FLAGS 0x0BF8
-#define SURFACE_ACCESS_CLR 0x0BFC
-#define GEN_INT_CNTL 0x0040
-#define GEN_INT_STATUS 0x0044
-# define VSYNC_INT_AK (1 << 2)
-# define VSYNC_INT (1 << 2)
-#define CRTC_EXT_CNTL 0x0054
+# define CRTC_DBL_SCAN_EN 0x00000001
+# define CRTC_INTERLACE_EN (1 << 1)
+# define CRTC_CSYNC_EN (1 << 4)
+# define CRTC_CUR_EN 0x00010000
+# define CRTC_CUR_MODE_MASK (7 << 17)
+# define CRTC_ICON_EN (1 << 20)
+# define CRTC_EXT_DISP_EN (1 << 24)
+# define CRTC_EN (1 << 25)
+# define CRTC_DISP_REQ_EN_B (1 << 26)
+#define CRTC2_GEN_CNTL 0x03f8
+/* CRTC2_GEN_CNTL bit constants */
+# define CRTC2_DBL_SCAN_EN (1 << 0)
+# define CRTC2_INTERLACE_EN (1 << 1)
+# define CRTC2_SYNC_TRISTAT (1 << 4)
+# define CRTC2_HSYNC_TRISTAT (1 << 5)
+# define CRTC2_VSYNC_TRISTAT (1 << 6)
+# define CRTC2_CRT2_ON (1 << 7)
+# define CRTC2_ICON_EN (1 << 15)
+# define CRTC2_CUR_EN (1 << 16)
+# define CRTC2_CUR_MODE_MASK (7 << 20)
+# define CRTC2_DISP_DIS (1 << 23)
+# define CRTC2_EN (1 << 25)
+# define CRTC2_DISP_REQ_EN_B (1 << 26)
+# define CRTC2_HSYNC_DIS (1 << 28)
+# define CRTC2_VSYNC_DIS (1 << 29)
+#define MEM_CNTL 0x0140
+/* MEM_CNTL bit constants */
+# define MEM_CTLR_STATUS_IDLE 0x00000000
+# define MEM_CTLR_STATUS_BUSY 0x00100000
+# define MEM_SEQNCR_STATUS_IDLE 0x00000000
+# define MEM_SEQNCR_STATUS_BUSY 0x00200000
+# define MEM_ARBITER_STATUS_IDLE 0x00000000
+# define MEM_ARBITER_STATUS_BUSY 0x00400000
+# define MEM_REQ_UNLOCK 0x00000000
+# define MEM_REQ_LOCK 0x00800000
+#define EXT_MEM_CNTL 0x0144
+#define MC_AGP_LOCATION 0x014C
+#define MEM_IO_CNTL_A0 0x0178
+#define MEM_INIT_LATENCY_TIMER 0x0154
+#define MEM_SDRAM_MODE_REG 0x0158
+#define AGP_BASE 0x0170
+#define MEM_IO_CNTL_A1 0x017C
+#define MEM_IO_CNTL_B0 0x0180
+#define MEM_IO_CNTL_B1 0x0184
+#define MC_DEBUG 0x0188
+#define MC_STATUS 0x0150
+#define MEM_IO_OE_CNTL 0x018C
+#define MC_FB_LOCATION 0x0148
+#define HOST_PATH_CNTL 0x0130
+#define MEM_VGA_WP_SEL 0x0038
+#define MEM_VGA_RP_SEL 0x003C
+#define HDP_DEBUG 0x0138
+#define SW_SEMAPHORE 0x013C
+#define SURFACE_CNTL 0x0B00
+/* SURFACE_CNTL bit constants */
+# define SURF_TRANSLATION_DIS (1 << 8)
+# define NONSURF_AP0_SWP_16BPP (1 << 20)
+# define NONSURF_AP0_SWP_32BPP (2 << 20)
+#define SURFACE0_LOWER_BOUND 0x0B04
+#define SURFACE1_LOWER_BOUND 0x0B14
+#define SURFACE2_LOWER_BOUND 0x0B24
+#define SURFACE3_LOWER_BOUND 0x0B34
+#define SURFACE4_LOWER_BOUND 0x0B44
+#define SURFACE5_LOWER_BOUND 0x0B54
+#define SURFACE6_LOWER_BOUND 0x0B64
+#define SURFACE7_LOWER_BOUND 0x0B74
+#define SURFACE0_UPPER_BOUND 0x0B08
+#define SURFACE1_UPPER_BOUND 0x0B18
+#define SURFACE2_UPPER_BOUND 0x0B28
+#define SURFACE3_UPPER_BOUND 0x0B38
+#define SURFACE4_UPPER_BOUND 0x0B48
+#define SURFACE5_UPPER_BOUND 0x0B58
+#define SURFACE6_UPPER_BOUND 0x0B68
+#define SURFACE7_UPPER_BOUND 0x0B78
+#define SURFACE0_INFO 0x0B0C
+#define SURFACE1_INFO 0x0B1C
+#define SURFACE2_INFO 0x0B2C
+#define SURFACE3_INFO 0x0B3C
+#define SURFACE4_INFO 0x0B4C
+#define SURFACE5_INFO 0x0B5C
+#define SURFACE6_INFO 0x0B6C
+#define SURFACE7_INFO 0x0B7C
+#define SURFACE_ACCESS_FLAGS 0x0BF8
+#define SURFACE_ACCESS_CLR 0x0BFC
+#define GEN_INT_CNTL 0x0040
+#define GEN_INT_STATUS 0x0044
+# define VSYNC_INT_AK (1 << 2)
+# define VSYNC_INT (1 << 2)
+#define CRTC_EXT_CNTL 0x0054
/* CRTC_EXT_CNTL bit constants */
-# define CRTC_VGA_XOVERSCAN (1 << 0)
-# define VGA_ATI_LINEAR 0x00000008
-# define VGA_128KAP_PAGING 0x00000010
-# define XCRT_CNT_EN (1 << 6)
-# define CRTC_HSYNC_DIS (1 << 8)
-# define CRTC_VSYNC_DIS (1 << 9)
-# define CRTC_DISPLAY_DIS (1 << 10)
-# define CRTC_SYNC_TRISTAT (1 << 11)
-# define CRTC_CRT_ON (1 << 15)
-#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055
-# define CRTC_HSYNC_DIS_BYTE (1 << 0)
-# define CRTC_VSYNC_DIS_BYTE (1 << 1)
-# define CRTC_DISPLAY_DIS_BYTE (1 << 2)
-#define RB3D_CNTL 0x1C3C
-#define WAIT_UNTIL 0x1720
-#define ISYNC_CNTL 0x1724
-#define RBBM_GUICNTL 0x172C
-#define RBBM_STATUS 0x0E40
-# define RBBM_FIFOCNT_MASK 0x007f
-# define RBBM_ACTIVE (1 << 31)
-#define RBBM_STATUS_alt_1 0x1740
-#define RBBM_CNTL 0x00EC
-#define RBBM_CNTL_alt_1 0x0E44
-#define RBBM_SOFT_RESET 0x00F0
+# define CRTC_VGA_XOVERSCAN (1 << 0)
+# define VGA_ATI_LINEAR 0x00000008
+# define VGA_128KAP_PAGING 0x00000010
+# define XCRT_CNT_EN (1 << 6)
+# define CRTC_HSYNC_DIS (1 << 8)
+# define CRTC_VSYNC_DIS (1 << 9)
+# define CRTC_DISPLAY_DIS (1 << 10)
+# define CRTC_SYNC_TRISTAT (1 << 11)
+# define CRTC_CRT_ON (1 << 15)
+#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055
+# define CRTC_HSYNC_DIS_BYTE (1 << 0)
+# define CRTC_VSYNC_DIS_BYTE (1 << 1)
+# define CRTC_DISPLAY_DIS_BYTE (1 << 2)
+#define RB3D_CNTL 0x1C3C
+#define WAIT_UNTIL 0x1720
+#define ISYNC_CNTL 0x1724
+#define RBBM_GUICNTL 0x172C
+#define RBBM_STATUS 0x0E40
+# define RBBM_FIFOCNT_MASK 0x007f
+# define RBBM_ACTIVE (1 << 31)
+#define RBBM_STATUS_alt_1 0x1740
+#define RBBM_CNTL 0x00EC
+#define RBBM_CNTL_alt_1 0x0E44
+#define RBBM_SOFT_RESET 0x00F0
/* RBBM_SOFT_RESET bit constants */
-# define SOFT_RESET_CP (1 << 0)
-# define SOFT_RESET_HI (1 << 1)
-# define SOFT_RESET_SE (1 << 2)
-# define SOFT_RESET_RE (1 << 3)
-# define SOFT_RESET_PP (1 << 4)
-# define SOFT_RESET_E2 (1 << 5)
-# define SOFT_RESET_RB (1 << 6)
-# define SOFT_RESET_HDP (1 << 7)
-#define RBBM_SOFT_RESET_alt_1 0x0E48
-#define NQWAIT_UNTIL 0x0E50
-#define RBBM_DEBUG 0x0E6C
-#define RBBM_CMDFIFO_ADDR 0x0E70
-#define RBBM_CMDFIFO_DATAL 0x0E74
-#define RBBM_CMDFIFO_DATAH 0x0E78
-#define RBBM_CMDFIFO_STAT 0x0E7C
-#define CRTC_STATUS 0x005C
+# define SOFT_RESET_CP (1 << 0)
+# define SOFT_RESET_HI (1 << 1)
+# define SOFT_RESET_SE (1 << 2)
+# define SOFT_RESET_RE (1 << 3)
+# define SOFT_RESET_PP (1 << 4)
+# define SOFT_RESET_E2 (1 << 5)
+# define SOFT_RESET_RB (1 << 6)
+# define SOFT_RESET_HDP (1 << 7)
+#define RBBM_SOFT_RESET_alt_1 0x0E48
+#define NQWAIT_UNTIL 0x0E50
+#define RBBM_DEBUG 0x0E6C
+#define RBBM_CMDFIFO_ADDR 0x0E70
+#define RBBM_CMDFIFO_DATAL 0x0E74
+#define RBBM_CMDFIFO_DATAH 0x0E78
+#define RBBM_CMDFIFO_STAT 0x0E7C
+#define CRTC_STATUS 0x005C
/* CRTC_STATUS bit constants */
-# define CRTC_VBLANK 0x00000001
-# define CRTC_VBLANK_SAVE ( 1 << 1)
-#define GPIO_VGA_DDC 0x0060
-#define GPIO_DVI_DDC 0x0064
-#define GPIO_MONID 0x0068
-#define PALETTE_INDEX 0x00B0
-#define PALETTE_DATA 0x00B4
-#define PALETTE_30_DATA 0x00B8
-#define CRTC_H_TOTAL_DISP 0x0200
-# define CRTC_H_TOTAL (0x03ff << 0)
-# define CRTC_H_TOTAL_SHIFT 0
-# define CRTC_H_DISP (0x01ff << 16)
-# define CRTC_H_DISP_SHIFT 16
-#define CRTC2_H_TOTAL_DISP 0x0300
-# define CRTC2_H_TOTAL (0x03ff << 0)
-# define CRTC2_H_TOTAL_SHIFT 0
-# define CRTC2_H_DISP (0x01ff << 16)
-# define CRTC2_H_DISP_SHIFT 16
-#define CRTC_H_SYNC_STRT_WID 0x0204
-# define CRTC_H_SYNC_STRT_PIX (0x07 << 0)
-# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
-# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3
-# define CRTC_H_SYNC_WID (0x3f << 16)
-# define CRTC_H_SYNC_WID_SHIFT 16
-# define CRTC_H_SYNC_POL (1 << 23)
-#define CRTC2_H_SYNC_STRT_WID 0x0304
-# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
-# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
-# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
-# define CRTC2_H_SYNC_WID (0x3f << 16)
-# define CRTC2_H_SYNC_WID_SHIFT 16
-# define CRTC2_H_SYNC_POL (1 << 23)
-#define CRTC_V_TOTAL_DISP 0x0208
-# define CRTC_V_TOTAL (0x07ff << 0)
-# define CRTC_V_TOTAL_SHIFT 0
-# define CRTC_V_DISP (0x07ff << 16)
-# define CRTC_V_DISP_SHIFT 16
-#define CRTC2_V_TOTAL_DISP 0x0308
-# define CRTC2_V_TOTAL (0x07ff << 0)
-# define CRTC2_V_TOTAL_SHIFT 0
-# define CRTC2_V_DISP (0x07ff << 16)
-# define CRTC2_V_DISP_SHIFT 16
-#define CRTC_V_SYNC_STRT_WID 0x020C
-# define CRTC_V_SYNC_STRT (0x7ff << 0)
-# define CRTC_V_SYNC_STRT_SHIFT 0
-# define CRTC_V_SYNC_WID (0x1f << 16)
-# define CRTC_V_SYNC_WID_SHIFT 16
-# define CRTC_V_SYNC_POL (1 << 23)
-#define CRTC2_V_SYNC_STRT_WID 0x030C
-# define CRTC2_V_SYNC_STRT (0x7ff << 0)
-# define CRTC2_V_SYNC_STRT_SHIFT 0
-# define CRTC2_V_SYNC_WID (0x1f << 16)
-# define CRTC2_V_SYNC_WID_SHIFT 16
-# define CRTC2_V_SYNC_POL (1 << 23)
-#define CRTC_VLINE_CRNT_VLINE 0x0210
-# define CRTC_CRNT_VLINE_MASK (0x7ff << 16)
-#define CRTC2_VLINE_CRNT_VLINE 0x0310
-#define CRTC_CRNT_FRAME 0x0214
-#define CRTC2_CRNT_FRAME 0x0314
-#define CRTC_GUI_TRIG_VLINE 0x0218
-#define CRTC2_GUI_TRIG_VLINE 0x0318
-#define CRTC_DEBUG 0x021C
-#define CRTC2_DEBUG 0x031C
-#define CRTC_OFFSET_RIGHT 0x0220
-#define CRTC_OFFSET 0x0224
-#define CRTC2_OFFSET 0x0324
-#define CRTC_OFFSET_CNTL 0x0228
-# define CRTC_TILE_EN (1 << 15)
-#define CRTC2_OFFSET_CNTL 0x0328
-# define CRTC2_TILE_EN (1 << 15)
-#define CRTC_PITCH 0x022C
-#define CRTC2_PITCH 0x032C
-#define TMDS_CRC 0x02a0
-#define OVR_CLR 0x0230
-#define OVR_WID_LEFT_RIGHT 0x0234
-#define OVR_WID_TOP_BOTTOM 0x0238
-#define DISPLAY_BASE_ADDR 0x023C
-#define SNAPSHOT_VH_COUNTS 0x0240
-#define SNAPSHOT_F_COUNT 0x0244
-#define N_VIF_COUNT 0x0248
-#define SNAPSHOT_VIF_COUNT 0x024C
-#define FP_CRTC_H_TOTAL_DISP 0x0250
-#define FP_CRTC2_H_TOTAL_DISP 0x0350
-#define FP_CRTC_V_TOTAL_DISP 0x0254
-#define FP_CRTC2_V_TOTAL_DISP 0x0354
-# define FP_CRTC_H_TOTAL_MASK 0x000003ff
-# define FP_CRTC_H_DISP_MASK 0x01ff0000
-# define FP_CRTC_V_TOTAL_MASK 0x00000fff
-# define FP_CRTC_V_DISP_MASK 0x0fff0000
-# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
-# define FP_H_SYNC_WID_MASK 0x003f0000
-# define FP_V_SYNC_STRT_MASK 0x00000fff
-# define FP_V_SYNC_WID_MASK 0x001f0000
-# define FP_CRTC_H_TOTAL_SHIFT 0x00000000
-# define FP_CRTC_H_DISP_SHIFT 0x00000010
-# define FP_CRTC_V_TOTAL_SHIFT 0x00000000
-# define FP_CRTC_V_DISP_SHIFT 0x00000010
-# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
-# define FP_H_SYNC_WID_SHIFT 0x00000010
-# define FP_V_SYNC_STRT_SHIFT 0x00000000
-# define FP_V_SYNC_WID_SHIFT 0x00000010
-#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
-#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
-#define CUR_OFFSET 0x0260
-#define CUR_HORZ_VERT_POSN 0x0264
-#define CUR_HORZ_VERT_OFF 0x0268
+# define CRTC_VBLANK 0x00000001
+# define CRTC_VBLANK_SAVE ( 1 << 1)
+#define GPIO_VGA_DDC 0x0060
+#define GPIO_DVI_DDC 0x0064
+#define GPIO_MONID 0x0068
+#define PALETTE_INDEX 0x00B0
+#define PALETTE_DATA 0x00B4
+#define PALETTE_30_DATA 0x00B8
+#define CRTC_H_TOTAL_DISP 0x0200
+# define CRTC_H_TOTAL (0x03ff << 0)
+# define CRTC_H_TOTAL_SHIFT 0
+# define CRTC_H_DISP (0x01ff << 16)
+# define CRTC_H_DISP_SHIFT 16
+#define CRTC2_H_TOTAL_DISP 0x0300
+# define CRTC2_H_TOTAL (0x03ff << 0)
+# define CRTC2_H_TOTAL_SHIFT 0
+# define CRTC2_H_DISP (0x01ff << 16)
+# define CRTC2_H_DISP_SHIFT 16
+#define CRTC_H_SYNC_STRT_WID 0x0204
+# define CRTC_H_SYNC_STRT_PIX (0x07 << 0)
+# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
+# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3
+# define CRTC_H_SYNC_WID (0x3f << 16)
+# define CRTC_H_SYNC_WID_SHIFT 16
+# define CRTC_H_SYNC_POL (1 << 23)
+#define CRTC2_H_SYNC_STRT_WID 0x0304
+# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
+# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
+# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
+# define CRTC2_H_SYNC_WID (0x3f << 16)
+# define CRTC2_H_SYNC_WID_SHIFT 16
+# define CRTC2_H_SYNC_POL (1 << 23)
+#define CRTC_V_TOTAL_DISP 0x0208
+# define CRTC_V_TOTAL (0x07ff << 0)
+# define CRTC_V_TOTAL_SHIFT 0
+# define CRTC_V_DISP (0x07ff << 16)
+# define CRTC_V_DISP_SHIFT 16
+#define CRTC2_V_TOTAL_DISP 0x0308
+# define CRTC2_V_TOTAL (0x07ff << 0)
+# define CRTC2_V_TOTAL_SHIFT 0
+# define CRTC2_V_DISP (0x07ff << 16)
+# define CRTC2_V_DISP_SHIFT 16
+#define CRTC_V_SYNC_STRT_WID 0x020C
+# define CRTC_V_SYNC_STRT (0x7ff << 0)
+# define CRTC_V_SYNC_STRT_SHIFT 0
+# define CRTC_V_SYNC_WID (0x1f << 16)
+# define CRTC_V_SYNC_WID_SHIFT 16
+# define CRTC_V_SYNC_POL (1 << 23)
+#define CRTC2_V_SYNC_STRT_WID 0x030C
+# define CRTC2_V_SYNC_STRT (0x7ff << 0)
+# define CRTC2_V_SYNC_STRT_SHIFT 0
+# define CRTC2_V_SYNC_WID (0x1f << 16)
+# define CRTC2_V_SYNC_WID_SHIFT 16
+# define CRTC2_V_SYNC_POL (1 << 23)
+#define CRTC_VLINE_CRNT_VLINE 0x0210
+# define CRTC_CRNT_VLINE_MASK (0x7ff << 16)
+#define CRTC2_VLINE_CRNT_VLINE 0x0310
+#define CRTC_CRNT_FRAME 0x0214
+#define CRTC2_CRNT_FRAME 0x0314
+#define CRTC_GUI_TRIG_VLINE 0x0218
+#define CRTC2_GUI_TRIG_VLINE 0x0318
+#define CRTC_DEBUG 0x021C
+#define CRTC2_DEBUG 0x031C
+#define CRTC_OFFSET_RIGHT 0x0220
+#define CRTC_OFFSET 0x0224
+#define CRTC2_OFFSET 0x0324
+#define CRTC_OFFSET_CNTL 0x0228
+# define CRTC_TILE_EN (1 << 15)
+#define CRTC2_OFFSET_CNTL 0x0328
+# define CRTC2_TILE_EN (1 << 15)
+#define CRTC_PITCH 0x022C
+#define CRTC2_PITCH 0x032C
+#define TMDS_CRC 0x02a0
+#define OVR_CLR 0x0230
+#define OVR_WID_LEFT_RIGHT 0x0234
+#define OVR_WID_TOP_BOTTOM 0x0238
+#define DISPLAY_BASE_ADDR 0x023C
+#define SNAPSHOT_VH_COUNTS 0x0240
+#define SNAPSHOT_F_COUNT 0x0244
+#define N_VIF_COUNT 0x0248
+#define SNAPSHOT_VIF_COUNT 0x024C
+#define FP_CRTC_H_TOTAL_DISP 0x0250
+#define FP_CRTC2_H_TOTAL_DISP 0x0350
+#define FP_CRTC_V_TOTAL_DISP 0x0254
+#define FP_CRTC2_V_TOTAL_DISP 0x0354
+# define FP_CRTC_H_TOTAL_MASK 0x000003ff
+# define FP_CRTC_H_DISP_MASK 0x01ff0000
+# define FP_CRTC_V_TOTAL_MASK 0x00000fff
+# define FP_CRTC_V_DISP_MASK 0x0fff0000
+# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
+# define FP_H_SYNC_WID_MASK 0x003f0000
+# define FP_V_SYNC_STRT_MASK 0x00000fff
+# define FP_V_SYNC_WID_MASK 0x001f0000
+# define FP_CRTC_H_TOTAL_SHIFT 0x00000000
+# define FP_CRTC_H_DISP_SHIFT 0x00000010
+# define FP_CRTC_V_TOTAL_SHIFT 0x00000000
+# define FP_CRTC_V_DISP_SHIFT 0x00000010
+# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
+# define FP_H_SYNC_WID_SHIFT 0x00000010
+# define FP_V_SYNC_STRT_SHIFT 0x00000000
+# define FP_V_SYNC_WID_SHIFT 0x00000010
+#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
+#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
+#define CUR_OFFSET 0x0260
+#define CUR_HORZ_VERT_POSN 0x0264
+#define CUR_HORZ_VERT_OFF 0x0268
/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
-# define CUR_LOCK 0x80000000
-#define CUR_CLR0 0x026C
-#define CUR_CLR1 0x0270
-#define CUR2_OFFSET 0x0360
-#define CUR2_HORZ_VERT_POSN 0x0364
-#define CUR2_HORZ_VERT_OFF 0x0368
-# define CUR2_LOCK (1 << 31)
-#define CUR2_CLR0 0x036c
-#define CUR2_CLR1 0x0370
-#define FP_HORZ_VERT_ACTIVE 0x0278
-#define CRTC_MORE_CNTL 0x027C
-#define DAC_EXT_CNTL 0x0280
-#define FP_GEN_CNTL 0x0284
+# define CUR_LOCK 0x80000000
+#define CUR_CLR0 0x026C
+#define CUR_CLR1 0x0270
+#define CUR2_OFFSET 0x0360
+#define CUR2_HORZ_VERT_POSN 0x0364
+#define CUR2_HORZ_VERT_OFF 0x0368
+# define CUR2_LOCK (1 << 31)
+#define CUR2_CLR0 0x036c
+#define CUR2_CLR1 0x0370
+#define FP_HORZ_VERT_ACTIVE 0x0278
+#define CRTC_MORE_CNTL 0x027C
+#define DAC_EXT_CNTL 0x0280
+#define FP_GEN_CNTL 0x0284
/* FP_GEN_CNTL bit constants */
-# define FP_FPON (1 << 0)
-# define FP_TMDS_EN (1 << 2)
-# define FP_EN_TMDS (1 << 7)
-# define FP_DETECT_SENSE (1 << 8)
-# define FP_SEL_CRTC2 (1 << 13)
-# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
-# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
-# define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
-# define FP_CRTC_USE_SHADOW_VEND (1 << 18)
-# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
-# define FP_DFP_SYNC_SEL (1 << 21)
-# define FP_CRTC_LOCK_8DOT (1 << 22)
-# define FP_CRT_SYNC_SEL (1 << 23)
-# define FP_USE_SHADOW_EN (1 << 24)
-# define FP_CRT_SYNC_ALT (1 << 26)
-#define FP2_GEN_CNTL 0x0288
-/* FP2_GEN_CNTL bit constants */
-# define FP2_FPON (1 << 0)
-# define FP2_TMDS_EN (1 << 2)
-# define FP2_EN_TMDS (1 << 7)
-# define FP2_DETECT_SENSE (1 << 8)
-# define FP2_SEL_CRTC2 (1 << 13)
-# define FP2_FP_POL (1 << 16)
-# define FP2_LP_POL (1 << 17)
-# define FP2_SCK_POL (1 << 18)
-# define FP2_LCD_CNTL_MASK (7 << 19)
-# define FP2_PAD_FLOP_EN (1 << 22)
-# define FP2_CRC_EN (1 << 23)
-# define FP2_CRC_READ_EN (1 << 24)
-#define FP_HORZ_STRETCH 0x028C
-#define FP_HORZ2_STRETCH 0x038C
-# define HORZ_STRETCH_RATIO_MASK 0xffff
-# define HORZ_STRETCH_RATIO_MAX 4096
-# define HORZ_PANEL_SIZE (0x1ff << 16)
-# define HORZ_PANEL_SHIFT 16
-# define HORZ_STRETCH_PIXREP (0 << 25)
-# define HORZ_STRETCH_BLEND (1 << 26)
-# define HORZ_STRETCH_ENABLE (1 << 25)
-# define HORZ_AUTO_RATIO (1 << 27)
-# define HORZ_FP_LOOP_STRETCH (0x7 << 28)
-# define HORZ_AUTO_RATIO_INC (1 << 31)
-#define FP_VERT_STRETCH 0x0290
-#define FP_VERT2_STRETCH 0x0390
-# define VERT_PANEL_SIZE (0xfff << 12)
-# define VERT_PANEL_SHIFT 12
-# define VERT_STRETCH_RATIO_MASK 0xfff
-# define VERT_STRETCH_RATIO_SHIFT 0
-# define VERT_STRETCH_RATIO_MAX 4096
-# define VERT_STRETCH_ENABLE (1 << 25)
-# define VERT_STRETCH_LINEREP (0 << 26)
-# define VERT_STRETCH_BLEND (1 << 26)
-# define VERT_AUTO_RATIO_EN (1 << 27)
-# define VERT_STRETCH_RESERVED 0xf1000000
-#define FP_H_SYNC_STRT_WID 0x02C4
-#define FP_H2_SYNC_STRT_WID 0x03C4
-#define FP_V_SYNC_STRT_WID 0x02C8
-#define FP_V2_SYNC_STRT_WID 0x03C8
-#define LVDS_GEN_CNTL 0x02d0
-# define LVDS_ON (1 << 0)
-# define LVDS_DISPLAY_DIS (1 << 1)
-# define LVDS_PANEL_TYPE (1 << 2)
-# define LVDS_PANEL_FORMAT (1 << 3)
-# define LVDS_EN (1 << 7)
-# define LVDS_DIGON (1 << 18)
-# define LVDS_BLON (1 << 19)
-# define LVDS_SEL_CRTC2 (1 << 23)
-#define LVDS_PLL_CNTL 0x02d4
-# define HSYNC_DELAY_SHIFT 28
-# define HSYNC_DELAY_MASK (0xf << 28)
-#define AUX_WINDOW_HORZ_CNTL 0x02D8
-#define AUX_WINDOW_VERT_CNTL 0x02DC
-#define DDA_CONFIG 0x02e0
-#define DDA_ON_OFF 0x02e4
-
-#define GRPH_BUFFER_CNTL 0x02F0
-#define VGA_BUFFER_CNTL 0x02F4
+# define FP_FPON (1 << 0)
+# define FP_TMDS_EN (1 << 2)
+# define FP_EN_TMDS (1 << 7)
+# define FP_DETECT_SENSE (1 << 8)
+# define FP_SEL_CRTC2 (1 << 13)
+# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
+# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
+# define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
+# define FP_CRTC_USE_SHADOW_VEND (1 << 18)
+# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
+# define FP_DFP_SYNC_SEL (1 << 21)
+# define FP_CRTC_LOCK_8DOT (1 << 22)
+# define FP_CRT_SYNC_SEL (1 << 23)
+# define FP_USE_SHADOW_EN (1 << 24)
+# define FP_CRT_SYNC_ALT (1 << 26)
+#define FP2_GEN_CNTL 0x0288
+/* FP2_GEN_CNTL bit constants */
+# define FP2_FPON (1 << 0)
+# define FP2_TMDS_EN (1 << 2)
+# define FP2_EN_TMDS (1 << 7)
+# define FP2_DETECT_SENSE (1 << 8)
+# define FP2_SEL_CRTC2 (1 << 13)
+# define FP2_FP_POL (1 << 16)
+# define FP2_LP_POL (1 << 17)
+# define FP2_SCK_POL (1 << 18)
+# define FP2_LCD_CNTL_MASK (7 << 19)
+# define FP2_PAD_FLOP_EN (1 << 22)
+# define FP2_CRC_EN (1 << 23)
+# define FP2_CRC_READ_EN (1 << 24)
+#define FP_HORZ_STRETCH 0x028C
+#define FP_HORZ2_STRETCH 0x038C
+# define HORZ_STRETCH_RATIO_MASK 0xffff
+# define HORZ_STRETCH_RATIO_MAX 4096
+# define HORZ_PANEL_SIZE (0x1ff << 16)
+# define HORZ_PANEL_SHIFT 16
+# define HORZ_STRETCH_PIXREP (0 << 25)
+# define HORZ_STRETCH_BLEND (1 << 26)
+# define HORZ_STRETCH_ENABLE (1 << 25)
+# define HORZ_AUTO_RATIO (1 << 27)
+# define HORZ_FP_LOOP_STRETCH (0x7 << 28)
+# define HORZ_AUTO_RATIO_INC (1 << 31)
+#define FP_VERT_STRETCH 0x0290
+#define FP_VERT2_STRETCH 0x0390
+# define VERT_PANEL_SIZE (0xfff << 12)
+# define VERT_PANEL_SHIFT 12
+# define VERT_STRETCH_RATIO_MASK 0xfff
+# define VERT_STRETCH_RATIO_SHIFT 0
+# define VERT_STRETCH_RATIO_MAX 4096
+# define VERT_STRETCH_ENABLE (1 << 25)
+# define VERT_STRETCH_LINEREP (0 << 26)
+# define VERT_STRETCH_BLEND (1 << 26)
+# define VERT_AUTO_RATIO_EN (1 << 27)
+# define VERT_STRETCH_RESERVED 0xf1000000
+#define FP_H_SYNC_STRT_WID 0x02C4
+#define FP_H2_SYNC_STRT_WID 0x03C4
+#define FP_V_SYNC_STRT_WID 0x02C8
+#define FP_V2_SYNC_STRT_WID 0x03C8
+#define LVDS_GEN_CNTL 0x02d0
+# define LVDS_ON (1 << 0)
+# define LVDS_DISPLAY_DIS (1 << 1)
+# define LVDS_PANEL_TYPE (1 << 2)
+# define LVDS_PANEL_FORMAT (1 << 3)
+# define LVDS_EN (1 << 7)
+# define LVDS_DIGON (1 << 18)
+# define LVDS_BLON (1 << 19)
+# define LVDS_SEL_CRTC2 (1 << 23)
+#define LVDS_PLL_CNTL 0x02d4
+# define HSYNC_DELAY_SHIFT 28
+# define HSYNC_DELAY_MASK (0xf << 28)
+#define AUX_WINDOW_HORZ_CNTL 0x02D8
+#define AUX_WINDOW_VERT_CNTL 0x02DC
+#define DDA_CONFIG 0x02e0
+#define DDA_ON_OFF 0x02e4
+
+#define GRPH_BUFFER_CNTL 0x02F0
+#define VGA_BUFFER_CNTL 0x02F4
/* first overlay unit (there is only one) */
-#define OV0_Y_X_START 0x0400
-#define OV0_Y_X_END 0x0404
-#define OV0_PIPELINE_CNTL 0x0408
-#define OV0_EXCLUSIVE_HORZ 0x0408
-# define EXCL_HORZ_START_MASK 0x000000ff
-# define EXCL_HORZ_END_MASK 0x0000ff00
-# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
-# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000
-#define OV0_EXCLUSIVE_VERT 0x040C
-# define EXCL_VERT_START_MASK 0x000003ff
-# define EXCL_VERT_END_MASK 0x03ff0000
-#define OV0_REG_LOAD_CNTL 0x0410
-# define REG_LD_CTL_LOCK 0x00000001L
-# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
-# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
-# define REG_LD_CTL_LOCK_READBACK 0x00000008L
-#define OV0_SCALE_CNTL 0x0420
-# define SCALER_PIX_EXPAND 0x00000001L
-# define SCALER_Y2R_TEMP 0x00000002L
+#define OV0_Y_X_START 0x0400
+#define OV0_Y_X_END 0x0404
+#define OV0_PIPELINE_CNTL 0x0408
+#define OV0_EXCLUSIVE_HORZ 0x0408
+# define EXCL_HORZ_START_MASK 0x000000ff
+# define EXCL_HORZ_END_MASK 0x0000ff00
+# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
+# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000
+#define OV0_EXCLUSIVE_VERT 0x040C
+# define EXCL_VERT_START_MASK 0x000003ff
+# define EXCL_VERT_END_MASK 0x03ff0000
+#define OV0_REG_LOAD_CNTL 0x0410
+# define REG_LD_CTL_LOCK 0x00000001L
+# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
+# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
+# define REG_LD_CTL_LOCK_READBACK 0x00000008L
+#define OV0_SCALE_CNTL 0x0420
+# define SCALER_PIX_EXPAND 0x00000001L
+# define SCALER_Y2R_TEMP 0x00000002L
#ifdef RAGE128
-# define SCALER_HORZ_PICK_NEAREST 0x00000003L
-# define SCALER_VERT_PICK_NEAREST 0x00000004L
+# define SCALER_HORZ_PICK_NEAREST 0x00000003L
+# define SCALER_VERT_PICK_NEAREST 0x00000004L
#else
-# define SCALER_HORZ_PICK_NEAREST 0x00000004L
-# define SCALER_VERT_PICK_NEAREST 0x00000008L
+# define SCALER_HORZ_PICK_NEAREST 0x00000004L
+# define SCALER_VERT_PICK_NEAREST 0x00000008L
#endif
-# define SCALER_SIGNED_UV 0x00000010L
-# define SCALER_GAMMA_SEL_MASK 0x00000060L
-# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L
-# define SCALER_GAMMA_SEL_G22 0x00000020L
-# define SCALER_GAMMA_SEL_G18 0x00000040L
-# define SCALER_GAMMA_SEL_G14 0x00000060L
-# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
-# define SCALER_SURFAC_FORMAT 0x00000f00L
-# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */
-# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */
-# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */
-# define SCALER_SOURCE_15BPP 0x00000300L
-# define SCALER_SOURCE_16BPP 0x00000400L
-# define SCALER_SOURCE_24BPP 0x00000500L
-# define SCALER_SOURCE_32BPP 0x00000600L
-# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */
-# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */
-# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */
-# define SCALER_SOURCE_YUV12 0x00000A00L
-# define SCALER_SOURCE_VYUY422 0x00000B00L
-# define SCALER_SOURCE_YVYU422 0x00000C00L
-# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */
-# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */
-# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */
-# define SCALER_ADAPTIVE_DEINT 0x00001000L
-# define R200_SCALER_TEMPORAL_DEINT 0x00002000L
-# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */
-# define SCALER_SMART_SWITCH 0x00008000L
+# define SCALER_SIGNED_UV 0x00000010L
+# define SCALER_GAMMA_SEL_MASK 0x00000060L
+# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L
+# define SCALER_GAMMA_SEL_G22 0x00000020L
+# define SCALER_GAMMA_SEL_G18 0x00000040L
+# define SCALER_GAMMA_SEL_G14 0x00000060L
+# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
+# define SCALER_SURFAC_FORMAT 0x00000f00L
+# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */
+# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */
+# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */
+# define SCALER_SOURCE_15BPP 0x00000300L
+# define SCALER_SOURCE_16BPP 0x00000400L
+# define SCALER_SOURCE_24BPP 0x00000500L
+# define SCALER_SOURCE_32BPP 0x00000600L
+# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */
+# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */
+# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */
+# define SCALER_SOURCE_YUV12 0x00000A00L
+# define SCALER_SOURCE_VYUY422 0x00000B00L
+# define SCALER_SOURCE_YVYU422 0x00000C00L
+# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */
+# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */
+# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */
+# define SCALER_ADAPTIVE_DEINT 0x00001000L
+# define R200_SCALER_TEMPORAL_DEINT 0x00002000L
+# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */
+# define SCALER_SMART_SWITCH 0x00008000L
#ifdef RAGE128
-# define SCALER_BURST_PER_PLANE 0x00ff0000L
+# define SCALER_BURST_PER_PLANE 0x00ff0000L
#else
-# define SCALER_BURST_PER_PLANE 0x007f0000L
+# define SCALER_BURST_PER_PLANE 0x007f0000L
#endif
-# define SCALER_DOUBLE_BUFFER 0x01000000L
-# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */
-# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */
-# define SCALER_DIS_LIMIT 0x08000000L
-# define SCALER_PRG_LOAD_START 0x10000000L
-# define SCALER_INT_EMU 0x20000000L
-# define SCALER_ENABLE 0x40000000L
-# define SCALER_SOFT_RESET 0x80000000L
-#define OV0_V_INC 0x0424
-#define OV0_P1_V_ACCUM_INIT 0x0428
-# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
-# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
-#define OV0_P23_V_ACCUM_INIT 0x042C
-# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L
-# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L
-#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
-# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
-# define P1_ACTIVE_LINES_M1 0x0fff0000L
-#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
-# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
-# define P23_ACTIVE_LINES_M1 0x07ff0000L
+# define SCALER_DOUBLE_BUFFER 0x01000000L
+# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */
+# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */
+# define SCALER_DIS_LIMIT 0x08000000L
+# define SCALER_PRG_LOAD_START 0x10000000L
+# define SCALER_INT_EMU 0x20000000L
+# define SCALER_ENABLE 0x40000000L
+# define SCALER_SOFT_RESET 0x80000000L
+#define OV0_V_INC 0x0424
+#define OV0_P1_V_ACCUM_INIT 0x0428
+# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
+# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
+#define OV0_P23_V_ACCUM_INIT 0x042C
+# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L
+# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L
+#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
+# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
+# define P1_ACTIVE_LINES_M1 0x0fff0000L
+#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
+# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
+# define P23_ACTIVE_LINES_M1 0x07ff0000L
#ifndef RAGE128
-#define OV0_BASE_ADDR 0x043C
+#define OV0_BASE_ADDR 0x043C
#endif
-#define OV0_VID_BUF0_BASE_ADRS 0x0440
-# define VIF_BUF0_PITCH_SEL 0x00000001L
-# define VIF_BUF0_TILE_ADRS 0x00000002L
-# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
-# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
-#define OV0_VID_BUF1_BASE_ADRS 0x0444
-# define VIF_BUF1_PITCH_SEL 0x00000001L
-# define VIF_BUF1_TILE_ADRS 0x00000002L
-# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
-# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
-#define OV0_VID_BUF2_BASE_ADRS 0x0448
-# define VIF_BUF2_PITCH_SEL 0x00000001L
-# define VIF_BUF2_TILE_ADRS 0x00000002L
-# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
-# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
-#define OV0_VID_BUF3_BASE_ADRS 0x044C
-# define VIF_BUF3_PITCH_SEL 0x00000001L
-# define VIF_BUF3_TILE_ADRS 0x00000002L
-# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L
-# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L
-#define OV0_VID_BUF4_BASE_ADRS 0x0450
-# define VIF_BUF4_PITCH_SEL 0x00000001L
-# define VIF_BUF4_TILE_ADRS 0x00000002L
-# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L
-# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L
-#define OV0_VID_BUF5_BASE_ADRS 0x0454
-# define VIF_BUF5_PITCH_SEL 0x00000001L
-# define VIF_BUF5_TILE_ADRS 0x00000002L
-# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L
-# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L
-#define OV0_VID_BUF_PITCH0_VALUE 0x0460
-#define OV0_VID_BUF_PITCH1_VALUE 0x0464
-#define OV0_AUTO_FLIP_CNTL 0x0470
-# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
-# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
-# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
-# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
-# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
-# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
-# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
-# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
-# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
-# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
-#define OV0_DEINTERLACE_PATTERN 0x0474
-#define OV0_SUBMIT_HISTORY 0x0478
-#define OV0_H_INC 0x0480
-#define OV0_STEP_BY 0x0484
-#define OV0_P1_H_ACCUM_INIT 0x0488
-#define OV0_P23_H_ACCUM_INIT 0x048C
-#define OV0_P1_X_START_END 0x0494
-#define OV0_P2_X_START_END 0x0498
-#define OV0_P3_X_START_END 0x049C
-#define OV0_FILTER_CNTL 0x04A0
-# define FILTER_PROGRAMMABLE_COEF 0x00000000
-# define FILTER_HARDCODED_COEF 0x0000000F
-# define FILTER_COEF_MASK 0x0000000F
+#define OV0_VID_BUF0_BASE_ADRS 0x0440
+# define VIF_BUF0_PITCH_SEL 0x00000001L
+# define VIF_BUF0_TILE_ADRS 0x00000002L
+# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
+#define OV0_VID_BUF1_BASE_ADRS 0x0444
+# define VIF_BUF1_PITCH_SEL 0x00000001L
+# define VIF_BUF1_TILE_ADRS 0x00000002L
+# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
+#define OV0_VID_BUF2_BASE_ADRS 0x0448
+# define VIF_BUF2_PITCH_SEL 0x00000001L
+# define VIF_BUF2_TILE_ADRS 0x00000002L
+# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
+#define OV0_VID_BUF3_BASE_ADRS 0x044C
+# define VIF_BUF3_PITCH_SEL 0x00000001L
+# define VIF_BUF3_TILE_ADRS 0x00000002L
+# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L
+#define OV0_VID_BUF4_BASE_ADRS 0x0450
+# define VIF_BUF4_PITCH_SEL 0x00000001L
+# define VIF_BUF4_TILE_ADRS 0x00000002L
+# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L
+#define OV0_VID_BUF5_BASE_ADRS 0x0454
+# define VIF_BUF5_PITCH_SEL 0x00000001L
+# define VIF_BUF5_TILE_ADRS 0x00000002L
+# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L
+#define OV0_VID_BUF_PITCH0_VALUE 0x0460
+#define OV0_VID_BUF_PITCH1_VALUE 0x0464
+#define OV0_AUTO_FLIP_CNTL 0x0470
+# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
+# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
+# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
+# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
+# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
+# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
+# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
+# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
+# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
+# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
+#define OV0_DEINTERLACE_PATTERN 0x0474
+#define OV0_SUBMIT_HISTORY 0x0478
+#define OV0_H_INC 0x0480
+#define OV0_STEP_BY 0x0484
+#define OV0_P1_H_ACCUM_INIT 0x0488
+#define OV0_P23_H_ACCUM_INIT 0x048C
+#define OV0_P1_X_START_END 0x0494
+#define OV0_P2_X_START_END 0x0498
+#define OV0_P3_X_START_END 0x049C
+#define OV0_FILTER_CNTL 0x04A0
+# define FILTER_PROGRAMMABLE_COEF 0x00000000
+# define FILTER_HARDCODED_COEF 0x0000000F
+# define FILTER_COEF_MASK 0x0000000F
/* other values allow us use hardcoded coefs for Y and
programmable for UV that's nosense. */
/*
@@ -666,1393 +666,1393 @@
It allows up to 64:1 upscaling and downscaling without
performance or quality degradation.
*/
-#define OV0_FOUR_TAP_COEF_0 0x04B0
-#define OV0_FOUR_TAP_COEF_1 0x04B4
-#define OV0_FOUR_TAP_COEF_2 0x04B8
-#define OV0_FOUR_TAP_COEF_3 0x04BC
-#define OV0_FOUR_TAP_COEF_4 0x04C0
+#define OV0_FOUR_TAP_COEF_0 0x04B0
+#define OV0_FOUR_TAP_COEF_1 0x04B4
+#define OV0_FOUR_TAP_COEF_2 0x04B8
+#define OV0_FOUR_TAP_COEF_3 0x04BC
+#define OV0_FOUR_TAP_COEF_4 0x04C0
-#define OV0_FLAG_CNTL 0x04DC
+#define OV0_FLAG_CNTL 0x04DC
#ifdef RAGE128
-#define OV0_COLOUR_CNTL 0x04E0
-# define COLOUR_CNTL_BRIGHTNESS 0x0000007F
-# define COLOUR_CNTL_SATURATION 0x001F1F00
+#define OV0_COLOUR_CNTL 0x04E0
+# define COLOUR_CNTL_BRIGHTNESS 0x0000007F
+# define COLOUR_CNTL_SATURATION 0x001F1F00
#else
/* NB: radeons have no COLOUR_CNTL register */
-#define OV0_SLICE_CNTL 0x04E0
-# define SLICE_CNTL_DISABLE 0x40000000
+#define OV0_SLICE_CNTL 0x04E0
+# define SLICE_CNTL_DISABLE 0x40000000
#endif
/* Video and graphics keys allow alpha blending, color correction
and many other video effects */
-#define OV0_VID_KEY_CLR 0x04E4
-#define OV0_VID_KEY_MSK 0x04E8
-#define OV0_GRAPHICS_KEY_CLR 0x04EC
-#define OV0_GRAPHICS_KEY_MSK 0x04F0
-#define OV0_KEY_CNTL 0x04F4
-# define VIDEO_KEY_FN_MASK 0x00000007L
-# define VIDEO_KEY_FN_FALSE 0x00000000L
-# define VIDEO_KEY_FN_TRUE 0x00000001L
-# define VIDEO_KEY_FN_EQ 0x00000004L
-# define VIDEO_KEY_FN_NE 0x00000005L
-# define GRAPHIC_KEY_FN_MASK 0x00000070L
-# define GRAPHIC_KEY_FN_FALSE 0x00000000L
-# define GRAPHIC_KEY_FN_TRUE 0x00000010L
-# define GRAPHIC_KEY_FN_EQ 0x00000040L
-# define GRAPHIC_KEY_FN_NE 0x00000050L
-# define CMP_MIX_MASK 0x00000100L
-# define CMP_MIX_OR 0x00000000L
-# define CMP_MIX_AND 0x00000100L
-#define OV0_TEST 0x04F8
-#define OV0_LIN_TRANS_A 0x0D20
-#define OV0_LIN_TRANS_B 0x0D24
-#define OV0_LIN_TRANS_C 0x0D28
-#define OV0_LIN_TRANS_D 0x0D2C
-#define OV0_LIN_TRANS_E 0x0D30
-#define OV0_LIN_TRANS_F 0x0D34
-#define OV0_GAMMA_0_F 0x0D40
-#define OV0_GAMMA_10_1F 0x0D44
-#define OV0_GAMMA_20_3F 0x0D48
-#define OV0_GAMMA_40_7F 0x0D4C
+#define OV0_VID_KEY_CLR 0x04E4
+#define OV0_VID_KEY_MSK 0x04E8
+#define OV0_GRAPHICS_KEY_CLR 0x04EC
+#define OV0_GRAPHICS_KEY_MSK 0x04F0
+#define OV0_KEY_CNTL 0x04F4
+# define VIDEO_KEY_FN_MASK 0x00000007L
+# define VIDEO_KEY_FN_FALSE 0x00000000L
+# define VIDEO_KEY_FN_TRUE 0x00000001L
+# define VIDEO_KEY_FN_EQ 0x00000004L
+# define VIDEO_KEY_FN_NE 0x00000005L
+# define GRAPHIC_KEY_FN_MASK 0x00000070L
+# define GRAPHIC_KEY_FN_FALSE 0x00000000L
+# define GRAPHIC_KEY_FN_TRUE 0x00000010L
+# define GRAPHIC_KEY_FN_EQ 0x00000040L
+# define GRAPHIC_KEY_FN_NE 0x00000050L
+# define CMP_MIX_MASK 0x00000100L
+# define CMP_MIX_OR 0x00000000L
+# define CMP_MIX_AND 0x00000100L
+#define OV0_TEST 0x04F8
+#define OV0_LIN_TRANS_A 0x0D20
+#define OV0_LIN_TRANS_B 0x0D24
+#define OV0_LIN_TRANS_C 0x0D28
+#define OV0_LIN_TRANS_D 0x0D2C
+#define OV0_LIN_TRANS_E 0x0D30
+#define OV0_LIN_TRANS_F 0x0D34
+#define OV0_GAMMA_0_F 0x0D40
+#define OV0_GAMMA_10_1F 0x0D44
+#define OV0_GAMMA_20_3F 0x0D48
+#define OV0_GAMMA_40_7F 0x0D4C
/* These registers exist on R200 only */
-#define OV0_GAMMA_80_BF 0x0E00
-#define OV0_GAMMA_C0_FF 0x0E04
-#define OV0_GAMMA_100_13F 0x0E08
-#define OV0_GAMMA_140_17F 0x0E0C
-#define OV0_GAMMA_180_1BF 0x0E10
-#define OV0_GAMMA_1C0_1FF 0x0E14
-#define OV0_GAMMA_200_23F 0x0E18
-#define OV0_GAMMA_240_27F 0x0E1C
-#define OV0_GAMMA_280_2BF 0x0E20
-#define OV0_GAMMA_2C0_2FF 0x0E24
-#define OV0_GAMMA_300_33F 0x0E28
-#define OV0_GAMMA_340_37F 0x0E2C
+#define OV0_GAMMA_80_BF 0x0E00
+#define OV0_GAMMA_C0_FF 0x0E04
+#define OV0_GAMMA_100_13F 0x0E08
+#define OV0_GAMMA_140_17F 0x0E0C
+#define OV0_GAMMA_180_1BF 0x0E10
+#define OV0_GAMMA_1C0_1FF 0x0E14
+#define OV0_GAMMA_200_23F 0x0E18
+#define OV0_GAMMA_240_27F 0x0E1C
+#define OV0_GAMMA_280_2BF 0x0E20
+#define OV0_GAMMA_2C0_2FF 0x0E24
+#define OV0_GAMMA_300_33F 0x0E28
+#define OV0_GAMMA_340_37F 0x0E2C
/* End of R200 specific definitions */
-#define OV0_GAMMA_380_3BF 0x0D50
-#define OV0_GAMMA_3C0_3FF 0x0D54
+#define OV0_GAMMA_380_3BF 0x0D50
+#define OV0_GAMMA_3C0_3FF 0x0D54
/*
IDCT ENGINE:
It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag
and IDCT into an IDCT engine to complement the motion compensation engine.
*/
-#define IDCT_RUNS 0x1F80
-#define IDCT_LEVELS 0x1F84
-#define IDCT_AUTH_CONTROL 0x1F88
-#define IDCT_AUTH 0x1F8C
-#define IDCT_CONTROL 0x1FBC
-
-#define SE_MC_SRC2_CNTL 0x19D4
-#define SE_MC_SRC1_CNTL 0x19D8
-#define SE_MC_DST_CNTL 0x19DC
-#define SE_MC_CNTL_START 0x19E0
+#define IDCT_RUNS 0x1F80
+#define IDCT_LEVELS 0x1F84
+#define IDCT_AUTH_CONTROL 0x1F88
+#define IDCT_AUTH 0x1F8C
+#define IDCT_CONTROL 0x1FBC
+
+#define SE_MC_SRC2_CNTL 0x19D4
+#define SE_MC_SRC1_CNTL 0x19D8
+#define SE_MC_DST_CNTL 0x19DC
+#define SE_MC_CNTL_START 0x19E0
#ifndef RAGE128
-#define SE_MC_BUF_BASE 0x19E4
-#define PP_MC_CONTEXT 0x19E8
-#define PP_MISC 0x1C14
+#define SE_MC_BUF_BASE 0x19E4
+#define PP_MC_CONTEXT 0x19E8
+#define PP_MISC 0x1C14
#endif
/*
SUBPICTURE UNIT:
Decompressing, scaling and alpha blending the compressed bitmap on the fly.
Provide optimal DVD subpicture qualtity.
*/
-#define SUBPIC_CNTL 0x0540
-#define SUBPIC_DEFCOLCON 0x0544
-#define SUBPIC_Y_X_START 0x054C
-#define SUBPIC_Y_X_END 0x0550
-#define SUBPIC_V_INC 0x0554
-#define SUBPIC_H_INC 0x0558
-#define SUBPIC_BUF0_OFFSET 0x055C
-#define SUBPIC_BUF1_OFFSET 0x0560
-#define SUBPIC_LC0_OFFSET 0x0564
-#define SUBPIC_LC1_OFFSET 0x0568
-#define SUBPIC_PITCH 0x056C
-#define SUBPIC_BTN_HLI_COLCON 0x0570
-#define SUBPIC_BTN_HLI_Y_X_START 0x0574
-#define SUBPIC_BTN_HLI_Y_X_END 0x0578
-#define SUBPIC_PALETTE_INDEX 0x057C
-#define SUBPIC_PALETTE_DATA 0x0580
-#define SUBPIC_H_ACCUM_INIT 0x0584
-#define SUBPIC_V_ACCUM_INIT 0x0588
-
-#define CP_RB_BASE 0x0700
-#define CP_RB_CNTL 0x0704
-#define CP_RB_RPTR_ADDR 0x070C
-#define CP_RB_RPTR 0x0710
-#define CP_RB_WPTR 0x0714
-#define CP_RB_WPTR_DELAY 0x0718
-#define CP_IB_BASE 0x0738
-#define CP_IB_BUFSZ 0x073C
-#define CP_CSQ_CNTL 0x0740
-#define SCRATCH_UMSK 0x0770
-#define SCRATCH_ADDR 0x0774
-#define DMA_GUI_TABLE_ADDR 0x0780
-#define DMA_GUI_SRC_ADDR 0x0784
-#define DMA_GUI_DST_ADDR 0x0788
-#define DMA_GUI_COMMAND 0x078C
-#define DMA_GUI_STATUS 0x0790
-#define DMA_GUI_ACT_DSCRPTR 0x0794
-#define DMA_VID_TABLE_ADDR 0x07A0
-#define DMA_VID_SRC_ADDR 0x07A4
-#define DMA_VID_DST_ADDR 0x07A8
-#define DMA_VID_COMMAND 0x07AC
-#define DMA_VID_STATUS 0x07B0
-#define DMA_VID_ACT_DSCRPTR 0x07B4
-#define CP_ME_CNTL 0x07D0
-#define CP_ME_RAM_ADDR 0x07D4
-#define CP_ME_RAM_RADDR 0x07D8
-#define CP_ME_RAM_DATAH 0x07DC
-#define CP_ME_RAM_DATAL 0x07E0
-#define CP_CSQ_ADDR 0x07F0
-#define CP_CSQ_DATA 0x07F4
-#define CP_CSQ_STAT 0x07F8
-
-#define DISP_MISC_CNTL 0x0D00
-# define SOFT_RESET_GRPH_PP (1 << 0)
-#define DAC_MACRO_CNTL 0x0D04
-#define DISP_PWR_MAN 0x0D08
-#define DISP_TEST_DEBUG_CNTL 0x0D10
-#define DISP_HW_DEBUG 0x0D14
-#define DAC_CRC_SIG1 0x0D18
-#define DAC_CRC_SIG2 0x0D1C
+#define SUBPIC_CNTL 0x0540
+#define SUBPIC_DEFCOLCON 0x0544
+#define SUBPIC_Y_X_START 0x054C
+#define SUBPIC_Y_X_END 0x0550
+#define SUBPIC_V_INC 0x0554
+#define SUBPIC_H_INC 0x0558
+#define SUBPIC_BUF0_OFFSET 0x055C
+#define SUBPIC_BUF1_OFFSET 0x0560
+#define SUBPIC_LC0_OFFSET 0x0564
+#define SUBPIC_LC1_OFFSET 0x0568
+#define SUBPIC_PITCH 0x056C
+#define SUBPIC_BTN_HLI_COLCON 0x0570
+#define SUBPIC_BTN_HLI_Y_X_START 0x0574
+#define SUBPIC_BTN_HLI_Y_X_END 0x0578
+#define SUBPIC_PALETTE_INDEX 0x057C
+#define SUBPIC_PALETTE_DATA 0x0580
+#define SUBPIC_H_ACCUM_INIT 0x0584
+#define SUBPIC_V_ACCUM_INIT 0x0588
+
+#define CP_RB_BASE 0x0700
+#define CP_RB_CNTL 0x0704
+#define CP_RB_RPTR_ADDR 0x070C
+#define CP_RB_RPTR 0x0710
+#define CP_RB_WPTR 0x0714
+#define CP_RB_WPTR_DELAY 0x0718
+#define CP_IB_BASE 0x0738
+#define CP_IB_BUFSZ 0x073C
+#define CP_CSQ_CNTL 0x0740
+#define SCRATCH_UMSK 0x0770
+#define SCRATCH_ADDR 0x0774
+#define DMA_GUI_TABLE_ADDR 0x0780
+#define DMA_GUI_SRC_ADDR 0x0784
+#define DMA_GUI_DST_ADDR 0x0788
+#define DMA_GUI_COMMAND 0x078C
+#define DMA_GUI_STATUS 0x0790
+#define DMA_GUI_ACT_DSCRPTR 0x0794
+#define DMA_VID_TABLE_ADDR 0x07A0
+#define DMA_VID_SRC_ADDR 0x07A4
+#define DMA_VID_DST_ADDR 0x07A8
+#define DMA_VID_COMMAND 0x07AC
+#define DMA_VID_STATUS 0x07B0
+#define DMA_VID_ACT_DSCRPTR 0x07B4
+#define CP_ME_CNTL 0x07D0
+#define CP_ME_RAM_ADDR 0x07D4
+#define CP_ME_RAM_RADDR 0x07D8
+#define CP_ME_RAM_DATAH 0x07DC
+#define CP_ME_RAM_DATAL 0x07E0
+#define CP_CSQ_ADDR 0x07F0
+#define CP_CSQ_DATA 0x07F4
+#define CP_CSQ_STAT 0x07F8
+
+#define DISP_MISC_CNTL 0x0D00
+# define SOFT_RESET_GRPH_PP (1 << 0)
+#define DAC_MACRO_CNTL 0x0D04
+#define DISP_PWR_MAN 0x0D08
+#define DISP_TEST_DEBUG_CNTL 0x0D10
+#define DISP_HW_DEBUG 0x0D14
+#define DAC_CRC_SIG1 0x0D18
+#define DAC_CRC_SIG2 0x0D1C
/* first capture unit */
-#define VID_BUFFER_CONTROL 0x0900
-#define CAP_INT_CNTL 0x0908
-#define CAP_INT_STATUS 0x090C
-#define FCP_CNTL 0x0910
-#define CAP0_BUF0_OFFSET 0x0920
-#define CAP0_BUF1_OFFSET 0x0924
-#define CAP0_BUF0_EVEN_OFFSET 0x0928
-#define CAP0_BUF1_EVEN_OFFSET 0x092C
-#define CAP0_BUF_PITCH 0x0930
-#define CAP0_V_WINDOW 0x0934
-#define CAP0_H_WINDOW 0x0938
-#define CAP0_VBI0_OFFSET 0x093C
-#define CAP0_VBI1_OFFSET 0x0940
-#define CAP0_VBI_V_WINDOW 0x0944
-#define CAP0_VBI_H_WINDOW 0x0948
-#define CAP0_PORT_MODE_CNTL 0x094C
-#define CAP0_TRIG_CNTL 0x0950
-#define CAP0_DEBUG 0x0954
-#define CAP0_CONFIG 0x0958
-# define CAP0_CONFIG_CONTINUOS 0x00000001
-# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002
-# define CAP0_CONFIG_START_BUF_GET 0x00000004
-# define CAP0_CONFIG_START_BUF_SET 0x00000008
-# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
-# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
-# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
-# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
-# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
-# define CAP0_CONFIG_MIRROR_EN 0x00000200
-# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
-# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
-# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000
-# define CAP0_CONFIG_VBI_EN 0x00002000
-# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
-# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
-# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
-# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
-# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
-# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
-# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
-# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
-# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
-# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
-# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000
-# define CAP0_CONFIG_FORMAT_ZV 0x01000000
-# define CAP0_CONFIG_FORMAT_VIP 0x01800000
-# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
-# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
-# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
-# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
-# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
-# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
-#define CAP0_ANC_ODD_OFFSET 0x095C
-#define CAP0_ANC_EVEN_OFFSET 0x0960
-#define CAP0_ANC_H_WINDOW 0x0964
-#define CAP0_VIDEO_SYNC_TEST 0x0968
-#define CAP0_ONESHOT_BUF_OFFSET 0x096C
-#define CAP0_BUF_STATUS 0x0970
+#define VID_BUFFER_CONTROL 0x0900
+#define CAP_INT_CNTL 0x0908
+#define CAP_INT_STATUS 0x090C
+#define FCP_CNTL 0x0910
+#define CAP0_BUF0_OFFSET 0x0920
+#define CAP0_BUF1_OFFSET 0x0924
+#define CAP0_BUF0_EVEN_OFFSET 0x0928
+#define CAP0_BUF1_EVEN_OFFSET 0x092C
+#define CAP0_BUF_PITCH 0x0930
+#define CAP0_V_WINDOW 0x0934
+#define CAP0_H_WINDOW 0x0938
+#define CAP0_VBI0_OFFSET 0x093C
+#define CAP0_VBI1_OFFSET 0x0940
+#define CAP0_VBI_V_WINDOW 0x0944
+#define CAP0_VBI_H_WINDOW 0x0948
+#define CAP0_PORT_MODE_CNTL 0x094C
+#define CAP0_TRIG_CNTL 0x0950
+#define CAP0_DEBUG 0x0954
+#define CAP0_CONFIG 0x0958
+# define CAP0_CONFIG_CONTINUOS 0x00000001
+# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002
+# define CAP0_CONFIG_START_BUF_GET 0x00000004
+# define CAP0_CONFIG_START_BUF_SET 0x00000008
+# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
+# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
+# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
+# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
+# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
+# define CAP0_CONFIG_MIRROR_EN 0x00000200
+# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
+# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
+# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000
+# define CAP0_CONFIG_VBI_EN 0x00002000
+# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
+# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
+# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
+# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
+# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
+# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
+# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
+# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
+# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
+# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
+# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000
+# define CAP0_CONFIG_FORMAT_ZV 0x01000000
+# define CAP0_CONFIG_FORMAT_VIP 0x01800000
+# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
+# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
+# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
+# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
+# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
+# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
+#define CAP0_ANC_ODD_OFFSET 0x095C
+#define CAP0_ANC_EVEN_OFFSET 0x0960
+#define CAP0_ANC_H_WINDOW 0x0964
+#define CAP0_VIDEO_SYNC_TEST 0x0968
+#define CAP0_ONESHOT_BUF_OFFSET 0x096C
+#define CAP0_BUF_STATUS 0x0970
#ifdef RAGE128
-#define CAP0_DWNSC_XRATIO 0x0978
-#define CAP0_XSHARPNESS 0x097C
+#define CAP0_DWNSC_XRATIO 0x0978
+#define CAP0_XSHARPNESS 0x097C
#else
-/* #define CAP0_DWNSC_XRATIO 0x0978 */
-/* #define CAP0_XSHARPNESS 0x097C */
+/* #define CAP0_DWNSC_XRATIO 0x0978 */
+/* #define CAP0_XSHARPNESS 0x097C */
#endif
-#define CAP0_VBI2_OFFSET 0x0980
-#define CAP0_VBI3_OFFSET 0x0984
-#define CAP0_ANC2_OFFSET 0x0988
-#define CAP0_ANC3_OFFSET 0x098C
+#define CAP0_VBI2_OFFSET 0x0980
+#define CAP0_VBI3_OFFSET 0x0984
+#define CAP0_ANC2_OFFSET 0x0988
+#define CAP0_ANC3_OFFSET 0x098C
/* second capture unit */
-#define CAP1_BUF0_OFFSET 0x0990
-#define CAP1_BUF1_OFFSET 0x0994
-#define CAP1_BUF0_EVEN_OFFSET 0x0998
-#define CAP1_BUF1_EVEN_OFFSET 0x099C
-
-#define CAP1_BUF_PITCH 0x09A0
-#define CAP1_V_WINDOW 0x09A4
-#define CAP1_H_WINDOW 0x09A8
-#define CAP1_VBI_ODD_OFFSET 0x09AC
-#define CAP1_VBI_EVEN_OFFSET 0x09B0
-#define CAP1_VBI_V_WINDOW 0x09B4
-#define CAP1_VBI_H_WINDOW 0x09B8
-#define CAP1_PORT_MODE_CNTL 0x09BC
-#define CAP1_TRIG_CNTL 0x09C0
-#define CAP1_DEBUG 0x09C4
-#define CAP1_CONFIG 0x09C8
-#define CAP1_ANC_ODD_OFFSET 0x09CC
-#define CAP1_ANC_EVEN_OFFSET 0x09D0
-#define CAP1_ANC_H_WINDOW 0x09D4
-#define CAP1_VIDEO_SYNC_TEST 0x09D8
-#define CAP1_ONESHOT_BUF_OFFSET 0x09DC
-#define CAP1_BUF_STATUS 0x09E0
-#define CAP1_DWNSC_XRATIO 0x09E8
-#define CAP1_XSHARPNESS 0x09EC
-
-#define DISP_MERGE_CNTL 0x0D60
-#define DISP_OUTPUT_CNTL 0x0D64
-# define DISP_DAC_SOURCE_MASK 0x03
-# define DISP_DAC_SOURCE_CRTC2 0x01
-#define DISP_LIN_TRANS_GRPH_A 0x0D80
-#define DISP_LIN_TRANS_GRPH_B 0x0D84
-#define DISP_LIN_TRANS_GRPH_C 0x0D88
-#define DISP_LIN_TRANS_GRPH_D 0x0D8C
-#define DISP_LIN_TRANS_GRPH_E 0x0D90
-#define DISP_LIN_TRANS_GRPH_F 0x0D94
-#define DISP_LIN_TRANS_VID_A 0x0D98
-#define DISP_LIN_TRANS_VID_B 0x0D9C
-#define DISP_LIN_TRANS_VID_C 0x0DA0
-#define DISP_LIN_TRANS_VID_D 0x0DA4
-#define DISP_LIN_TRANS_VID_E 0x0DA8
-#define DISP_LIN_TRANS_VID_F 0x0DAC
-#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
-#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
-#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
-#define RMX_HORZ_PHASE 0x0DBC
-#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
-#define DAC_BROAD_PULSE 0x0DC4
-#define DAC_SKEW_CLKS 0x0DC8
-#define DAC_INCR 0x0DCC
-#define DAC_NEG_SYNC_LEVEL 0x0DD0
-#define DAC_POS_SYNC_LEVEL 0x0DD4
-#define DAC_BLANK_LEVEL 0x0DD8
-#define CLOCK_CNTL_INDEX 0x0008
-/* CLOCK_CNTL_INDEX bit constants */
-# define PLL_WR_EN 0x00000080
-# define PLL_DIV_SEL (3 << 8)
-# define PLL2_DIV_SEL_MASK ~(3 << 8)
-#define CLOCK_CNTL_DATA 0x000C
-#define CP_RB_CNTL 0x0704
-#define CP_RB_BASE 0x0700
-#define CP_RB_RPTR_ADDR 0x070C
-#define CP_RB_RPTR 0x0710
-#define CP_RB_WPTR 0x0714
-#define CP_RB_WPTR_DELAY 0x0718
-#define CP_IB_BASE 0x0738
-#define CP_IB_BUFSZ 0x073C
-#define SCRATCH_REG0 0x15E0
-#define GUI_SCRATCH_REG0 0x15E0
-#define SCRATCH_REG1 0x15E4
-#define GUI_SCRATCH_REG1 0x15E4
-#define SCRATCH_REG2 0x15E8
-#define GUI_SCRATCH_REG2 0x15E8
-#define SCRATCH_REG3 0x15EC
-#define GUI_SCRATCH_REG3 0x15EC
-#define SCRATCH_REG4 0x15F0
-#define GUI_SCRATCH_REG4 0x15F0
-#define SCRATCH_REG5 0x15F4
-#define GUI_SCRATCH_REG5 0x15F4
-#define SCRATCH_UMSK 0x0770
-#define SCRATCH_ADDR 0x0774
-#define DP_BRUSH_FRGD_CLR 0x147C
-#define DP_BRUSH_BKGD_CLR 0x1478
-#define DST_LINE_START 0x1600
-#define DST_LINE_END 0x1604
-#define SRC_OFFSET 0x15AC
-#define SRC_PITCH 0x15B0
-#define SRC_TILE 0x1704
-#define SRC_PITCH_OFFSET 0x1428
-#define SRC_X 0x1414
-#define SRC_Y 0x1418
-#define DST_WIDTH_X 0x1588
-#define DST_HEIGHT_WIDTH_8 0x158C
-#define SRC_X_Y 0x1590
-#define SRC_Y_X 0x1434
-#define DST_Y_X 0x1438
-#define DST_WIDTH_HEIGHT 0x1598
-#define DST_HEIGHT_WIDTH 0x143c
-#define SRC_CLUT_ADDRESS 0x1780
-#define SRC_CLUT_DATA 0x1784
-#define SRC_CLUT_DATA_RD 0x1788
-#define HOST_DATA0 0x17C0
-#define HOST_DATA1 0x17C4
-#define HOST_DATA2 0x17C8
-#define HOST_DATA3 0x17CC
-#define HOST_DATA4 0x17D0
-#define HOST_DATA5 0x17D4
-#define HOST_DATA6 0x17D8
-#define HOST_DATA7 0x17DC
-#define HOST_DATA_LAST 0x17E0
-#define DP_SRC_ENDIAN 0x15D4
-#define DP_SRC_FRGD_CLR 0x15D8
-#define DP_SRC_BKGD_CLR 0x15DC
-#define DP_WRITE_MASK 0x16cc
-#define SC_LEFT 0x1640
-#define SC_RIGHT 0x1644
-#define SC_TOP 0x1648
-#define SC_BOTTOM 0x164C
-#define SRC_SC_RIGHT 0x1654
-#define SRC_SC_BOTTOM 0x165C
-#define DP_CNTL 0x16C0
+#define CAP1_BUF0_OFFSET 0x0990
+#define CAP1_BUF1_OFFSET 0x0994
+#define CAP1_BUF0_EVEN_OFFSET 0x0998
+#define CAP1_BUF1_EVEN_OFFSET 0x099C
+
+#define CAP1_BUF_PITCH 0x09A0
+#define CAP1_V_WINDOW 0x09A4
+#define CAP1_H_WINDOW 0x09A8
+#define CAP1_VBI_ODD_OFFSET 0x09AC
+#define CAP1_VBI_EVEN_OFFSET 0x09B0
+#define CAP1_VBI_V_WINDOW 0x09B4
+#define CAP1_VBI_H_WINDOW 0x09B8
+#define CAP1_PORT_MODE_CNTL 0x09BC
+#define CAP1_TRIG_CNTL 0x09C0
+#define CAP1_DEBUG 0x09C4
+#define CAP1_CONFIG 0x09C8
+#define CAP1_ANC_ODD_OFFSET 0x09CC
+#define CAP1_ANC_EVEN_OFFSET 0x09D0
+#define CAP1_ANC_H_WINDOW 0x09D4
+#define CAP1_VIDEO_SYNC_TEST 0x09D8
+#define CAP1_ONESHOT_BUF_OFFSET 0x09DC
+#define CAP1_BUF_STATUS 0x09E0
+#define CAP1_DWNSC_XRATIO 0x09E8
+#define CAP1_XSHARPNESS 0x09EC
+
+#define DISP_MERGE_CNTL 0x0D60
+#define DISP_OUTPUT_CNTL 0x0D64
+# define DISP_DAC_SOURCE_MASK 0x03
+# define DISP_DAC_SOURCE_CRTC2 0x01
+#define DISP_LIN_TRANS_GRPH_A 0x0D80
+#define DISP_LIN_TRANS_GRPH_B 0x0D84
+#define DISP_LIN_TRANS_GRPH_C 0x0D88
+#define DISP_LIN_TRANS_GRPH_D 0x0D8C
+#define DISP_LIN_TRANS_GRPH_E 0x0D90
+#define DISP_LIN_TRANS_GRPH_F 0x0D94
+#define DISP_LIN_TRANS_VID_A 0x0D98
+#define DISP_LIN_TRANS_VID_B 0x0D9C
+#define DISP_LIN_TRANS_VID_C 0x0DA0
+#define DISP_LIN_TRANS_VID_D 0x0DA4
+#define DISP_LIN_TRANS_VID_E 0x0DA8
+#define DISP_LIN_TRANS_VID_F 0x0DAC
+#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
+#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
+#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
+#define RMX_HORZ_PHASE 0x0DBC
+#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
+#define DAC_BROAD_PULSE 0x0DC4
+#define DAC_SKEW_CLKS 0x0DC8
+#define DAC_INCR 0x0DCC
+#define DAC_NEG_SYNC_LEVEL 0x0DD0
+#define DAC_POS_SYNC_LEVEL 0x0DD4
+#define DAC_BLANK_LEVEL 0x0DD8
+#define CLOCK_CNTL_INDEX 0x0008
+/* CLOCK_CNTL_INDEX bit constants */
+# define PLL_WR_EN 0x00000080
+# define PLL_DIV_SEL (3 << 8)
+# define PLL2_DIV_SEL_MASK ~(3 << 8)
+#define CLOCK_CNTL_DATA 0x000C
+#define CP_RB_CNTL 0x0704
+#define CP_RB_BASE 0x0700
+#define CP_RB_RPTR_ADDR 0x070C
+#define CP_RB_RPTR 0x0710
+#define CP_RB_WPTR 0x0714
+#define CP_RB_WPTR_DELAY 0x0718
+#define CP_IB_BASE 0x0738
+#define CP_IB_BUFSZ 0x073C
+#define SCRATCH_REG0 0x15E0
+#define GUI_SCRATCH_REG0 0x15E0
+#define SCRATCH_REG1 0x15E4
+#define GUI_SCRATCH_REG1 0x15E4
+#define SCRATCH_REG2 0x15E8
+#define GUI_SCRATCH_REG2 0x15E8
+#define SCRATCH_REG3 0x15EC
+#define GUI_SCRATCH_REG3 0x15EC
+#define SCRATCH_REG4 0x15F0
+#define GUI_SCRATCH_REG4 0x15F0
+#define SCRATCH_REG5 0x15F4
+#define GUI_SCRATCH_REG5 0x15F4
+#define SCRATCH_UMSK 0x0770
+#define SCRATCH_ADDR 0x0774
+#define DP_BRUSH_FRGD_CLR 0x147C
+#define DP_BRUSH_BKGD_CLR 0x1478
+#define DST_LINE_START 0x1600
+#define DST_LINE_END 0x1604
+#define SRC_OFFSET 0x15AC
+#define SRC_PITCH 0x15B0
+#define SRC_TILE 0x1704
+#define SRC_PITCH_OFFSET 0x1428
+#define SRC_X 0x1414
+#define SRC_Y 0x1418
+#define DST_WIDTH_X 0x1588
+#define DST_HEIGHT_WIDTH_8 0x158C
+#define SRC_X_Y 0x1590
+#define SRC_Y_X 0x1434
+#define DST_Y_X 0x1438
+#define DST_WIDTH_HEIGHT 0x1598
+#define DST_HEIGHT_WIDTH 0x143c
+#define SRC_CLUT_ADDRESS 0x1780
+#define SRC_CLUT_DATA 0x1784
+#define SRC_CLUT_DATA_RD 0x1788
+#define HOST_DATA0 0x17C0
+#define HOST_DATA1 0x17C4
+#define HOST_DATA2 0x17C8
+#define HOST_DATA3 0x17CC
+#define HOST_DATA4 0x17D0
+#define HOST_DATA5 0x17D4
+#define HOST_DATA6 0x17D8
+#define HOST_DATA7 0x17DC
+#define HOST_DATA_LAST 0x17E0
+#define DP_SRC_ENDIAN 0x15D4
+#define DP_SRC_FRGD_CLR 0x15D8
+#define DP_SRC_BKGD_CLR 0x15DC
+#define DP_WRITE_MASK 0x16cc
+#define SC_LEFT 0x1640
+#define SC_RIGHT 0x1644
+#define SC_TOP 0x1648
+#define SC_BOTTOM 0x164C
+#define SRC_SC_RIGHT 0x1654
+#define SRC_SC_BOTTOM 0x165C
+#define DP_CNTL 0x16C0
/* DP_CNTL bit constants */
-# define DST_X_RIGHT_TO_LEFT 0x00000000
-# define DST_X_LEFT_TO_RIGHT 0x00000001
-# define DST_Y_BOTTOM_TO_TOP 0x00000000
-# define DST_Y_TOP_TO_BOTTOM 0x00000002
-# define DST_X_MAJOR 0x00000000
-# define DST_Y_MAJOR 0x00000004
-# define DST_X_TILE 0x00000008
-# define DST_Y_TILE 0x00000010
-# define DST_LAST_PEL 0x00000020
-# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
-# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
-# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
-# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
-# define DST_BRES_SIGN 0x00000100
-# define DST_HOST_BIG_ENDIAN_EN 0x00000200
-# define DST_POLYLINE_NONLAST 0x00008000
-# define DST_RASTER_STALL 0x00010000
-# define DST_POLY_EDGE 0x00040000
-#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
-/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */
-# define DST_X_MAJOR_S 0x00000000
-# define DST_Y_MAJOR_S 0x00000001
-# define DST_Y_BOTTOM_TO_TOP_S 0x00000000
-# define DST_Y_TOP_TO_BOTTOM_S 0x00008000
-# define DST_X_RIGHT_TO_LEFT_S 0x00000000
-# define DST_X_LEFT_TO_RIGHT_S 0x80000000
-#define DP_DATATYPE 0x16C4
+# define DST_X_RIGHT_TO_LEFT 0x00000000
+# define DST_X_LEFT_TO_RIGHT 0x00000001
+# define DST_Y_BOTTOM_TO_TOP 0x00000000
+# define DST_Y_TOP_TO_BOTTOM 0x00000002
+# define DST_X_MAJOR 0x00000000
+# define DST_Y_MAJOR 0x00000004
+# define DST_X_TILE 0x00000008
+# define DST_Y_TILE 0x00000010
+# define DST_LAST_PEL 0x00000020
+# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
+# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
+# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
+# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
+# define DST_BRES_SIGN 0x00000100
+# define DST_HOST_BIG_ENDIAN_EN 0x00000200
+# define DST_POLYLINE_NONLAST 0x00008000
+# define DST_RASTER_STALL 0x00010000
+# define DST_POLY_EDGE 0x00040000
+#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
+/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */
+# define DST_X_MAJOR_S 0x00000000
+# define DST_Y_MAJOR_S 0x00000001
+# define DST_Y_BOTTOM_TO_TOP_S 0x00000000
+# define DST_Y_TOP_TO_BOTTOM_S 0x00008000
+# define DST_X_RIGHT_TO_LEFT_S 0x00000000
+# define DST_X_LEFT_TO_RIGHT_S 0x80000000
+#define DP_DATATYPE 0x16C4
/* DP_DATATYPE bit constants */
-# define DST_8BPP 0x00000002
-# define DST_15BPP 0x00000003
-# define DST_16BPP 0x00000004
-# define DST_24BPP 0x00000005
-# define DST_32BPP 0x00000006
-# define DST_8BPP_RGB332 0x00000007
-# define DST_8BPP_Y8 0x00000008
-# define DST_8BPP_RGB8 0x00000009
-# define DST_16BPP_VYUY422 0x0000000b
-# define DST_16BPP_YVYU422 0x0000000c
-# define DST_32BPP_AYUV444 0x0000000e
-# define DST_16BPP_ARGB4444 0x0000000f
-# define BRUSH_SOLIDCOLOR 0x00000d00
-# define SRC_MONO 0x00000000
-# define SRC_MONO_LBKGD 0x00010000
-# define SRC_DSTCOLOR 0x00030000
-# define BYTE_ORDER_MSB_TO_LSB 0x00000000
-# define BYTE_ORDER_LSB_TO_MSB 0x40000000
-# define DP_CONVERSION_TEMP 0x80000000
-# define HOST_BIG_ENDIAN_EN (1 << 29)
-#define DP_MIX 0x16C8
-/* DP_MIX bit constants */
-# define DP_SRC_RECT 0x00000200
-# define DP_SRC_HOST 0x00000300
-# define DP_SRC_HOST_BYTEALIGN 0x00000400
-#define DP_WRITE_MSK 0x16CC
-#define DP_XOP 0x17F8
-#define CLR_CMP_CLR_SRC 0x15C4
-#define CLR_CMP_CLR_DST 0x15C8
-#define CLR_CMP_CNTL 0x15C0
-/* CLR_CMP_CNTL bit constants */
-# define COMPARE_SRC_FALSE 0x00000000
-# define COMPARE_SRC_TRUE 0x00000001
-# define COMPARE_SRC_NOT_EQUAL 0x00000004
-# define COMPARE_SRC_EQUAL 0x00000005
-# define COMPARE_SRC_EQUAL_FLIP 0x00000007
-# define COMPARE_DST_FALSE 0x00000000
-# define COMPARE_DST_TRUE 0x00000100
-# define COMPARE_DST_NOT_EQUAL 0x00000400
-# define COMPARE_DST_EQUAL 0x00000500
-# define COMPARE_DESTINATION 0x00000000
-# define COMPARE_SOURCE 0x01000000
-# define COMPARE_SRC_AND_DST 0x02000000
-#define CLR_CMP_MSK 0x15CC
-#define DSTCACHE_MODE 0x1710
-#define DSTCACHE_CTLSTAT 0x1714
-/* DSTCACHE_CTLSTAT bit constants */
-# define RB2D_DC_FLUSH (3 << 0)
-# define RB2D_DC_FLUSH_ALL 0xf
-# define RB2D_DC_BUSY (1 << 31)
-#define DEFAULT_OFFSET 0x16e0
-#define DEFAULT_PITCH_OFFSET 0x16E0
-#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
+# define DST_8BPP 0x00000002
+# define DST_15BPP 0x00000003
+# define DST_16BPP 0x00000004
+# define DST_24BPP 0x00000005
+# define DST_32BPP 0x00000006
+# define DST_8BPP_RGB332 0x00000007
+# define DST_8BPP_Y8 0x00000008
+# define DST_8BPP_RGB8 0x00000009
+# define DST_16BPP_VYUY422 0x0000000b
+# define DST_16BPP_YVYU422 0x0000000c
+# define DST_32BPP_AYUV444 0x0000000e
+# define DST_16BPP_ARGB4444 0x0000000f
+# define BRUSH_SOLIDCOLOR 0x00000d00
+# define SRC_MONO 0x00000000
+# define SRC_MONO_LBKGD 0x00010000
+# define SRC_DSTCOLOR 0x00030000
+# define BYTE_ORDER_MSB_TO_LSB 0x00000000
+# define BYTE_ORDER_LSB_TO_MSB 0x40000000
+# define DP_CONVERSION_TEMP 0x80000000
+# define HOST_BIG_ENDIAN_EN (1 << 29)
+#define DP_MIX 0x16C8
+/* DP_MIX bit constants */
+# define DP_SRC_RECT 0x00000200
+# define DP_SRC_HOST 0x00000300
+# define DP_SRC_HOST_BYTEALIGN 0x00000400
+#define DP_WRITE_MSK 0x16CC
+#define DP_XOP 0x17F8
+#define CLR_CMP_CLR_SRC 0x15C4
+#define CLR_CMP_CLR_DST 0x15C8
+#define CLR_CMP_CNTL 0x15C0
+/* CLR_CMP_CNTL bit constants */
+# define COMPARE_SRC_FALSE 0x00000000
+# define COMPARE_SRC_TRUE 0x00000001
+# define COMPARE_SRC_NOT_EQUAL 0x00000004
+# define COMPARE_SRC_EQUAL 0x00000005
+# define COMPARE_SRC_EQUAL_FLIP 0x00000007
+# define COMPARE_DST_FALSE 0x00000000
+# define COMPARE_DST_TRUE 0x00000100
+# define COMPARE_DST_NOT_EQUAL 0x00000400
+# define COMPARE_DST_EQUAL 0x00000500
+# define COMPARE_DESTINATION 0x00000000
+# define COMPARE_SOURCE 0x01000000
+# define COMPARE_SRC_AND_DST 0x02000000
+#define CLR_CMP_MSK 0x15CC
+#define DSTCACHE_MODE 0x1710
+#define DSTCACHE_CTLSTAT 0x1714
+/* DSTCACHE_CTLSTAT bit constants */
+# define RB2D_DC_FLUSH (3 << 0)
+# define RB2D_DC_FLUSH_ALL 0xf
+# define RB2D_DC_BUSY (1 << 31)
+#define DEFAULT_OFFSET 0x16e0
+#define DEFAULT_PITCH_OFFSET 0x16E0
+#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
-# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
-# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
-#define DP_GUI_MASTER_CNTL 0x146C
+# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
+# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
+#define DP_GUI_MASTER_CNTL 0x146C
/* DP_GUI_MASTER_CNTL bit constants */
-# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
-# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
-# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
-# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
-# define GMC_SRC_CLIP_DEFAULT 0x00000000
-# define GMC_SRC_CLIP_LEAVE 0x00000004
-# define GMC_DST_CLIP_DEFAULT 0x00000000
-# define GMC_DST_CLIP_LEAVE 0x00000008
-# define GMC_BRUSH_8x8MONO 0x00000000
-# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
-# define GMC_BRUSH_8x1MONO 0x00000020
-# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
-# define GMC_BRUSH_1x8MONO 0x00000040
-# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
-# define GMC_BRUSH_32x1MONO 0x00000060
-# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
-# define GMC_BRUSH_32x32MONO 0x00000080
-# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
-# define GMC_BRUSH_8x8COLOR 0x000000a0
-# define GMC_BRUSH_8x1COLOR 0x000000b0
-# define GMC_BRUSH_1x8COLOR 0x000000c0
-# define GMC_BRUSH_SOLID_COLOR 0x000000d0
-# define GMC_DST_8BPP 0x00000200
-# define GMC_DST_15BPP 0x00000300
-# define GMC_DST_16BPP 0x00000400
-# define GMC_DST_24BPP 0x00000500
-# define GMC_DST_32BPP 0x00000600
-# define GMC_DST_8BPP_RGB332 0x00000700
-# define GMC_DST_8BPP_Y8 0x00000800
-# define GMC_DST_8BPP_RGB8 0x00000900
-# define GMC_DST_16BPP_VYUY422 0x00000b00
-# define GMC_DST_16BPP_YVYU422 0x00000c00
-# define GMC_DST_32BPP_AYUV444 0x00000e00
-# define GMC_DST_16BPP_ARGB4444 0x00000f00
-# define GMC_SRC_MONO 0x00000000
-# define GMC_SRC_MONO_LBKGD 0x00001000
-# define GMC_SRC_DSTCOLOR 0x00003000
-# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
-# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
-# define GMC_DP_CONVERSION_TEMP_9300 0x00008000
-# define GMC_DP_CONVERSION_TEMP_6500 0x00000000
-# define GMC_DP_SRC_RECT 0x02000000
-# define GMC_DP_SRC_HOST 0x03000000
-# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
-# define GMC_3D_FCN_EN_CLR 0x00000000
-# define GMC_3D_FCN_EN_SET 0x08000000
-# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
-# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
-# define GMC_AUX_CLIP_LEAVE 0x00000000
-# define GMC_AUX_CLIP_CLEAR 0x20000000
-# define GMC_WRITE_MASK_LEAVE 0x00000000
-# define GMC_WRITE_MASK_SET 0x40000000
-# define GMC_CLR_CMP_CNTL_DIS (1 << 28)
-# define GMC_SRC_DATATYPE_COLOR (3 << 12)
-# define ROP3_S 0x00cc0000
-# define ROP3_SRCCOPY 0x00cc0000
-# define ROP3_P 0x00f00000
-# define ROP3_PATCOPY 0x00f00000
-# define DP_SRC_SOURCE_MASK (7 << 24)
-# define GMC_BRUSH_NONE (15 << 4)
-# define DP_SRC_SOURCE_MEMORY (2 << 24)
-# define GMC_BRUSH_SOLIDCOLOR 0x000000d0
-#define SC_TOP_LEFT 0x16EC
-#define SC_BOTTOM_RIGHT 0x16F0
-#define SRC_SC_BOTTOM_RIGHT 0x16F4
-#define RB2D_DSTCACHE_CTLSTAT 0x342C
-#define RB2D_DSTCACHE_MODE 0x3428
-
-#define BASE_CODE 0x0f0b
-#define RADEON_BIOS_0_SCRATCH 0x0010
-#define RADEON_BIOS_1_SCRATCH 0x0014
-#define RADEON_BIOS_2_SCRATCH 0x0018
-#define RADEON_BIOS_3_SCRATCH 0x001c
-#define RADEON_BIOS_4_SCRATCH 0x0020
-#define RADEON_BIOS_5_SCRATCH 0x0024
-#define RADEON_BIOS_6_SCRATCH 0x0028
-#define RADEON_BIOS_7_SCRATCH 0x002c
-
-
-#define CLK_PIN_CNTL 0x0001
-#define PPLL_CNTL 0x0002
-# define PPLL_RESET (1 << 0)
-# define PPLL_SLEEP (1 << 1)
-# define PPLL_ATOMIC_UPDATE_EN (1 << 16)
-# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
-#define PPLL_REF_DIV 0x0003
-# define PPLL_REF_DIV_MASK 0x03ff
-# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-#define PPLL_DIV_0 0x0004
-#define PPLL_DIV_1 0x0005
-#define PPLL_DIV_2 0x0006
-#define PPLL_DIV_3 0x0007
-#define VCLK_ECP_CNTL 0x0008
-#define HTOTAL_CNTL 0x0009
-#define HTOTAL2_CNTL 0x002e /* PLL */
-#define M_SPLL_REF_FB_DIV 0x000a
-#define AGP_PLL_CNTL 0x000b
-#define SPLL_CNTL 0x000c
-#define SCLK_CNTL 0x000d
-#define MPLL_CNTL 0x000e
-#define MCLK_CNTL 0x0012
+# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
+# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
+# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
+# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
+# define GMC_SRC_CLIP_DEFAULT 0x00000000
+# define GMC_SRC_CLIP_LEAVE 0x00000004
+# define GMC_DST_CLIP_DEFAULT 0x00000000
+# define GMC_DST_CLIP_LEAVE 0x00000008
+# define GMC_BRUSH_8x8MONO 0x00000000
+# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
+# define GMC_BRUSH_8x1MONO 0x00000020
+# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
+# define GMC_BRUSH_1x8MONO 0x00000040
+# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
+# define GMC_BRUSH_32x1MONO 0x00000060
+# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
+# define GMC_BRUSH_32x32MONO 0x00000080
+# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
+# define GMC_BRUSH_8x8COLOR 0x000000a0
+# define GMC_BRUSH_8x1COLOR 0x000000b0
+# define GMC_BRUSH_1x8COLOR 0x000000c0
+# define GMC_BRUSH_SOLID_COLOR 0x000000d0
+# define GMC_DST_8BPP 0x00000200
+# define GMC_DST_15BPP 0x00000300
+# define GMC_DST_16BPP 0x00000400
+# define GMC_DST_24BPP 0x00000500
+# define GMC_DST_32BPP 0x00000600
+# define GMC_DST_8BPP_RGB332 0x00000700
+# define GMC_DST_8BPP_Y8 0x00000800
+# define GMC_DST_8BPP_RGB8 0x00000900
+# define GMC_DST_16BPP_VYUY422 0x00000b00
+# define GMC_DST_16BPP_YVYU422 0x00000c00
+# define GMC_DST_32BPP_AYUV444 0x00000e00
+# define GMC_DST_16BPP_ARGB4444 0x00000f00
+# define GMC_SRC_MONO 0x00000000
+# define GMC_SRC_MONO_LBKGD 0x00001000
+# define GMC_SRC_DSTCOLOR 0x00003000
+# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
+# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
+# define GMC_DP_CONVERSION_TEMP_9300 0x00008000
+# define GMC_DP_CONVERSION_TEMP_6500 0x00000000
+# define GMC_DP_SRC_RECT 0x02000000
+# define GMC_DP_SRC_HOST 0x03000000
+# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
+# define GMC_3D_FCN_EN_CLR 0x00000000
+# define GMC_3D_FCN_EN_SET 0x08000000
+# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
+# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
+# define GMC_AUX_CLIP_LEAVE 0x00000000
+# define GMC_AUX_CLIP_CLEAR 0x20000000
+# define GMC_WRITE_MASK_LEAVE 0x00000000
+# define GMC_WRITE_MASK_SET 0x40000000
+# define GMC_CLR_CMP_CNTL_DIS (1 << 28)
+# define GMC_SRC_DATATYPE_COLOR (3 << 12)
+# define ROP3_S 0x00cc0000
+# define ROP3_SRCCOPY 0x00cc0000
+# define ROP3_P 0x00f00000
+# define ROP3_PATCOPY 0x00f00000
+# define DP_SRC_SOURCE_MASK (7 << 24)
+# define GMC_BRUSH_NONE (15 << 4)
+# define DP_SRC_SOURCE_MEMORY (2 << 24)
+# define GMC_BRUSH_SOLIDCOLOR 0x000000d0
+#define SC_TOP_LEFT 0x16EC
+#define SC_BOTTOM_RIGHT 0x16F0
+#define SRC_SC_BOTTOM_RIGHT 0x16F4
+#define RB2D_DSTCACHE_CTLSTAT 0x342C
+#define RB2D_DSTCACHE_MODE 0x3428
+
+#define BASE_CODE 0x0f0b
+#define RADEON_BIOS_0_SCRATCH 0x0010
+#define RADEON_BIOS_1_SCRATCH 0x0014
+#define RADEON_BIOS_2_SCRATCH 0x0018
+#define RADEON_BIOS_3_SCRATCH 0x001c
+#define RADEON_BIOS_4_SCRATCH 0x0020
+#define RADEON_BIOS_5_SCRATCH 0x0024
+#define RADEON_BIOS_6_SCRATCH 0x0028
+#define RADEON_BIOS_7_SCRATCH 0x002c
+
+
+#define CLK_PIN_CNTL 0x0001
+#define PPLL_CNTL 0x0002
+# define PPLL_RESET (1 << 0)
+# define PPLL_SLEEP (1 << 1)
+# define PPLL_ATOMIC_UPDATE_EN (1 << 16)
+# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
+# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
+#define PPLL_REF_DIV 0x0003
+# define PPLL_REF_DIV_MASK 0x03ff
+# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
+# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
+#define PPLL_DIV_0 0x0004
+#define PPLL_DIV_1 0x0005
+#define PPLL_DIV_2 0x0006
+#define PPLL_DIV_3 0x0007
+#define VCLK_ECP_CNTL 0x0008
+#define HTOTAL_CNTL 0x0009
+#define HTOTAL2_CNTL 0x002e /* PLL */
+#define M_SPLL_REF_FB_DIV 0x000a
+#define AGP_PLL_CNTL 0x000b
+#define SPLL_CNTL 0x000c
+#define SCLK_CNTL 0x000d
+#define MPLL_CNTL 0x000e
+#define MCLK_CNTL 0x0012
/* MCLK_CNTL bit constants */
-# define FORCEON_MCLKA (1 << 16)
-# define FORCEON_MCLKB (1 << 17)
-# define FORCEON_YCLKA (1 << 18)
-# define FORCEON_YCLKB (1 << 19)
-# define FORCEON_MC (1 << 20)
-# define FORCEON_AIC (1 << 21)
-#define PLL_TEST_CNTL 0x0013
-#define P2PLL_CNTL 0x002a /* P2PLL */
-# define P2PLL_RESET (1 << 0)
-# define P2PLL_SLEEP (1 << 1)
-# define P2PLL_ATOMIC_UPDATE_EN (1 << 16)
-# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
-#define P2PLL_DIV_0 0x002c
-# define P2PLL_FB0_DIV_MASK 0x07ff
-# define P2PLL_POST0_DIV_MASK 0x00070000
-#define P2PLL_REF_DIV 0x002B /* PLL */
-# define P2PLL_REF_DIV_MASK 0x03ff
-# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
+# define FORCEON_MCLKA (1 << 16)
+# define FORCEON_MCLKB (1 << 17)
+# define FORCEON_YCLKA (1 << 18)
+# define FORCEON_YCLKB (1 << 19)
+# define FORCEON_MC (1 << 20)
+# define FORCEON_AIC (1 << 21)
+#define PLL_TEST_CNTL 0x0013
+#define P2PLL_CNTL 0x002a /* P2PLL */
+# define P2PLL_RESET (1 << 0)
+# define P2PLL_SLEEP (1 << 1)
+# define P2PLL_ATOMIC_UPDATE_EN (1 << 16)
+# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
+# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
+#define P2PLL_DIV_0 0x002c
+# define P2PLL_FB0_DIV_MASK 0x07ff
+# define P2PLL_POST0_DIV_MASK 0x00070000
+#define P2PLL_REF_DIV 0x002B /* PLL */
+# define P2PLL_REF_DIV_MASK 0x03ff
+# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
+# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
/* masks */
-#define CONFIG_MEMSIZE_MASK 0x1f000000
-#define MEM_CFG_TYPE 0x40000000
-#define DST_OFFSET_MASK 0x003fffff
-#define DST_PITCH_MASK 0x3fc00000
-#define DEFAULT_TILE_MASK 0xc0000000
-#define PPLL_DIV_SEL_MASK 0x00000300
-#define PPLL_FB3_DIV_MASK 0x000007ff
-#define PPLL_POST3_DIV_MASK 0x00070000
-
-#define GUI_ACTIVE 0x80000000
-
-/* GEN_RESET_CNTL bit constants */
-#define SOFT_RESET_GUI 0x00000001
-#define SOFT_RESET_VCLK 0x00000100
-#define SOFT_RESET_PCLK 0x00000200
-#define SOFT_RESET_ECP 0x00000400
-#define SOFT_RESET_DISPENG_XCLK 0x00000800
-
-/* RAGE THEATER REGISTERS */
-
-#define DMA_VIPH0_COMMAND 0x0A00
-#define DMA_VIPH1_COMMAND 0x0A04
-#define DMA_VIPH2_COMMAND 0x0A08
-#define DMA_VIPH3_COMMAND 0x0A0C
-#define DMA_VIPH_STATUS 0x0A10
-#define DMA_VIPH_CHUNK_0 0x0A18
-#define DMA_VIPH_CHUNK_1_VAL 0x0A1C
-#define DMA_VIP0_TABLE_ADDR 0x0A20
-#define DMA_VIPH0_ACTIVE 0x0A24
-#define DMA_VIP1_TABLE_ADDR 0x0A30
-#define DMA_VIPH1_ACTIVE 0x0A34
-#define DMA_VIP2_TABLE_ADDR 0x0A40
-#define DMA_VIPH2_ACTIVE 0x0A44
-#define DMA_VIP3_TABLE_ADDR 0x0A50
-#define DMA_VIPH3_ACTIVE 0x0A54
-#define DMA_VIPH_ABORT 0x0A88
-
-#define VIPH_CH0_DATA 0x0c00
-#define VIPH_CH1_DATA 0x0c04
-#define VIPH_CH2_DATA 0x0c08
-#define VIPH_CH3_DATA 0x0c0c
-#define VIPH_CH0_ADDR 0x0c10
-#define VIPH_CH1_ADDR 0x0c14
-#define VIPH_CH2_ADDR 0x0c18
-#define VIPH_CH3_ADDR 0x0c1c
-#define VIPH_CH0_SBCNT 0x0c20
-#define VIPH_CH1_SBCNT 0x0c24
-#define VIPH_CH2_SBCNT 0x0c28
-#define VIPH_CH3_SBCNT 0x0c2c
-#define VIPH_CH0_ABCNT 0x0c30
-#define VIPH_CH1_ABCNT 0x0c34
-#define VIPH_CH2_ABCNT 0x0c38
-#define VIPH_CH3_ABCNT 0x0c3c
-#define VIPH_CONTROL 0x0c40
-#define VIPH_DV_LAT 0x0c44
-#define VIPH_BM_CHUNK 0x0c48
-#define VIPH_DV_INT 0x0c4c
-#define VIPH_TIMEOUT_STAT 0x0c50
-
-#define VIPH_REG_DATA 0x0084
-#define VIPH_REG_ADDR 0x0080
-
-/* Address Space Rage Theatre Registers (VIP Access) */
-#define VIP_VIP_VENDOR_DEVICE_ID 0x0000
-#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004
-#define VIP_VIP_COMMAND_STATUS 0x0008
-#define VIP_VIP_REVISION_ID 0x000c
-#define VIP_HW_DEBUG 0x0010
-#define VIP_SW_SCRATCH 0x0014
-#define VIP_I2C_CNTL_0 0x0020
-#define VIP_I2C_CNTL_1 0x0024
-#define VIP_I2C_DATA 0x0028
-#define VIP_INT_CNTL 0x002c
-#define VIP_GPIO_INOUT 0x0030
-#define VIP_GPIO_CNTL 0x0034
-#define VIP_CLKOUT_GPIO_CNTL 0x0038
-#define VIP_RIPINTF_PORT_CNTL 0x003c
-#define VIP_ADC_CNTL 0x0400
-#define VIP_ADC_DEBUG 0x0404
-#define VIP_STANDARD_SELECT 0x0408
-#define VIP_THERMO2BIN_STATUS 0x040c
-#define VIP_COMB_CNTL0 0x0440
-#define VIP_COMB_CNTL1 0x0444
-#define VIP_COMB_CNTL2 0x0448
-#define VIP_COMB_LINE_LENGTH 0x044c
-#define VIP_NOISE_CNTL0 0x0450
-#define VIP_HS_PLINE 0x0480
-#define VIP_HS_DTOINC 0x0484
-#define VIP_HS_PLLGAIN 0x0488
-#define VIP_HS_MINMAXWIDTH 0x048c
-#define VIP_HS_GENLOCKDELAY 0x0490
-#define VIP_HS_WINDOW_LIMIT 0x0494
-#define VIP_HS_WINDOW_OC_SPEED 0x0498
-#define VIP_HS_PULSE_WIDTH 0x049c
-#define VIP_HS_PLL_ERROR 0x04a0
-#define VIP_HS_PLL_FS_PATH 0x04a4
-#define VIP_SG_BLACK_GATE 0x04c0
-#define VIP_SG_SYNCTIP_GATE 0x04c4
-#define VIP_SG_UVGATE_GATE 0x04c8
-#define VIP_LP_AGC_CLAMP_CNTL0 0x0500
-#define VIP_LP_AGC_CLAMP_CNTL1 0x0504
-#define VIP_LP_BRIGHTNESS 0x0508
-#define VIP_LP_CONTRAST 0x050c
-#define VIP_LP_SLICE_LIMIT 0x0510
-#define VIP_LP_WPA_CNTL0 0x0514
-#define VIP_LP_WPA_CNTL1 0x0518
-#define VIP_LP_BLACK_LEVEL 0x051c
-#define VIP_LP_SLICE_LEVEL 0x0520
-#define VIP_LP_SYNCTIP_LEVEL 0x0524
-#define VIP_LP_VERT_LOCKOUT 0x0528
-#define VIP_VS_DETECTOR_CNTL 0x0540
-#define VIP_VS_BLANKING_CNTL 0x0544
-#define VIP_VS_FIELD_ID_CNTL 0x0548
-#define VIP_VS_COUNTER_CNTL 0x054c
-#define VIP_VS_FRAME_TOTAL 0x0550
-#define VIP_VS_LINE_COUNT 0x0554
-#define VIP_CP_PLL_CNTL0 0x0580
-#define VIP_CP_PLL_CNTL1 0x0584
-#define VIP_CP_HUE_CNTL 0x0588
-#define VIP_CP_BURST_GAIN 0x058c
-#define VIP_CP_AGC_CNTL 0x0590
-#define VIP_CP_ACTIVE_GAIN 0x0594
-#define VIP_CP_PLL_STATUS0 0x0598
-#define VIP_CP_PLL_STATUS1 0x059c
-#define VIP_CP_PLL_STATUS2 0x05a0
-#define VIP_CP_PLL_STATUS3 0x05a4
-#define VIP_CP_PLL_STATUS4 0x05a8
-#define VIP_CP_PLL_STATUS5 0x05ac
-#define VIP_CP_PLL_STATUS6 0x05b0
-#define VIP_CP_PLL_STATUS7 0x05b4
-#define VIP_CP_DEBUG_FORCE 0x05b8
-#define VIP_CP_VERT_LOCKOUT 0x05bc
-#define VIP_H_ACTIVE_WINDOW 0x05c0
-#define VIP_V_ACTIVE_WINDOW 0x05c4
-#define VIP_H_VBI_WINDOW 0x05c8
-#define VIP_V_VBI_WINDOW 0x05cc
-#define VIP_VBI_CONTROL 0x05d0
-#define VIP_DECODER_DEBUG_CNTL 0x05d4
-#define VIP_SINGLE_STEP_DATA 0x05d8
-#define VIP_MASTER_CNTL 0x0040
-#define VIP_RGB_CNTL 0x0048
-#define VIP_CLKOUT_CNTL 0x004c
-#define VIP_SYNC_CNTL 0x0050
-#define VIP_I2C_CNTL 0x0054
-#define VIP_HTOTAL 0x0080
-#define VIP_HDISP 0x0084
-#define VIP_HSIZE 0x0088
-#define VIP_HSTART 0x008c
-#define VIP_HCOUNT 0x0090
-#define VIP_VTOTAL 0x0094
-#define VIP_VDISP 0x0098
-#define VIP_VCOUNT 0x009c
-#define VIP_VFTOTAL 0x00a0
-#define VIP_DFCOUNT 0x00a4
-#define VIP_DFRESTART 0x00a8
-#define VIP_DHRESTART 0x00ac
-#define VIP_DVRESTART 0x00b0
-#define VIP_SYNC_SIZE 0x00b4
-#define VIP_TV_PLL_FINE_CNTL 0x00b8
-#define VIP_CRT_PLL_FINE_CNTL 0x00bc
-#define VIP_TV_PLL_CNTL 0x00c0
-#define VIP_CRT_PLL_CNTL 0x00c4
-#define VIP_PLL_CNTL0 0x00c8
-#define VIP_PLL_TEST_CNTL 0x00cc
-#define VIP_CLOCK_SEL_CNTL 0x00d0
-#define VIP_VIN_PLL_CNTL 0x00d4
-#define VIP_VIN_PLL_FINE_CNTL 0x00d8
-#define VIP_AUD_PLL_CNTL 0x00e0
-#define VIP_AUD_PLL_FINE_CNTL 0x00e4
-#define VIP_AUD_CLK_DIVIDERS 0x00e8
-#define VIP_AUD_DTO_INCREMENTS 0x00ec
-#define VIP_L54_PLL_CNTL 0x00f0
-#define VIP_L54_PLL_FINE_CNTL 0x00f4
-#define VIP_L54_DTO_INCREMENTS 0x00f8
-#define VIP_PLL_CNTL1 0x00fc
-#define VIP_FRAME_LOCK_CNTL 0x0100
-#define VIP_SYNC_LOCK_CNTL 0x0104
-#define VIP_TVO_SYNC_PAT_ACCUM 0x0108
-#define VIP_TVO_SYNC_THRESHOLD 0x010c
-#define VIP_TVO_SYNC_PAT_EXPECT 0x0110
-#define VIP_DELAY_ONE_MAP_A 0x0114
-#define VIP_DELAY_ONE_MAP_B 0x0118
-#define VIP_DELAY_ZERO_MAP_A 0x011c
-#define VIP_DELAY_ZERO_MAP_B 0x0120
-#define VIP_TVO_DATA_DELAY_A 0x0140
-#define VIP_TVO_DATA_DELAY_B 0x0144
-#define VIP_HOST_READ_DATA 0x0180
-#define VIP_HOST_WRITE_DATA 0x0184
-#define VIP_HOST_RD_WT_CNTL 0x0188
-#define VIP_VSCALER_CNTL1 0x01c0
-#define VIP_TIMING_CNTL 0x01c4
-#define VIP_VSCALER_CNTL2 0x01c8
-#define VIP_Y_FALL_CNTL 0x01cc
-#define VIP_Y_RISE_CNTL 0x01d0
-#define VIP_Y_SAW_TOOTH_CNTL 0x01d4
-#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0
-#define VIP_GAIN_LIMIT_SETTINGS 0x01e4
-#define VIP_LINEAR_GAIN_SETTINGS 0x01e8
-#define VIP_MODULATOR_CNTL1 0x0200
-#define VIP_MODULATOR_CNTL2 0x0204
-#define VIP_MV_MODE_CNTL 0x0208
-#define VIP_MV_STRIPE_CNTL 0x020c
-#define VIP_MV_LEVEL_CNTL1 0x0210
-#define VIP_MV_LEVEL_CNTL2 0x0214
-#define VIP_PRE_DAC_MUX_CNTL 0x0240
-#define VIP_TV_DAC_CNTL 0x0280
-#define VIP_CRC_CNTL 0x02c0
-#define VIP_VIDEO_PORT_SIG 0x02c4
-#define VIP_VBI_CC_CNTL 0x02c8
-#define VIP_VBI_EDS_CNTL 0x02cc
-#define VIP_VBI_20BIT_CNTL 0x02d0
-#define VIP_VBI_DTO_CNTL 0x02d4
-#define VIP_VBI_LEVEL_CNTL 0x02d8
-#define VIP_UV_ADR 0x0300
-#define VIP_MV_STATUS 0x0330
-#define VIP_UPSAMP_COEFF0_0 0x0340
-#define VIP_UPSAMP_COEFF0_1 0x0344
-#define VIP_UPSAMP_COEFF0_2 0x0348
-#define VIP_UPSAMP_COEFF1_0 0x034c
-#define VIP_UPSAMP_COEFF1_1 0x0350
-#define VIP_UPSAMP_COEFF1_2 0x0354
-#define VIP_UPSAMP_COEFF2_0 0x0358
-#define VIP_UPSAMP_COEFF2_1 0x035c
-#define VIP_UPSAMP_COEFF2_2 0x0360
-#define VIP_UPSAMP_COEFF3_0 0x0364
-#define VIP_UPSAMP_COEFF3_1 0x0368
-#define VIP_UPSAMP_COEFF3_2 0x036c
-#define VIP_UPSAMP_COEFF4_0 0x0370
-#define VIP_UPSAMP_COEFF4_1 0x0374
-#define VIP_UPSAMP_COEFF4_2 0x0378
-#define VIP_TV_DTO_INCREMENTS 0x0390
-#define VIP_CRT_DTO_INCREMENTS 0x0394
-#define VIP_VSYNC_DIFF_CNTL 0x03a0
-#define VIP_VSYNC_DIFF_LIMITS 0x03a4
-#define VIP_VSYNC_DIFF_RD_DATA 0x03a8
-#define VIP_SCALER_IN_WINDOW 0x0618
-#define VIP_SCALER_OUT_WINDOW 0x061c
-#define VIP_H_SCALER_CONTROL 0x0600
-#define VIP_V_SCALER_CONTROL 0x0604
-#define VIP_V_DEINTERLACE_CONTROL 0x0608
-#define VIP_VBI_SCALER_CONTROL 0x060c
-#define VIP_DVS_PORT_CTRL 0x0610
-#define VIP_DVS_PORT_READBACK 0x0614
-#define VIP_FIFOA_CONFIG 0x0800
-#define VIP_FIFOB_CONFIG 0x0804
-#define VIP_FIFOC_CONFIG 0x0808
-#define VIP_SPDIF_PORT_CNTL 0x080c
-#define VIP_SPDIF_CHANNEL_STAT 0x0810
-#define VIP_SPDIF_AC3_PREAMBLE 0x0814
-#define VIP_I2S_TRANSMIT_CNTL 0x0818
-#define VIP_I2S_RECEIVE_CNTL 0x081c
-#define VIP_SPDIF_TX_CNT_REG 0x0820
-#define VIP_IIS_TX_CNT_REG 0x0824
+#define CONFIG_MEMSIZE_MASK 0x1f000000
+#define MEM_CFG_TYPE 0x40000000
+#define DST_OFFSET_MASK 0x003fffff
+#define DST_PITCH_MASK 0x3fc00000
+#define DEFAULT_TILE_MASK 0xc0000000
+#define PPLL_DIV_SEL_MASK 0x00000300
+#define PPLL_FB3_DIV_MASK 0x000007ff
+#define PPLL_POST3_DIV_MASK 0x00070000
+
+#define GUI_ACTIVE 0x80000000
+
+/* GEN_RESET_CNTL bit constants */
+#define SOFT_RESET_GUI 0x00000001
+#define SOFT_RESET_VCLK 0x00000100
+#define SOFT_RESET_PCLK 0x00000200
+#define SOFT_RESET_ECP 0x00000400
+#define SOFT_RESET_DISPENG_XCLK 0x00000800
+
+/* RAGE THEATER REGISTERS */
+
+#define DMA_VIPH0_COMMAND 0x0A00
+#define DMA_VIPH1_COMMAND 0x0A04
+#define DMA_VIPH2_COMMAND 0x0A08
+#define DMA_VIPH3_COMMAND 0x0A0C
+#define DMA_VIPH_STATUS 0x0A10
+#define DMA_VIPH_CHUNK_0 0x0A18
+#define DMA_VIPH_CHUNK_1_VAL 0x0A1C
+#define DMA_VIP0_TABLE_ADDR 0x0A20
+#define DMA_VIPH0_ACTIVE 0x0A24
+#define DMA_VIP1_TABLE_ADDR 0x0A30
+#define DMA_VIPH1_ACTIVE 0x0A34
+#define DMA_VIP2_TABLE_ADDR 0x0A40
+#define DMA_VIPH2_ACTIVE 0x0A44
+#define DMA_VIP3_TABLE_ADDR 0x0A50
+#define DMA_VIPH3_ACTIVE 0x0A54
+#define DMA_VIPH_ABORT 0x0A88
+
+#define VIPH_CH0_DATA 0x0c00
+#define VIPH_CH1_DATA 0x0c04
+#define VIPH_CH2_DATA 0x0c08
+#define VIPH_CH3_DATA 0x0c0c
+#define VIPH_CH0_ADDR 0x0c10
+#define VIPH_CH1_ADDR 0x0c14
+#define VIPH_CH2_ADDR 0x0c18
+#define VIPH_CH3_ADDR 0x0c1c
+#define VIPH_CH0_SBCNT 0x0c20
+#define VIPH_CH1_SBCNT 0x0c24
+#define VIPH_CH2_SBCNT 0x0c28
+#define VIPH_CH3_SBCNT 0x0c2c
+#define VIPH_CH0_ABCNT 0x0c30
+#define VIPH_CH1_ABCNT 0x0c34
+#define VIPH_CH2_ABCNT 0x0c38
+#define VIPH_CH3_ABCNT 0x0c3c
+#define VIPH_CONTROL 0x0c40
+#define VIPH_DV_LAT 0x0c44
+#define VIPH_BM_CHUNK 0x0c48
+#define VIPH_DV_INT 0x0c4c
+#define VIPH_TIMEOUT_STAT 0x0c50
+
+#define VIPH_REG_DATA 0x0084
+#define VIPH_REG_ADDR 0x0080
+
+/* Address Space Rage Theatre Registers (VIP Access) */
+#define VIP_VIP_VENDOR_DEVICE_ID 0x0000
+#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004
+#define VIP_VIP_COMMAND_STATUS 0x0008
+#define VIP_VIP_REVISION_ID 0x000c
+#define VIP_HW_DEBUG 0x0010
+#define VIP_SW_SCRATCH 0x0014
+#define VIP_I2C_CNTL_0 0x0020
+#define VIP_I2C_CNTL_1 0x0024
+#define VIP_I2C_DATA 0x0028
+#define VIP_INT_CNTL 0x002c
+#define VIP_GPIO_INOUT 0x0030
+#define VIP_GPIO_CNTL 0x0034
+#define VIP_CLKOUT_GPIO_CNTL 0x0038
+#define VIP_RIPINTF_PORT_CNTL 0x003c
+#define VIP_ADC_CNTL 0x0400
+#define VIP_ADC_DEBUG 0x0404
+#define VIP_STANDARD_SELECT 0x0408
+#define VIP_THERMO2BIN_STATUS 0x040c
+#define VIP_COMB_CNTL0 0x0440
+#define VIP_COMB_CNTL1 0x0444
+#define VIP_COMB_CNTL2 0x0448
+#define VIP_COMB_LINE_LENGTH 0x044c
+#define VIP_NOISE_CNTL0 0x0450
+#define VIP_HS_PLINE 0x0480
+#define VIP_HS_DTOINC 0x0484
+#define VIP_HS_PLLGAIN 0x0488
+#define VIP_HS_MINMAXWIDTH 0x048c
+#define VIP_HS_GENLOCKDELAY 0x0490
+#define VIP_HS_WINDOW_LIMIT 0x0494
+#define VIP_HS_WINDOW_OC_SPEED 0x0498
+#define VIP_HS_PULSE_WIDTH 0x049c
+#define VIP_HS_PLL_ERROR 0x04a0
+#define VIP_HS_PLL_FS_PATH 0x04a4
+#define VIP_SG_BLACK_GATE 0x04c0
+#define VIP_SG_SYNCTIP_GATE 0x04c4
+#define VIP_SG_UVGATE_GATE 0x04c8
+#define VIP_LP_AGC_CLAMP_CNTL0 0x0500
+#define VIP_LP_AGC_CLAMP_CNTL1 0x0504
+#define VIP_LP_BRIGHTNESS 0x0508
+#define VIP_LP_CONTRAST 0x050c
+#define VIP_LP_SLICE_LIMIT 0x0510
+#define VIP_LP_WPA_CNTL0 0x0514
+#define VIP_LP_WPA_CNTL1 0x0518
+#define VIP_LP_BLACK_LEVEL 0x051c
+#define VIP_LP_SLICE_LEVEL 0x0520
+#define VIP_LP_SYNCTIP_LEVEL 0x0524
+#define VIP_LP_VERT_LOCKOUT 0x0528
+#define VIP_VS_DETECTOR_CNTL 0x0540
+#define VIP_VS_BLANKING_CNTL 0x0544
+#define VIP_VS_FIELD_ID_CNTL 0x0548
+#define VIP_VS_COUNTER_CNTL 0x054c
+#define VIP_VS_FRAME_TOTAL 0x0550
+#define VIP_VS_LINE_COUNT 0x0554
+#define VIP_CP_PLL_CNTL0 0x0580
+#define VIP_CP_PLL_CNTL1 0x0584
+#define VIP_CP_HUE_CNTL 0x0588
+#define VIP_CP_BURST_GAIN 0x058c
+#define VIP_CP_AGC_CNTL 0x0590
+#define VIP_CP_ACTIVE_GAIN 0x0594
+#define VIP_CP_PLL_STATUS0 0x0598
+#define VIP_CP_PLL_STATUS1 0x059c
+#define VIP_CP_PLL_STATUS2 0x05a0
+#define VIP_CP_PLL_STATUS3 0x05a4
+#define VIP_CP_PLL_STATUS4 0x05a8
+#define VIP_CP_PLL_STATUS5 0x05ac
+#define VIP_CP_PLL_STATUS6 0x05b0
+#define VIP_CP_PLL_STATUS7 0x05b4
+#define VIP_CP_DEBUG_FORCE 0x05b8
+#define VIP_CP_VERT_LOCKOUT 0x05bc
+#define VIP_H_ACTIVE_WINDOW 0x05c0
+#define VIP_V_ACTIVE_WINDOW 0x05c4
+#define VIP_H_VBI_WINDOW 0x05c8
+#define VIP_V_VBI_WINDOW 0x05cc
+#define VIP_VBI_CONTROL 0x05d0
+#define VIP_DECODER_DEBUG_CNTL 0x05d4
+#define VIP_SINGLE_STEP_DATA 0x05d8
+#define VIP_MASTER_CNTL 0x0040
+#define VIP_RGB_CNTL 0x0048
+#define VIP_CLKOUT_CNTL 0x004c
+#define VIP_SYNC_CNTL 0x0050
+#define VIP_I2C_CNTL 0x0054
+#define VIP_HTOTAL 0x0080
+#define VIP_HDISP 0x0084
+#define VIP_HSIZE 0x0088
+#define VIP_HSTART 0x008c
+#define VIP_HCOUNT 0x0090
+#define VIP_VTOTAL 0x0094
+#define VIP_VDISP 0x0098
+#define VIP_VCOUNT 0x009c
+#define VIP_VFTOTAL 0x00a0
+#define VIP_DFCOUNT 0x00a4
+#define VIP_DFRESTART 0x00a8
+#define VIP_DHRESTART 0x00ac
+#define VIP_DVRESTART 0x00b0
+#define VIP_SYNC_SIZE 0x00b4
+#define VIP_TV_PLL_FINE_CNTL 0x00b8
+#define VIP_CRT_PLL_FINE_CNTL 0x00bc
+#define VIP_TV_PLL_CNTL 0x00c0
+#define VIP_CRT_PLL_CNTL 0x00c4
+#define VIP_PLL_CNTL0 0x00c8
+#define VIP_PLL_TEST_CNTL 0x00cc
+#define VIP_CLOCK_SEL_CNTL 0x00d0
+#define VIP_VIN_PLL_CNTL 0x00d4
+#define VIP_VIN_PLL_FINE_CNTL 0x00d8
+#define VIP_AUD_PLL_CNTL 0x00e0
+#define VIP_AUD_PLL_FINE_CNTL 0x00e4
+#define VIP_AUD_CLK_DIVIDERS 0x00e8
+#define VIP_AUD_DTO_INCREMENTS 0x00ec
+#define VIP_L54_PLL_CNTL 0x00f0
+#define VIP_L54_PLL_FINE_CNTL 0x00f4
+#define VIP_L54_DTO_INCREMENTS 0x00f8
+#define VIP_PLL_CNTL1 0x00fc
+#define VIP_FRAME_LOCK_CNTL 0x0100
+#define VIP_SYNC_LOCK_CNTL 0x0104
+#define VIP_TVO_SYNC_PAT_ACCUM 0x0108
+#define VIP_TVO_SYNC_THRESHOLD 0x010c
+#define VIP_TVO_SYNC_PAT_EXPECT 0x0110
+#define VIP_DELAY_ONE_MAP_A 0x0114
+#define VIP_DELAY_ONE_MAP_B 0x0118
+#define VIP_DELAY_ZERO_MAP_A 0x011c
+#define VIP_DELAY_ZERO_MAP_B 0x0120
+#define VIP_TVO_DATA_DELAY_A 0x0140
+#define VIP_TVO_DATA_DELAY_B 0x0144
+#define VIP_HOST_READ_DATA 0x0180
+#define VIP_HOST_WRITE_DATA 0x0184
+#define VIP_HOST_RD_WT_CNTL 0x0188
+#define VIP_VSCALER_CNTL1 0x01c0
+#define VIP_TIMING_CNTL 0x01c4
+#define VIP_VSCALER_CNTL2 0x01c8
+#define VIP_Y_FALL_CNTL 0x01cc
+#define VIP_Y_RISE_CNTL 0x01d0
+#define VIP_Y_SAW_TOOTH_CNTL 0x01d4
+#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0
+#define VIP_GAIN_LIMIT_SETTINGS 0x01e4
+#define VIP_LINEAR_GAIN_SETTINGS 0x01e8
+#define VIP_MODULATOR_CNTL1 0x0200
+#define VIP_MODULATOR_CNTL2 0x0204
+#define VIP_MV_MODE_CNTL 0x0208
+#define VIP_MV_STRIPE_CNTL 0x020c
+#define VIP_MV_LEVEL_CNTL1 0x0210
+#define VIP_MV_LEVEL_CNTL2 0x0214
+#define VIP_PRE_DAC_MUX_CNTL 0x0240
+#define VIP_TV_DAC_CNTL 0x0280
+#define VIP_CRC_CNTL 0x02c0
+#define VIP_VIDEO_PORT_SIG 0x02c4
+#define VIP_VBI_CC_CNTL 0x02c8
+#define VIP_VBI_EDS_CNTL 0x02cc
+#define VIP_VBI_20BIT_CNTL 0x02d0
+#define VIP_VBI_DTO_CNTL 0x02d4
+#define VIP_VBI_LEVEL_CNTL 0x02d8
+#define VIP_UV_ADR 0x0300
+#define VIP_MV_STATUS 0x0330
+#define VIP_UPSAMP_COEFF0_0 0x0340
+#define VIP_UPSAMP_COEFF0_1 0x0344
+#define VIP_UPSAMP_COEFF0_2 0x0348
+#define VIP_UPSAMP_COEFF1_0 0x034c
+#define VIP_UPSAMP_COEFF1_1 0x0350
+#define VIP_UPSAMP_COEFF1_2 0x0354
+#define VIP_UPSAMP_COEFF2_0 0x0358
+#define VIP_UPSAMP_COEFF2_1 0x035c
+#define VIP_UPSAMP_COEFF2_2 0x0360
+#define VIP_UPSAMP_COEFF3_0 0x0364
+#define VIP_UPSAMP_COEFF3_1 0x0368
+#define VIP_UPSAMP_COEFF3_2 0x036c
+#define VIP_UPSAMP_COEFF4_0 0x0370
+#define VIP_UPSAMP_COEFF4_1 0x0374
+#define VIP_UPSAMP_COEFF4_2 0x0378
+#define VIP_TV_DTO_INCREMENTS 0x0390
+#define VIP_CRT_DTO_INCREMENTS 0x0394
+#define VIP_VSYNC_DIFF_CNTL 0x03a0
+#define VIP_VSYNC_DIFF_LIMITS 0x03a4
+#define VIP_VSYNC_DIFF_RD_DATA 0x03a8
+#define VIP_SCALER_IN_WINDOW 0x0618
+#define VIP_SCALER_OUT_WINDOW 0x061c
+#define VIP_H_SCALER_CONTROL 0x0600
+#define VIP_V_SCALER_CONTROL 0x0604
+#define VIP_V_DEINTERLACE_CONTROL 0x0608
+#define VIP_VBI_SCALER_CONTROL 0x060c
+#define VIP_DVS_PORT_CTRL 0x0610
+#define VIP_DVS_PORT_READBACK 0x0614
+#define VIP_FIFOA_CONFIG 0x0800
+#define VIP_FIFOB_CONFIG 0x0804
+#define VIP_FIFOC_CONFIG 0x0808
+#define VIP_SPDIF_PORT_CNTL 0x080c
+#define VIP_SPDIF_CHANNEL_STAT 0x0810
+#define VIP_SPDIF_AC3_PREAMBLE 0x0814
+#define VIP_I2S_TRANSMIT_CNTL 0x0818
+#define VIP_I2S_RECEIVE_CNTL 0x081c
+#define VIP_SPDIF_TX_CNT_REG 0x0820
+#define VIP_IIS_TX_CNT_REG 0x0824
/* Status defines */
-#define VIP_BUSY 0
-#define VIP_IDLE 1
-#define VIP_RESET 2
+#define VIP_BUSY 0
+#define VIP_IDLE 1
+#define VIP_RESET 2
-#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
-#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
-#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
-#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
+#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
+#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
+#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
+#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
-#define RT_ATI_ID 0x4D541002
+#define RT_ATI_ID 0x4D541002
/* Register/Field values: */
-#define RT_COMP0 0x0
-#define RT_COMP1 0x1
-#define RT_COMP2 0x2
-#define RT_YF_COMP3 0x3
-#define RT_YR_COMP3 0x4
-#define RT_YCF_COMP4 0x5
-#define RT_YCR_COMP4 0x6
+#define RT_COMP0 0x0
+#define RT_COMP1 0x1
+#define RT_COMP2 0x2
+#define RT_YF_COMP3 0x3
+#define RT_YR_COMP3 0x4
+#define RT_YCF_COMP4 0x5
+#define RT_YCR_COMP4 0x6
/* Video standard defines */
-#define RT_NTSC 0x0
-#define RT_PAL 0x1
-#define RT_SECAM 0x2
-#define extNONE 0x0000
-#define extNTSC 0x0100
-#define extRsvd 0x0200
-#define extPAL 0x0300
-#define extPAL_M 0x0400
-#define extPAL_N 0x0500
-#define extSECAM 0x0600
-#define extPAL_NCOMB 0x0700
-#define extNTSC_J 0x0800
-#define extNTSC_443 0x0900
-#define extPAL_BGHI 0x0A00
-#define extPAL_60 0x0B00
+#define RT_NTSC 0x0
+#define RT_PAL 0x1
+#define RT_SECAM 0x2
+#define extNONE 0x0000
+#define extNTSC 0x0100
+#define extRsvd 0x0200
+#define extPAL 0x0300
+#define extPAL_M 0x0400
+#define extPAL_N 0x0500
+#define extSECAM 0x0600
+#define extPAL_NCOMB 0x0700
+#define extNTSC_J 0x0800
+#define extNTSC_443 0x0900
+#define extPAL_BGHI 0x0A00
+#define extPAL_60 0x0B00
/* these are used in MSP3430 */
-#define extPAL_DK1 0x0C00
-#define extPAL_AUTO 0x0D00
+#define extPAL_DK1 0x0C00
+#define extPAL_AUTO 0x0D00
-#define RT_FREF_2700 6
-#define RT_FREF_2950 5
+#define RT_FREF_2700 6
+#define RT_FREF_2950 5
-#define RT_COMPOSITE 0x0
-#define RT_SVIDEO 0x1
+#define RT_COMPOSITE 0x0
+#define RT_SVIDEO 0x1
-#define RT_NORM_SHARPNESS 0x03
-#define RT_HIGH_SHARPNESS 0x0F
+#define RT_NORM_SHARPNESS 0x03
+#define RT_HIGH_SHARPNESS 0x0F
-#define RT_HUE_PAL_DEF 0x00
+#define RT_HUE_PAL_DEF 0x00
-#define RT_DECINTERLACED 0x1
-#define RT_DECNONINTERLACED 0x0
+#define RT_DECINTERLACED 0x1
+#define RT_DECNONINTERLACED 0x0
-#define NTSC_LINES 525
-#define PAL_SECAM_LINES 625
+#define NTSC_LINES 525
+#define PAL_SECAM_LINES 625
-#define RT_ASYNC_ENABLE 0x0
-#define RT_ASYNC_DISABLE 0x1
-#define RT_ASYNC_RESET 0x1
+#define RT_ASYNC_ENABLE 0x0
+#define RT_ASYNC_DISABLE 0x1
+#define RT_ASYNC_RESET 0x1
-#define RT_VINRST_ACTIVE 0x0
-#define RT_VINRST_RESET 0x1
-#define RT_L54RST_RESET 0x1
+#define RT_VINRST_ACTIVE 0x0
+#define RT_VINRST_RESET 0x1
+#define RT_L54RST_RESET 0x1
-#define RT_REF_CLK 0x0
-#define RT_PLL_VIN_CLK 0x1
+#define RT_REF_CLK 0x0
+#define RT_PLL_VIN_CLK 0x1
-#define RT_VIN_ASYNC_RST 0x20
-#define RT_DVS_ASYNC_RST 0x80
+#define RT_VIN_ASYNC_RST 0x20
+#define RT_DVS_ASYNC_RST 0x80
-#define RT_ADC_ENABLE 0x0
-#define RT_ADC_DISABLE 0x1
+#define RT_ADC_ENABLE 0x0
+#define RT_ADC_DISABLE 0x1
-#define RT_DVSDIR_IN 0x0
-#define RT_DVSDIR_OUT 0x1
+#define RT_DVSDIR_IN 0x0
+#define RT_DVSDIR_OUT 0x1
-#define RT_DVSCLK_HIGH 0x0
-#define RT_DVSCLK_LOW 0x1
+#define RT_DVSCLK_HIGH 0x0
+#define RT_DVSCLK_LOW 0x1
-#define RT_DVSCLK_SEL_8FS 0x0
-#define RT_DVSCLK_SEL_27MHZ 0x1
+#define RT_DVSCLK_SEL_8FS 0x0
+#define RT_DVSCLK_SEL_27MHZ 0x1
-#define RT_DVS_CONTSTREAM 0x1
-#define RT_DVS_NONCONTSTREAM 0x0
+#define RT_DVS_CONTSTREAM 0x1
+#define RT_DVS_NONCONTSTREAM 0x0
-#define RT_DVSDAT_HIGH 0x0
-#define RT_DVSDAT_LOW 0x1
+#define RT_DVSDAT_HIGH 0x0
+#define RT_DVSDAT_LOW 0x1
-#define RT_ADC_CNTL_DEFAULT 0x03252338
+#define RT_ADC_CNTL_DEFAULT 0x03252338
/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090
-#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000
+#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090
+#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000
-#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090
-#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090
+#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090
+#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090
-#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/
-#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090
+#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/
+#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090
-#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090
-#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090
+#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090
+#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090
-#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090
-#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090
+#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090
+#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090
/* End of filter settings. */
/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081
+#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010
+#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081
-#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1
+#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010
+#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1
-#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091
-#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081
+#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091
+#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081
-#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1
+#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010
+#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1
-#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1
+#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010
+#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1
/* End of filter settings. */
/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010
-#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF
+#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010
+#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF
-#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */
-#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102
+#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */
+#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102
-#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */
-#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102
+#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */
+#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102
-#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102
-#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102
+#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102
+#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102
-#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102
-#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102
+#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102
+#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102
/* End of filter settings. */
-/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A
-#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A
+/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */
+#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A
+#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A
-#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B
-#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B
+#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B
+#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B
-#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A
-#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A
+#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A
+#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A
-#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391
-#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391
+#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391
+#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391
-#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389
-#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389
+#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389
+#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389
/* End of filter settings. */
/* LP_AGC_CLAMP_CNTL0 */
-#define RT_NTSCM_SYNCTIP_REF0 0x00000037
-#define RT_NTSCM_SYNCTIP_REF1 0x00000029
-#define RT_NTSCM_CLAMP_REF 0x0000003B
-#define RT_NTSCM_PEAKWHITE 0x000000FF
-#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2
-
-#define RT_NTSCM_WPA_THRESHOLD 0x00000406
-#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3
-
-#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B
-
-#define RT_NTSCM_LP_LOCKOUT_START 0x00000206
-#define RT_NTSCM_LP_LOCKOUT_END 0x00000021
-#define RT_NTSCM_CH_DTO_INC 0x00400000
-#define RT_NTSCM_CH_PLL_SGAIN 0x00000001
-#define RT_NTSCM_CH_PLL_FGAIN 0x00000002
-
-#define RT_NTSCM_CR_BURST_GAIN 0x0000007A
-#define RT_NTSCM_CB_BURST_GAIN 0x000000AC
-
-#define RT_NTSCM_CH_HEIGHT 0x000000CD
-#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0
-#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002
-#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000
-#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A
-#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC
-
-#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207
-#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E
-
-#define RT_NTSCJ_SYNCTIP_REF0 0x00000004
-#define RT_NTSCJ_SYNCTIP_REF1 0x00000012
-#define RT_NTSCJ_CLAMP_REF 0x0000003B
-#define RT_NTSCJ_PEAKWHITE 0x000000CB
-#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2
-#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0
-#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4
-#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C
-#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206
-#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021
-
-#define RT_NTSCJ_CR_BURST_GAIN 0x00000071
-#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F
-#define RT_NTSCJ_CH_HEIGHT 0x000000CD
-#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0
-#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002
-#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000
-#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071
-#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F
-#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207
-#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E
-
-#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
-#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
-#define RT_PAL_CLAMP_REF 0x0000003B
-#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
-#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
-#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */
-
-#define RT_PAL_WPA_TRIGGER_LO 0x00000096
-#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2
-#define RT_PAL_LP_LOCKOUT_START 0x00000263
-#define RT_PAL_LP_LOCKOUT_END 0x0000002C
-
-#define RT_PAL_CH_DTO_INC 0x00400000
-#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */
-#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */
-#define RT_PAL_CR_BURST_GAIN 0x0000007A
-#define RT_PAL_CB_BURST_GAIN 0x000000AB
-#define RT_PAL_CH_HEIGHT 0x0000009C
-#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */
-#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */
-#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */
-#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */
-#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */
-#define RT_PAL_VERT_LOCKOUT_START 0x00000269
-#define RT_PAL_VERT_LOCKOUT_END 0x00000012
-
-#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
-#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
-#define RT_SECAM_CLAMP_REF 0x0000003B
-#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
-#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
-#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/
-
-#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */
-#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2
-#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */
-#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */
-
-#define RT_SECAM_CH_DTO_INC 0x003E7A28
-#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */
-#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */
-
-#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
-#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
-#define RT_SECAM_CH_HEIGHT 0x00000066
-#define RT_SECAM_CH_KILL_LEVEL 0x00000060
-#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003
-#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000
-#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */
-#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */
-#define RT_SECAM_VERT_LOCKOUT_START 0x00000269
-#define RT_SECAM_VERT_LOCKOUT_END 0x00000012
-
-#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/
-#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A
-
-#define RT_NTSCM_FIELD_IDLOCATION 0x00000105
-#define RT_PAL_FIELD_IDLOCATION 0x00000137
-
-#define RT_NTSCM_H_ACTIVE_START 0x00000070
-#define RT_NTSCM_H_ACTIVE_END 0x00000363
-
-#define RT_PAL_H_ACTIVE_START 0x0000009A
-#define RT_PAL_H_ACTIVE_END 0x00000439
-
-#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1)
-#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1)
-
-#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */
-#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */
+#define RT_NTSCM_SYNCTIP_REF0 0x00000037
+#define RT_NTSCM_SYNCTIP_REF1 0x00000029
+#define RT_NTSCM_CLAMP_REF 0x0000003B
+#define RT_NTSCM_PEAKWHITE 0x000000FF
+#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2
+
+#define RT_NTSCM_WPA_THRESHOLD 0x00000406
+#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3
+
+#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B
+
+#define RT_NTSCM_LP_LOCKOUT_START 0x00000206
+#define RT_NTSCM_LP_LOCKOUT_END 0x00000021
+#define RT_NTSCM_CH_DTO_INC 0x00400000
+#define RT_NTSCM_CH_PLL_SGAIN 0x00000001
+#define RT_NTSCM_CH_PLL_FGAIN 0x00000002
+
+#define RT_NTSCM_CR_BURST_GAIN 0x0000007A
+#define RT_NTSCM_CB_BURST_GAIN 0x000000AC
+
+#define RT_NTSCM_CH_HEIGHT 0x000000CD
+#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0
+#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002
+#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000
+#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000
+
+#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A
+#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC
+
+#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207
+#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E
+
+#define RT_NTSCJ_SYNCTIP_REF0 0x00000004
+#define RT_NTSCJ_SYNCTIP_REF1 0x00000012
+#define RT_NTSCJ_CLAMP_REF 0x0000003B
+#define RT_NTSCJ_PEAKWHITE 0x000000CB
+#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2
+#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0
+#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4
+#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C
+#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206
+#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021
+
+#define RT_NTSCJ_CR_BURST_GAIN 0x00000071
+#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F
+#define RT_NTSCJ_CH_HEIGHT 0x000000CD
+#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0
+#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002
+#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000
+#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000
+
+#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071
+#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F
+#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207
+#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E
+
+#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
+#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
+#define RT_PAL_CLAMP_REF 0x0000003B
+#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
+#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
+#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */
+
+#define RT_PAL_WPA_TRIGGER_LO 0x00000096
+#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2
+#define RT_PAL_LP_LOCKOUT_START 0x00000263
+#define RT_PAL_LP_LOCKOUT_END 0x0000002C
+
+#define RT_PAL_CH_DTO_INC 0x00400000
+#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */
+#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */
+#define RT_PAL_CR_BURST_GAIN 0x0000007A
+#define RT_PAL_CB_BURST_GAIN 0x000000AB
+#define RT_PAL_CH_HEIGHT 0x0000009C
+#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */
+#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */
+#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */
+#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000
+
+#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */
+#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */
+#define RT_PAL_VERT_LOCKOUT_START 0x00000269
+#define RT_PAL_VERT_LOCKOUT_END 0x00000012
+
+#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
+#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
+#define RT_SECAM_CLAMP_REF 0x0000003B
+#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
+#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
+#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/
+
+#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */
+#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2
+#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */
+#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */
+
+#define RT_SECAM_CH_DTO_INC 0x003E7A28
+#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */
+#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */
+
+#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
+#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
+#define RT_SECAM_CH_HEIGHT 0x00000066
+#define RT_SECAM_CH_KILL_LEVEL 0x00000060
+#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003
+#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000
+#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000
+
+#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */
+#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */
+#define RT_SECAM_VERT_LOCKOUT_START 0x00000269
+#define RT_SECAM_VERT_LOCKOUT_END 0x00000012
+
+#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/
+#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A
+
+#define RT_NTSCM_FIELD_IDLOCATION 0x00000105
+#define RT_PAL_FIELD_IDLOCATION 0x00000137
+
+#define RT_NTSCM_H_ACTIVE_START 0x00000070
+#define RT_NTSCM_H_ACTIVE_END 0x00000363
+
+#define RT_PAL_H_ACTIVE_START 0x0000009A
+#define RT_PAL_H_ACTIVE_END 0x00000439
+
+#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1)
+#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1)
+
+#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */
+#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */
/* VBI */
-#define RT_NTSCM_H_VBI_WIND_START 0x00000049
-#define RT_NTSCM_H_VBI_WIND_END 0x00000366
+#define RT_NTSCM_H_VBI_WIND_START 0x00000049
+#define RT_NTSCM_H_VBI_WIND_END 0x00000366
-#define RT_PAL_H_VBI_WIND_START 0x00000084
-#define RT_PAL_H_VBI_WIND_END 0x0000041F
+#define RT_PAL_H_VBI_WIND_START 0x00000084
+#define RT_PAL_H_VBI_WIND_END 0x0000041F
-#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def
-#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def
+#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def
+#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def
-#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */
-#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */
+#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */
+#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */
-#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */
-#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */
-#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */
+#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */
+#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */
+#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */
-#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA
-#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353
+#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA
+#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353
-#define RT_NTSCM_VSYNC_INT_HOLD 0x17
-#define RT_PALSEM_VSYNC_INT_HOLD 0x1C
+#define RT_NTSCM_VSYNC_INT_HOLD 0x17
+#define RT_PALSEM_VSYNC_INT_HOLD 0x1C
-#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
-#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */
+#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
+#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */
-#define RT_FIELD_FLIP_EN 0x4
-#define RT_V_FIELD_FLIP_INVERTED 0x2000
+#define RT_FIELD_FLIP_EN 0x4
+#define RT_V_FIELD_FLIP_INVERTED 0x2000
-#define RT_NTSCM_H_IN_START 0x70
-#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */
-#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */
-#define RT_NTSC_H_ACTIVE_SIZE 744
-#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */
-#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */
-#define RT_NTSCM_V_IN_START (0x23)
-#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */
-#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */
-#define RT_NTSCM_V_ACTIVE_SIZE 480
-#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */
-#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */
+#define RT_NTSCM_H_IN_START 0x70
+#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */
+#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */
+#define RT_NTSC_H_ACTIVE_SIZE 744
+#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */
+#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */
+#define RT_NTSCM_V_IN_START (0x23)
+#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */
+#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */
+#define RT_NTSCM_V_ACTIVE_SIZE 480
+#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */
+#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */
-#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D
-#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D
-#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F
-#define RT_PALM_WIN_CLOSE_LIMIT 0x4D
-#define RT_PALN_WIN_CLOSE_LIMIT 0x5F
-#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */
+#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D
+#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D
+#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F
+#define RT_PALM_WIN_CLOSE_LIMIT 0x4D
+#define RT_PALN_WIN_CLOSE_LIMIT 0x5F
+#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */
-#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
+#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
-#define RT_NTSCM_HS_PLL_SGAIN 0x5
-#define RT_NTSCM_HS_PLL_FGAIN 0x7
+#define RT_NTSCM_HS_PLL_SGAIN 0x5
+#define RT_NTSCM_HS_PLL_FGAIN 0x7
-#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4
-#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0
+#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4
+#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0
-#define TV 0x1
-#define LINEIN 0x2
-#define MUTE 0x3
+#define TV 0x1
+#define LINEIN 0x2
+#define MUTE 0x3
-#define DEC_COMPOSITE 0
-#define DEC_SVIDEO 1
-#define DEC_TUNER 2
+#define DEC_COMPOSITE 0
+#define DEC_SVIDEO 1
+#define DEC_TUNER 2
-#define DEC_NTSC 0
-#define DEC_PAL 1
-#define DEC_SECAM 2
-#define DEC_NTSC_J 8
+#define DEC_NTSC 0
+#define DEC_PAL 1
+#define DEC_SECAM 2
+#define DEC_NTSC_J 8
-#define DEC_SMOOTH 0
-#define DEC_SHARP 1
+#define DEC_SMOOTH 0
+#define DEC_SHARP 1
/* RT Register Field Defaults: */
-#define fld_tmpReg1_def 0x00000000
-#define fld_tmpReg2_def 0x00000001
-#define fld_tmpReg3_def 0x00000002
+#define fld_tmpReg1_def 0x00000000
+#define fld_tmpReg2_def 0x00000001
+#define fld_tmpReg3_def 0x00000002
-#define fld_LP_CONTRAST_def 0x0000006e
-#define fld_LP_BRIGHTNESS_def 0x00003ff0
-#define fld_CP_HUE_CNTL_def 0x00000000
-#define fld_LUMA_FILTER_def 0x00000001
-#define fld_H_SCALE_RATIO_def 0x00010000
-#define fld_H_SHARPNESS_def 0x00000000
+#define fld_LP_CONTRAST_def 0x0000006e
+#define fld_LP_BRIGHTNESS_def 0x00003ff0
+#define fld_CP_HUE_CNTL_def 0x00000000
+#define fld_LUMA_FILTER_def 0x00000001
+#define fld_H_SCALE_RATIO_def 0x00010000
+#define fld_H_SHARPNESS_def 0x00000000
-#define fld_V_SCALE_RATIO_def 0x00000800
-#define fld_V_DEINTERLACE_ON_def 0x00000001
-#define fld_V_BYPSS_def 0x00000000
-#define fld_V_DITHER_ON_def 0x00000001
-#define fld_EVENF_OFFSET_def 0x00000000
-#define fld_ODDF_OFFSET_def 0x00000000
+#define fld_V_SCALE_RATIO_def 0x00000800
+#define fld_V_DEINTERLACE_ON_def 0x00000001
+#define fld_V_BYPSS_def 0x00000000
+#define fld_V_DITHER_ON_def 0x00000001
+#define fld_EVENF_OFFSET_def 0x00000000
+#define fld_ODDF_OFFSET_def 0x00000000
-#define fld_INTERLACE_DETECTED_def 0x00000000
+#define fld_INTERLACE_DETECTED_def 0x00000000
-#define fld_VS_LINE_COUNT_def 0x00000000
-#define fld_VS_DETECTED_LINES_def 0x00000000
-#define fld_VS_ITU656_VB_def 0x00000000
+#define fld_VS_LINE_COUNT_def 0x00000000
+#define fld_VS_DETECTED_LINES_def 0x00000000
+#define fld_VS_ITU656_VB_def 0x00000000
-#define fld_VBI_CC_DATA_def 0x00000000
-#define fld_VBI_CC_WT_def 0x00000000
-#define fld_VBI_CC_WT_ACK_def 0x00000000
-#define fld_VBI_CC_HOLD_def 0x00000000
-#define fld_VBI_DECODE_EN_def 0x00000000
+#define fld_VBI_CC_DATA_def 0x00000000
+#define fld_VBI_CC_WT_def 0x00000000
+#define fld_VBI_CC_WT_ACK_def 0x00000000
+#define fld_VBI_CC_HOLD_def 0x00000000
+#define fld_VBI_DECODE_EN_def 0x00000000
-#define fld_VBI_CC_DTO_P_def 0x00001802
-#define fld_VBI_20BIT_DTO_P_def 0x0000155c
+#define fld_VBI_CC_DTO_P_def 0x00001802
+#define fld_VBI_20BIT_DTO_P_def 0x0000155c
-#define fld_VBI_CC_LEVEL_def 0x0000003f
-#define fld_VBI_20BIT_LEVEL_def 0x00000059
-#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f
+#define fld_VBI_CC_LEVEL_def 0x0000003f
+#define fld_VBI_20BIT_LEVEL_def 0x00000059
+#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f
-#define fld_H_VBI_WIND_START_def 0x00000041
-#define fld_H_VBI_WIND_END_def 0x00000366
+#define fld_H_VBI_WIND_START_def 0x00000041
+#define fld_H_VBI_WIND_END_def 0x00000366
-#define fld_V_VBI_WIND_START_def 0x0D
-#define fld_V_VBI_WIND_END_def 0x24
+#define fld_V_VBI_WIND_START_def 0x0D
+#define fld_V_VBI_WIND_END_def 0x24
-#define fld_VBI_20BIT_DATA0_def 0x00000000
-#define fld_VBI_20BIT_DATA1_def 0x00000000
-#define fld_VBI_20BIT_WT_def 0x00000000
-#define fld_VBI_20BIT_WT_ACK_def 0x00000000
-#define fld_VBI_20BIT_HOLD_def 0x00000000
+#define fld_VBI_20BIT_DATA0_def 0x00000000
+#define fld_VBI_20BIT_DATA1_def 0x00000000
+#define fld_VBI_20BIT_WT_def 0x00000000
+#define fld_VBI_20BIT_WT_ACK_def 0x00000000
+#define fld_VBI_20BIT_HOLD_def 0x00000000
-#define fld_VBI_CAPTURE_ENABLE_def 0x00000000
+#define fld_VBI_CAPTURE_ENABLE_def 0x00000000
-#define fld_VBI_EDS_DATA_def 0x00000000
-#define fld_VBI_EDS_WT_def 0x00000000
-#define fld_VBI_EDS_WT_ACK_def 0x00000000
-#define fld_VBI_EDS_HOLD_def 0x00000000
+#define fld_VBI_EDS_DATA_def 0x00000000
+#define fld_VBI_EDS_WT_def 0x00000000
+#define fld_VBI_EDS_WT_ACK_def 0x00000000
+#define fld_VBI_EDS_HOLD_def 0x00000000
-#define fld_VBI_SCALING_RATIO_def 0x00010000
-#define fld_VBI_ALIGNER_ENABLE_def 0x00000000
+#define fld_VBI_SCALING_RATIO_def 0x00010000
+#define fld_VBI_ALIGNER_ENABLE_def 0x00000000
-#define fld_H_ACTIVE_START_def 0x00000070
-#define fld_H_ACTIVE_END_def 0x000002f0
+#define fld_H_ACTIVE_START_def 0x00000070
+#define fld_H_ACTIVE_END_def 0x000002f0
-#define fld_V_ACTIVE_START_def ((22-4)*2+1)
-#define fld_V_ACTIVE_END_def ((22+240-4)*2+2)
+#define fld_V_ACTIVE_START_def ((22-4)*2+1)
+#define fld_V_ACTIVE_END_def ((22+240-4)*2+2)
-#define fld_CH_HEIGHT_def 0x000000CD
-#define fld_CH_KILL_LEVEL_def 0x000000C0
-#define fld_CH_AGC_ERROR_LIM_def 0x00000002
-#define fld_CH_AGC_FILTER_EN_def 0x00000000
-#define fld_CH_AGC_LOOP_SPEED_def 0x00000000
+#define fld_CH_HEIGHT_def 0x000000CD
+#define fld_CH_KILL_LEVEL_def 0x000000C0
+#define fld_CH_AGC_ERROR_LIM_def 0x00000002
+#define fld_CH_AGC_FILTER_EN_def 0x00000000
+#define fld_CH_AGC_LOOP_SPEED_def 0x00000000
-#define fld_HUE_ADJ_def 0x00000000
+#define fld_HUE_ADJ_def 0x00000000
-#define fld_STANDARD_SEL_def 0x00000000
-#define fld_STANDARD_YC_def 0x00000000
+#define fld_STANDARD_SEL_def 0x00000000
+#define fld_STANDARD_YC_def 0x00000000
-#define fld_ADC_PDWN_def 0x00000001
-#define fld_INPUT_SELECT_def 0x00000000
+#define fld_ADC_PDWN_def 0x00000001
+#define fld_INPUT_SELECT_def 0x00000000
-#define fld_ADC_PREFLO_def 0x00000003
-#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000
-#define fld_HS_GENLOCKED_def 0x00000000
-#define fld_HS_SYNC_IN_WIN_def 0x00000000
+#define fld_ADC_PREFLO_def 0x00000003
+#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000
+#define fld_HS_GENLOCKED_def 0x00000000
+#define fld_HS_SYNC_IN_WIN_def 0x00000000
-#define fld_VIN_ASYNC_RST_def 0x00000001
-#define fld_DVS_ASYNC_RST_def 0x00000001
+#define fld_VIN_ASYNC_RST_def 0x00000001
+#define fld_DVS_ASYNC_RST_def 0x00000001
/* Vendor IDs: */
-#define fld_VIP_VENDOR_ID_def 0x00001002
-#define fld_VIP_DEVICE_ID_def 0x00004d54
-#define fld_VIP_REVISION_ID_def 0x00000001
+#define fld_VIP_VENDOR_ID_def 0x00001002
+#define fld_VIP_DEVICE_ID_def 0x00004d54
+#define fld_VIP_REVISION_ID_def 0x00000001
/* AGC Delay Register */
-#define fld_BLACK_INT_START_def 0x00000031
-#define fld_BLACK_INT_LENGTH_def 0x0000000f
+#define fld_BLACK_INT_START_def 0x00000031
+#define fld_BLACK_INT_LENGTH_def 0x0000000f
-#define fld_UV_INT_START_def 0x0000003b
-#define fld_U_INT_LENGTH_def 0x0000000f
-#define fld_V_INT_LENGTH_def 0x0000000f
-#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a
-#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac
+#define fld_UV_INT_START_def 0x0000003b
+#define fld_U_INT_LENGTH_def 0x0000000f
+#define fld_V_INT_LENGTH_def 0x0000000f
+#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a
+#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac
-#define fld_DVS_DIRECTION_def 0x00000000
-#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000
-#define fld_DVS_CLK_SELECT_def 0x00000000
-#define fld_CONTINUOUS_STREAM_def 0x00000000
-#define fld_DVSOUT_CLK_DRV_def 0x00000001
-#define fld_DVSOUT_DATA_DRV_def 0x00000001
+#define fld_DVS_DIRECTION_def 0x00000000
+#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000
+#define fld_DVS_CLK_SELECT_def 0x00000000
+#define fld_CONTINUOUS_STREAM_def 0x00000000
+#define fld_DVSOUT_CLK_DRV_def 0x00000001
+#define fld_DVSOUT_DATA_DRV_def 0x00000001
-#define fld_COMB_CNTL0_def 0x09438090
-#define fld_COMB_CNTL1_def 0x00000010
+#define fld_COMB_CNTL0_def 0x09438090
+#define fld_COMB_CNTL1_def 0x00000010
-#define fld_COMB_CNTL2_def 0x16161010
-#define fld_COMB_LENGTH_def 0x0718038A
+#define fld_COMB_CNTL2_def 0x16161010
+#define fld_COMB_LENGTH_def 0x0718038A
-#define fld_SYNCTIP_REF0_def 0x00000037
-#define fld_SYNCTIP_REF1_def 0x00000029
-#define fld_CLAMP_REF_def 0x0000003B
-#define fld_AGC_PEAKWHITE_def 0x000000FF
-#define fld_VBI_PEAKWHITE_def 0x000000D2
+#define fld_SYNCTIP_REF0_def 0x00000037
+#define fld_SYNCTIP_REF1_def 0x00000029
+#define fld_CLAMP_REF_def 0x0000003B
+#define fld_AGC_PEAKWHITE_def 0x000000FF
+#define fld_VBI_PEAKWHITE_def 0x000000D2
-#define fld_WPA_THRESHOLD_def 0x000003B0
+#define fld_WPA_THRESHOLD_def 0x000003B0
-#define fld_WPA_TRIGGER_LO_def 0x000000B4
-#define fld_WPA_TRIGGER_HIGH_def 0x0000021C
+#define fld_WPA_TRIGGER_LO_def 0x000000B4
+#define fld_WPA_TRIGGER_HIGH_def 0x0000021C
-#define fld_LOCKOUT_START_def 0x00000206
-#define fld_LOCKOUT_END_def 0x00000021
+#define fld_LOCKOUT_START_def 0x00000206
+#define fld_LOCKOUT_END_def 0x00000021
-#define fld_CH_DTO_INC_def 0x00400000
-#define fld_PLL_SGAIN_def 0x00000001
-#define fld_PLL_FGAIN_def 0x00000002
+#define fld_CH_DTO_INC_def 0x00400000
+#define fld_PLL_SGAIN_def 0x00000001
+#define fld_PLL_FGAIN_def 0x00000002
-#define fld_CR_BURST_GAIN_def 0x0000007a
-#define fld_CB_BURST_GAIN_def 0x000000ac
+#define fld_CR_BURST_GAIN_def 0x0000007a
+#define fld_CB_BURST_GAIN_def 0x000000ac
-#define fld_VERT_LOCKOUT_START_def 0x00000207
-#define fld_VERT_LOCKOUT_END_def 0x0000000E
+#define fld_VERT_LOCKOUT_START_def 0x00000207
+#define fld_VERT_LOCKOUT_END_def 0x0000000E
-#define fld_H_IN_WIND_START_def 0x00000070
-#define fld_V_IN_WIND_START_def 0x00000027
+#define fld_H_IN_WIND_START_def 0x00000070
+#define fld_V_IN_WIND_START_def 0x00000027
-#define fld_H_OUT_WIND_WIDTH_def 0x000002f4
+#define fld_H_OUT_WIND_WIDTH_def 0x000002f4
-#define fld_V_OUT_WIND_WIDTH_def 0x000000f0
+#define fld_V_OUT_WIND_WIDTH_def 0x000000f0
-#define fld_HS_LINE_TOTAL_def 0x0000038E
+#define fld_HS_LINE_TOTAL_def 0x0000038E
-#define fld_MIN_PULSE_WIDTH_def 0x0000002F
-#define fld_MAX_PULSE_WIDTH_def 0x00000046
+#define fld_MIN_PULSE_WIDTH_def 0x0000002F
+#define fld_MAX_PULSE_WIDTH_def 0x00000046
-#define fld_WIN_CLOSE_LIMIT_def 0x0000004D
-#define fld_WIN_OPEN_LIMIT_def 0x000001B7
+#define fld_WIN_CLOSE_LIMIT_def 0x0000004D
+#define fld_WIN_OPEN_LIMIT_def 0x000001B7
-#define fld_VSYNC_INT_TRIGGER_def 0x000002AA
+#define fld_VSYNC_INT_TRIGGER_def 0x000002AA
-#define fld_VSYNC_INT_HOLD_def 0x0000001D
+#define fld_VSYNC_INT_HOLD_def 0x0000001D
-#define fld_VIN_M0_def 0x00000039
-#define fld_VIN_N0_def 0x0000014c
-#define fld_MNFLIP_EN_def 0x00000000
-#define fld_VIN_P_def 0x00000006
-#define fld_REG_CLK_SEL_def 0x00000000
+#define fld_VIN_M0_def 0x00000039
+#define fld_VIN_N0_def 0x0000014c
+#define fld_MNFLIP_EN_def 0x00000000
+#define fld_VIN_P_def 0x00000006
+#define fld_REG_CLK_SEL_def 0x00000000
-#define fld_VIN_M1_def 0x00000000
-#define fld_VIN_N1_def 0x00000000
-#define fld_VIN_DRIVER_SEL_def 0x00000000
-#define fld_VIN_MNFLIP_REQ_def 0x00000000
-#define fld_VIN_MNFLIP_DONE_def 0x00000000
-#define fld_TV_LOCK_TO_VIN_def 0x00000000
-#define fld_TV_P_FOR_WINCLK_def 0x00000004
+#define fld_VIN_M1_def 0x00000000
+#define fld_VIN_N1_def 0x00000000
+#define fld_VIN_DRIVER_SEL_def 0x00000000
+#define fld_VIN_MNFLIP_REQ_def 0x00000000
+#define fld_VIN_MNFLIP_DONE_def 0x00000000
+#define fld_TV_LOCK_TO_VIN_def 0x00000000
+#define fld_TV_P_FOR_WINCLK_def 0x00000004
-#define fld_VINRST_def 0x00000001
-#define fld_VIN_CLK_SEL_def 0x00000000
+#define fld_VINRST_def 0x00000001
+#define fld_VIN_CLK_SEL_def 0x00000000
-#define fld_VS_FIELD_BLANK_START_def 0x00000206
+#define fld_VS_FIELD_BLANK_START_def 0x00000206
-#define fld_VS_FIELD_BLANK_END_def 0x0000000A
+#define fld_VS_FIELD_BLANK_END_def 0x0000000A
-/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */
-#define fld_VS_FIELD_IDLOCATION_def 0x00000001
-#define fld_VS_FRAME_TOTAL_def 0x00000217
+/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */
+#define fld_VS_FIELD_IDLOCATION_def 0x00000001
+#define fld_VS_FRAME_TOTAL_def 0x00000217
-#define fld_SYNC_TIP_START_def 0x00000372
-#define fld_SYNC_TIP_LENGTH_def 0x0000000F
+#define fld_SYNC_TIP_START_def 0x00000372
+#define fld_SYNC_TIP_LENGTH_def 0x0000000F
-#define fld_GAIN_FORCE_DATA_def 0x00000000
-#define fld_GAIN_FORCE_EN_def 0x00000000
-#define fld_I_CLAMP_SEL_def 0x00000003
-#define fld_I_AGC_SEL_def 0x00000001
-#define fld_EXT_CLAMP_CAP_def 0x00000001
-#define fld_EXT_AGC_CAP_def 0x00000001
-#define fld_DECI_DITHER_EN_def 0x00000001
-#define fld_ADC_PREFHI_def 0x00000000
-#define fld_ADC_CH_GAIN_SEL_def 0x00000001
+#define fld_GAIN_FORCE_DATA_def 0x00000000
+#define fld_GAIN_FORCE_EN_def 0x00000000
+#define fld_I_CLAMP_SEL_def 0x00000003
+#define fld_I_AGC_SEL_def 0x00000001
+#define fld_EXT_CLAMP_CAP_def 0x00000001
+#define fld_EXT_AGC_CAP_def 0x00000001
+#define fld_DECI_DITHER_EN_def 0x00000001
+#define fld_ADC_PREFHI_def 0x00000000
+#define fld_ADC_CH_GAIN_SEL_def 0x00000001
-#define fld_HS_PLL_SGAIN_def 0x00000003
+#define fld_HS_PLL_SGAIN_def 0x00000003
-#define fld_NREn_def 0x00000000
-#define fld_NRGainCntl_def 0x00000000
-#define fld_NRBWTresh_def 0x00000000
-#define fld_NRGCTresh_def 0x00000000
-#define fld_NRCoefDespeclMode_def 0x00000000
+#define fld_NREn_def 0x00000000
+#define fld_NRGainCntl_def 0x00000000
+#define fld_NRBWTresh_def 0x00000000
+#define fld_NRGCTresh_def 0x00000000
+#define fld_NRCoefDespeclMode_def 0x00000000
-#define fld_GPIO_5_OE_def 0x00000000
-#define fld_GPIO_6_OE_def 0x00000000
+#define fld_GPIO_5_OE_def 0x00000000
+#define fld_GPIO_6_OE_def 0x00000000
-#define fld_GPIO_5_OUT_def 0x00000000
-#define fld_GPIO_6_OUT_def 0x00000000
+#define fld_GPIO_5_OUT_def 0x00000000
+#define fld_GPIO_6_OUT_def 0x00000000
-/* End of field default values. */
+/* End of field default values. */
#endif /* MPLAYER_RADEON_H */