From 7573c29480850d715e2f06cae70f252573098123 Mon Sep 17 00:00:00 2001 From: diego Date: Mon, 12 Apr 2010 10:56:17 +0000 Subject: the great MPlayer tab removal: part I git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@31032 b3059339-0415-0410-9bf9-f77b7e298cf2 --- drivers/3dfx.h | 288 ++-- drivers/README.Ati | 8 +- drivers/README.Matrox | 34 +- drivers/generic_math.h | 2 +- drivers/hacking.ati | 240 ++-- drivers/mga_vid.c | 2324 +++++++++++++++--------------- drivers/mga_vid_test.c | 326 ++--- drivers/radeon.h | 3660 ++++++++++++++++++++++++------------------------ 8 files changed, 3436 insertions(+), 3446 deletions(-) (limited to 'drivers') diff --git a/drivers/3dfx.h b/drivers/3dfx.h index 0cabc492ce..159327d482 100644 --- a/drivers/3dfx.h +++ b/drivers/3dfx.h @@ -29,10 +29,10 @@ #define VOODOO_YUV_PLANE_OFFSET ((unsigned long int)0x0C00000) #define VOODOO_BLT_FORMAT_YUYV (8<<16) -#define VOODOO_BLT_FORMAT_UYVY (9<<16) +#define VOODOO_BLT_FORMAT_UYVY (9<<16) #define VOODOO_BLT_FORMAT_16 (3<<16) -#define VOODOO_BLT_FORMAT_24 (4<<16) -#define VOODOO_BLT_FORMAT_32 (5<<16) +#define VOODOO_BLT_FORMAT_24 (4<<16) +#define VOODOO_BLT_FORMAT_32 (5<<16) #define VOODOO_YUV_STRIDE (1024>>2) @@ -164,95 +164,95 @@ typedef struct voodoo_yuv_fb_t voodoo_yuv_fb; */ #ifndef PCI_DEVICE_ID_3DFX_VOODOO5 -#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 +#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 #endif /* membase0 register offsets */ -#define STATUS 0x00 -#define PCIINIT0 0x04 -#define SIPMONITOR 0x08 -#define LFBMEMORYCONFIG 0x0c -#define MISCINIT0 0x10 -#define MISCINIT1 0x14 -#define DRAMINIT0 0x18 -#define DRAMINIT1 0x1c -#define AGPINIT 0x20 -#define TMUGBEINIT 0x24 -#define VGAINIT0 0x28 -#define VGAINIT1 0x2c -#define DRAMCOMMAND 0x30 -#define DRAMDATA 0x34 -/* reserved 0x38 */ -/* reserved 0x3c */ -#define PLLCTRL0 0x40 -#define PLLCTRL1 0x44 -#define PLLCTRL2 0x48 -#define DACMODE 0x4c -#define DACADDR 0x50 -#define DACDATA 0x54 -#define RGBMAXDELTA 0x58 -#define VIDPROCCFG 0x5c -#define HWCURPATADDR 0x60 -#define HWCURLOC 0x64 -#define HWCURC0 0x68 -#define HWCURC1 0x6c -#define VIDINFORMAT 0x70 -#define VIDINSTATUS 0x74 -#define VIDSERPARPORT 0x78 -#define VIDINXDELTA 0x7c -#define VIDININITERR 0x80 -#define VIDINYDELTA 0x84 -#define VIDPIXBUFTHOLD 0x88 -#define VIDCHRMIN 0x8c -#define VIDCHRMAX 0x90 -#define VIDCURLIN 0x94 -#define VIDSCREENSIZE 0x98 -#define VIDOVRSTARTCRD 0x9c -#define VIDOVRENDCRD 0xa0 -#define VIDOVRDUDX 0xa4 -#define VIDOVRDUDXOFF 0xa8 -#define VIDOVRDVDY 0xac +#define STATUS 0x00 +#define PCIINIT0 0x04 +#define SIPMONITOR 0x08 +#define LFBMEMORYCONFIG 0x0c +#define MISCINIT0 0x10 +#define MISCINIT1 0x14 +#define DRAMINIT0 0x18 +#define DRAMINIT1 0x1c +#define AGPINIT 0x20 +#define TMUGBEINIT 0x24 +#define VGAINIT0 0x28 +#define VGAINIT1 0x2c +#define DRAMCOMMAND 0x30 +#define DRAMDATA 0x34 +/* reserved 0x38 */ +/* reserved 0x3c */ +#define PLLCTRL0 0x40 +#define PLLCTRL1 0x44 +#define PLLCTRL2 0x48 +#define DACMODE 0x4c +#define DACADDR 0x50 +#define DACDATA 0x54 +#define RGBMAXDELTA 0x58 +#define VIDPROCCFG 0x5c +#define HWCURPATADDR 0x60 +#define HWCURLOC 0x64 +#define HWCURC0 0x68 +#define HWCURC1 0x6c +#define VIDINFORMAT 0x70 +#define VIDINSTATUS 0x74 +#define VIDSERPARPORT 0x78 +#define VIDINXDELTA 0x7c +#define VIDININITERR 0x80 +#define VIDINYDELTA 0x84 +#define VIDPIXBUFTHOLD 0x88 +#define VIDCHRMIN 0x8c +#define VIDCHRMAX 0x90 +#define VIDCURLIN 0x94 +#define VIDSCREENSIZE 0x98 +#define VIDOVRSTARTCRD 0x9c +#define VIDOVRENDCRD 0xa0 +#define VIDOVRDUDX 0xa4 +#define VIDOVRDUDXOFF 0xa8 +#define VIDOVRDVDY 0xac /* ... */ -#define VIDOVRDVDYOFF 0xe0 -#define VIDDESKSTART 0xe4 -#define VIDDESKSTRIDE 0xe8 -#define VIDINADDR0 0xec -#define VIDINADDR1 0xf0 -#define VIDINADDR2 0xf4 -#define VIDINSTRIDE 0xf8 -#define VIDCUROVRSTART 0xfc - -#define INTCTRL (0x00100000 + 0x04) -#define CLIP0MIN (0x00100000 + 0x08) -#define CLIP0MAX (0x00100000 + 0x0c) -#define DSTBASE (0x00100000 + 0x10) -#define DSTFORMAT (0x00100000 + 0x14) -#define SRCCOLORKEYMIN (0x00100000 + 0x18) -#define SRCCOLORKEYMAX (0x00100000 + 0x1c) -#define DSTCOLORKEYMIN (0x00100000 + 0x20) -#define DSTCOLORKEYMAX (0x00100000 + 0x24) -#define ROP123 (0x00100000 + 0x30) -#define SRCBASE (0x00100000 + 0x34) -#define COMMANDEXTRA_2D (0x00100000 + 0x38) -#define CLIP1MIN (0x00100000 + 0x4c) -#define CLIP1MAX (0x00100000 + 0x50) -#define SRCFORMAT (0x00100000 + 0x54) -#define SRCSIZE (0x00100000 + 0x58) -#define SRCXY (0x00100000 + 0x5c) -#define COLORBACK (0x00100000 + 0x60) -#define COLORFORE (0x00100000 + 0x64) -#define DSTSIZE (0x00100000 + 0x68) -#define DSTXY (0x00100000 + 0x6c) -#define COMMAND_2D (0x00100000 + 0x70) -#define LAUNCH_2D (0x00100000 + 0x80) - -#define COMMAND_3D (0x00200000 + 0x120) - -#define SWAPBUFCMD (0x00200000 + 0x128) -#define SWAPPENDING (0x00200000 + 0x24C) -#define LEFTOVBUF (0x00200000 + 0x250) -#define RIGHTOVBUF (0x00200000 + 0x254) -#define FBISWAPBUFHIST (0x00200000 + 0x258) +#define VIDOVRDVDYOFF 0xe0 +#define VIDDESKSTART 0xe4 +#define VIDDESKSTRIDE 0xe8 +#define VIDINADDR0 0xec +#define VIDINADDR1 0xf0 +#define VIDINADDR2 0xf4 +#define VIDINSTRIDE 0xf8 +#define VIDCUROVRSTART 0xfc + +#define INTCTRL (0x00100000 + 0x04) +#define CLIP0MIN (0x00100000 + 0x08) +#define CLIP0MAX (0x00100000 + 0x0c) +#define DSTBASE (0x00100000 + 0x10) +#define DSTFORMAT (0x00100000 + 0x14) +#define SRCCOLORKEYMIN (0x00100000 + 0x18) +#define SRCCOLORKEYMAX (0x00100000 + 0x1c) +#define DSTCOLORKEYMIN (0x00100000 + 0x20) +#define DSTCOLORKEYMAX (0x00100000 + 0x24) +#define ROP123 (0x00100000 + 0x30) +#define SRCBASE (0x00100000 + 0x34) +#define COMMANDEXTRA_2D (0x00100000 + 0x38) +#define CLIP1MIN (0x00100000 + 0x4c) +#define CLIP1MAX (0x00100000 + 0x50) +#define SRCFORMAT (0x00100000 + 0x54) +#define SRCSIZE (0x00100000 + 0x58) +#define SRCXY (0x00100000 + 0x5c) +#define COLORBACK (0x00100000 + 0x60) +#define COLORFORE (0x00100000 + 0x64) +#define DSTSIZE (0x00100000 + 0x68) +#define DSTXY (0x00100000 + 0x6c) +#define COMMAND_2D (0x00100000 + 0x70) +#define LAUNCH_2D (0x00100000 + 0x80) + +#define COMMAND_3D (0x00200000 + 0x120) + +#define SWAPBUFCMD (0x00200000 + 0x128) +#define SWAPPENDING (0x00200000 + 0x24C) +#define LEFTOVBUF (0x00200000 + 0x250) +#define RIGHTOVBUF (0x00200000 + 0x254) +#define FBISWAPBUFHIST (0x00200000 + 0x258) /* register bitfields (not all, only as needed) */ @@ -268,44 +268,44 @@ typedef struct voodoo_yuv_fb_t voodoo_yuv_fb; #define AUTOINC_DSTY BIT(11) -#define COMMAND_2D_S2S_BITBLT 0x01 // screen to screen -#define COMMAND_2D_S2S_STRECH_BLT 0x02 // BLT + Strech +#define COMMAND_2D_S2S_BITBLT 0x01 // screen to screen +#define COMMAND_2D_S2S_STRECH_BLT 0x02 // BLT + Strech #define COMMAND_2D_H2S_BITBLT 0x03 // host to screen -#define COMMAND_2D_FILLRECT 0x05 - -#define COMMAND_2D_DO_IMMED BIT(8) // Do it immediatly - - - -#define COMMAND_3D_NOP 0x00 -#define STATUS_RETRACE BIT(6) -#define STATUS_BUSY BIT(9) -#define MISCINIT1_CLUT_INV BIT(0) -#define MISCINIT1_2DBLOCK_DIS BIT(15) -#define DRAMINIT0_SGRAM_NUM BIT(26) -#define DRAMINIT0_SGRAM_TYPE BIT(27) -#define DRAMINIT1_MEM_SDRAM BIT(30) -#define VGAINIT0_VGA_DISABLE BIT(0) -#define VGAINIT0_EXT_TIMING BIT(1) -#define VGAINIT0_8BIT_DAC BIT(2) -#define VGAINIT0_EXT_ENABLE BIT(6) -#define VGAINIT0_WAKEUP_3C3 BIT(8) -#define VGAINIT0_LEGACY_DISABLE BIT(9) -#define VGAINIT0_ALT_READBACK BIT(10) -#define VGAINIT0_FAST_BLINK BIT(11) -#define VGAINIT0_EXTSHIFTOUT BIT(12) -#define VGAINIT0_DECODE_3C6 BIT(13) -#define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22) -#define VGAINIT1_MASK 0x1fffff -#define VIDCFG_VIDPROC_ENABLE BIT(0) -#define VIDCFG_CURS_X11 BIT(1) -#define VIDCFG_HALF_MODE BIT(4) -#define VIDCFG_DESK_ENABLE BIT(7) -#define VIDCFG_CLUT_BYPASS BIT(10) -#define VIDCFG_2X BIT(26) -#define VIDCFG_HWCURSOR_ENABLE BIT(27) -#define VIDCFG_PIXFMT_SHIFT 18 -#define DACMODE_2X BIT(0) +#define COMMAND_2D_FILLRECT 0x05 + +#define COMMAND_2D_DO_IMMED BIT(8) // Do it immediatly + + + +#define COMMAND_3D_NOP 0x00 +#define STATUS_RETRACE BIT(6) +#define STATUS_BUSY BIT(9) +#define MISCINIT1_CLUT_INV BIT(0) +#define MISCINIT1_2DBLOCK_DIS BIT(15) +#define DRAMINIT0_SGRAM_NUM BIT(26) +#define DRAMINIT0_SGRAM_TYPE BIT(27) +#define DRAMINIT1_MEM_SDRAM BIT(30) +#define VGAINIT0_VGA_DISABLE BIT(0) +#define VGAINIT0_EXT_TIMING BIT(1) +#define VGAINIT0_8BIT_DAC BIT(2) +#define VGAINIT0_EXT_ENABLE BIT(6) +#define VGAINIT0_WAKEUP_3C3 BIT(8) +#define VGAINIT0_LEGACY_DISABLE BIT(9) +#define VGAINIT0_ALT_READBACK BIT(10) +#define VGAINIT0_FAST_BLINK BIT(11) +#define VGAINIT0_EXTSHIFTOUT BIT(12) +#define VGAINIT0_DECODE_3C6 BIT(13) +#define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22) +#define VGAINIT1_MASK 0x1fffff +#define VIDCFG_VIDPROC_ENABLE BIT(0) +#define VIDCFG_CURS_X11 BIT(1) +#define VIDCFG_HALF_MODE BIT(4) +#define VIDCFG_DESK_ENABLE BIT(7) +#define VIDCFG_CLUT_BYPASS BIT(10) +#define VIDCFG_2X BIT(26) +#define VIDCFG_HWCURSOR_ENABLE BIT(27) +#define VIDCFG_PIXFMT_SHIFT 18 +#define DACMODE_2X BIT(0) /* AGP registers */ #define AGPREQSIZE (0x0080000 + 0x00) @@ -332,35 +332,35 @@ typedef struct voodoo_yuv_fb_t voodoo_yuv_fb; #define YUVSTRIDE (0x0080000 + 0x104) /* VGA rubbish, need to change this for multihead support */ -#define MISC_W 0x3c2 -#define MISC_R 0x3cc -#define SEQ_I 0x3c4 -#define SEQ_D 0x3c5 -#define CRT_I 0x3d4 -#define CRT_D 0x3d5 -#define ATT_IW 0x3c0 +#define MISC_W 0x3c2 +#define MISC_R 0x3cc +#define SEQ_I 0x3c4 +#define SEQ_D 0x3c5 +#define CRT_I 0x3d4 +#define CRT_D 0x3d5 +#define ATT_IW 0x3c0 #define RAMDAC_R 0x3c7 #define RAMDAC_W 0x3c8 #define RAMDAC_D 0x3c9 -#define IS1_R 0x3da -#define GRA_I 0x3ce -#define GRA_D 0x3cf +#define IS1_R 0x3da +#define GRA_I 0x3ce +#define GRA_D 0x3cf #ifndef FB_ACCEL_3DFX_BANSHEE #define FB_ACCEL_3DFX_BANSHEE 31 #endif -#define TDFXF_HSYNC_ACT_HIGH 0x01 -#define TDFXF_HSYNC_ACT_LOW 0x02 -#define TDFXF_VSYNC_ACT_HIGH 0x04 -#define TDFXF_VSYNC_ACT_LOW 0x08 -#define TDFXF_LINE_DOUBLE 0x10 -#define TDFXF_VIDEO_ENABLE 0x20 +#define TDFXF_HSYNC_ACT_HIGH 0x01 +#define TDFXF_HSYNC_ACT_LOW 0x02 +#define TDFXF_VSYNC_ACT_HIGH 0x04 +#define TDFXF_VSYNC_ACT_LOW 0x08 +#define TDFXF_LINE_DOUBLE 0x10 +#define TDFXF_VIDEO_ENABLE 0x20 -#define TDFXF_HSYNC_MASK 0x03 -#define TDFXF_VSYNC_MASK 0x0c +#define TDFXF_HSYNC_MASK 0x03 +#define TDFXF_VSYNC_MASK 0x0c -#define XYREG(x,y) (((((unsigned long)y) & 0x1FFF) << 16) | (((unsigned long)x) & 0x1FFF)) +#define XYREG(x,y) (((((unsigned long)y) & 0x1FFF) << 16) | (((unsigned long)x) & 0x1FFF)) //#define TDFXFB_DEBUG #ifdef TDFXFB_DEBUG diff --git a/drivers/README.Ati b/drivers/README.Ati index 640107f56c..077b6ffff2 100644 --- a/drivers/README.Ati +++ b/drivers/README.Ati @@ -1,5 +1,5 @@ - framebuffer driver for ATI Radeon chipset video boards - ====================================================== + framebuffer driver for ATI Radeon chipset video boards + ====================================================== These files are replacement for linux-2.4.x-ac.y drivers. To use this driver you should have at least linux-2.4.5-ac.1 @@ -21,7 +21,7 @@ and at least '8bpp packed pixel support' compiled and installed as module. Radeon video overlay - ==================== + ==================== It was designed for MPlayer and currently can be used only by MPlayer. It's RGB-YUV BES for Radeon cards (althrough there is experimental @@ -93,7 +93,7 @@ List of driver parameters: ~~~~~~~~~~~~~~~~~~~~~~~~~~ mtrr=1/0 Configures MTRR (if available), default = 1. swap_fourcc=1/0 Performs byte swapping of passed fourcc. - (It's required for compatibility with -vo mga.) + (It's required for compatibility with -vo mga.) To know more about driver parameters execute: modinfo radeon_vid diff --git a/drivers/README.Matrox b/drivers/README.Matrox index ae641ab452..48a37ed057 100644 --- a/drivers/README.Matrox +++ b/drivers/README.Matrox @@ -7,12 +7,12 @@ http://attila.kinali.ch/mga/ mga_vid - MGA G200/G400 YUV Overlay kernel module - Author: - Aaron Holtzman , Oct 1999 + Author: + Aaron Holtzman , Oct 1999 - Contributions by: - Fredrik Vraalsen - Alan Cox + Contributions by: + Fredrik Vraalsen + Alan Cox WARNING ----- WARNING @@ -24,23 +24,23 @@ MAX to spout 6 inch flames. You have been warned. What does this code do? - mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550 - video scaler/overlay unit to perform YUV->RGB colorspace conversion - and arbitrary video scaling. + mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550 + video scaler/overlay unit to perform YUV->RGB colorspace conversion + and arbitrary video scaling. - mga_vid is also a monster hack. + mga_vid is also a monster hack. How does mga_vid work? - This kernel module sets up the BES (backend scaler) with appropriate - values based on parameters supplied via ioctl. It also maps a chunk of - video memory into userspace via mmap. This memory is stolen from X - (which may decide to write to it later). The application can then write - image data directly to the framebuffer (if it knows the right padding, - etc). + This kernel module sets up the BES (backend scaler) with appropriate + values based on parameters supplied via ioctl. It also maps a chunk of + video memory into userspace via mmap. This memory is stolen from X + (which may decide to write to it later). The application can then write + image data directly to the framebuffer (if it knows the right padding, + etc). How do I know if mga_vid works on my system? - There is a test application called mga_vid_test. This test code should - draw some nice 256x256 images for you if all is working well. + There is a test application called mga_vid_test. This test code should + draw some nice 256x256 images for you if all is working well. diff --git a/drivers/generic_math.h b/drivers/generic_math.h index f606cce3d8..00a0e976f8 100644 --- a/drivers/generic_math.h +++ b/drivers/generic_math.h @@ -233,7 +233,7 @@ static gen_sincos_t g_sincos[201] = { { 3.141600e+00, -7.346410e-06, -1.000000e-00 } }; -# define M_PI 3.14159265358979323846 /* pi */ +#define M_PI 3.14159265358979323846 /* pi */ static double inline gen_sin(double x) { diff --git a/drivers/hacking.ati b/drivers/hacking.ati index 518c3a8f90..20c9bfa8ea 100644 --- a/drivers/hacking.ati +++ b/drivers/hacking.ati @@ -1,6 +1,6 @@ ATI chips hacking ================= - Dedicated to ATI's hackers. + Dedicated to ATI's hackers. Preface ~~~~~~~ @@ -11,20 +11,20 @@ This document doesn't include information about ATI AIW (All In Wonder) chips. What are units on modern ATI chips: DAC - (Digital to Analog Convertor) controls CRTC, LCD, DFP monitor's output - Consists from: - PLL - (Programable line length) registers - CRTC - CRT controller - LCD/DFP scaler - surface control + Consists from: + PLL - (Programable line length) registers + CRTC - CRT controller + LCD/DFP scaler + surface control DAC2 - controls CRTC, LCD, DFP monitor's output on second head TVDAC - controls Composite Video and Super Video output ports - Consists from: - TV_PLL - TV scaler & sync unit - TV format convertor (PAL/NTSC) + Consists from: + TV_PLL + TV scaler & sync unit + TV format convertor (PAL/NTSC) TVCAP - controls Video-In port MPP - Miscellaneous peripheral port. (includes macrovision's filter - copy - protection mechanism) + protection mechanism) OV - Video overlay (YUV BES) (include subpictures, gamma correction and adaptive deinterlacing) CAP0 - Video capturing @@ -61,100 +61,100 @@ of this question: 3. Mach32 4. Mach64. - It's first chip which has support from side of open - source drivers. Set of mach64 chips is: - mach64GX (ATI888GX00) - mach64CX (ATI888CX00) - mach64CT (ATI264CT) - mach64ET (ATI264ET) - mach64VTA3 (ATI264VT) - mach64VTA4 (ATI264VT) - mach64VTB (ATI264VTB) - mach64VT4 (ATI264VT4) + It's first chip which has support from side of open + source drivers. Set of mach64 chips is: + mach64GX (ATI888GX00) + mach64CX (ATI888CX00) + mach64CT (ATI264CT) + mach64ET (ATI264ET) + mach64VTA3 (ATI264VT) + mach64VTA4 (ATI264VT) + mach64VTB (ATI264VTB) + mach64VT4 (ATI264VT4) 5. 3D rage chips. - It seems that these chips have fully compatible by GPU with Mach64 - which is extended by 3D possibilities. Set of 3D rage chips is: - 3D RAGE (GT) - 3D RAGE II+ (GTB) - 3D RAGE IIC (PCI) - 3D RAGE IIC (AGP) - 3D RAGE LT - 3D RAGE LT-G - 3D RAGE PRO (BGA, AGP) - 3D RAGE PRO (BGA, AGP, 1x only) - 3D RAGE PRO (BGA, PCI) - 3D RAGE PRO (PQFP, PCI) - 3D RAGE PRO (PQFP, PCI, limited 3D) - 3D RAGE (XL) - 3D RAGE LT PRO (AGP) - 3D RAGE LT PRO (PCI) - 3D RAGE Mobility (PCI) - 3D RAGE Mobility (AGP) + It seems that these chips have fully compatible by GPU with Mach64 + which is extended by 3D possibilities. Set of 3D rage chips is: + 3D RAGE (GT) + 3D RAGE II+ (GTB) + 3D RAGE IIC (PCI) + 3D RAGE IIC (AGP) + 3D RAGE LT + 3D RAGE LT-G + 3D RAGE PRO (BGA, AGP) + 3D RAGE PRO (BGA, AGP, 1x only) + 3D RAGE PRO (BGA, PCI) + 3D RAGE PRO (PQFP, PCI) + 3D RAGE PRO (PQFP, PCI, limited 3D) + 3D RAGE (XL) + 3D RAGE LT PRO (AGP) + 3D RAGE LT PRO (PCI) + 3D RAGE Mobility (PCI) + 3D RAGE Mobility (AGP) 6. Rage128 chips. - These chips have perfectly new GPU which supports memory mapped IO - space for accelerating port access (It's main cause of incompatibility - with mach64). Set of Rage128 chips is: - Rage128 GL RE - Rage128 GL RF - Rage128 GL RG - Rage128 GL RH - Rage128 GL RI - Rage128 VR RK - Rage128 VR RL - Rage128 VR RM - Rage128 VR RN - Rage128 VR RO - Rage128 Mobility M3 LE - Rage128 Mobility M3 LF + These chips have perfectly new GPU which supports memory mapped IO + space for accelerating port access (It's main cause of incompatibility + with mach64). Set of Rage128 chips is: + Rage128 GL RE + Rage128 GL RF + Rage128 GL RG + Rage128 GL RH + Rage128 GL RI + Rage128 VR RK + Rage128 VR RL + Rage128 VR RM + Rage128 VR RN + Rage128 VR RO + Rage128 Mobility M3 LE + Rage128 Mobility M3 LF 7. Rage128Pro chips. - These chips are successors of Rage128 ones. - Rage128Pro GL PA - Rage128Pro GL PB - Rage128Pro GL PC - Rage128Pro GL PD - Rage128Pro GL PE - Rage128Pro GL PF - Rage128Pro VR PG - Rage128Pro VR PH - Rage128Pro VR PI - Rage128Pro VR PJ - Rage128Pro VR PK - Rage128Pro VR PL - Rage128Pro VR PM - Rage128Pro VR PN - Rage128Pro VR PO - Rage128Pro VR PP - Rage128Pro VR PQ - Rage128Pro VR PR - Rage128Pro VR TR - Rage128Pro VR PS - Rage128Pro VR PT - Rage128Pro VR PU - Rage128Pro VR PV - Rage128Pro VR PW - Rage128Pro VR PX - Rage128Pro Ultra U1 - Rage128Pro Ultra U2 - Rage128Pro Ultra U3 + These chips are successors of Rage128 ones. + Rage128Pro GL PA + Rage128Pro GL PB + Rage128Pro GL PC + Rage128Pro GL PD + Rage128Pro GL PE + Rage128Pro GL PF + Rage128Pro VR PG + Rage128Pro VR PH + Rage128Pro VR PI + Rage128Pro VR PJ + Rage128Pro VR PK + Rage128Pro VR PL + Rage128Pro VR PM + Rage128Pro VR PN + Rage128Pro VR PO + Rage128Pro VR PP + Rage128Pro VR PQ + Rage128Pro VR PR + Rage128Pro VR TR + Rage128Pro VR PS + Rage128Pro VR PT + Rage128Pro VR PU + Rage128Pro VR PV + Rage128Pro VR PW + Rage128Pro VR PX + Rage128Pro Ultra U1 + Rage128Pro Ultra U2 + Rage128Pro Ultra U3 8. Radeon chips. - Indeed they could be named Rage256 Pro. (With minor changes is fully - compatible with Rage128 chips). - Radeon QD - Radeon QE - Radeon QF - Radeon QG - Radeon VE QY - Radeon VE QZ - Radeon M6 LY - Radeon M6 LZ - Radeon M7 LW + Indeed they could be named Rage256 Pro. (With minor changes is fully + compatible with Rage128 chips). + Radeon QD + Radeon QE + Radeon QF + Radeon QG + Radeon VE QY + Radeon VE QZ + Radeon M6 LY + Radeon M6 LZ + Radeon M7 LW 9. Radeon2 chips. - Indeed they could be named Rage512 Pro. - Radeon2 8500 QL - Radeon2 7500 QW + Indeed they could be named Rage512 Pro. + Radeon2 8500 QL + Radeon2 7500 QW 10. Radeon3 and newest are cooming soon, but I hope that they will be fully compatible with Radeon1 chips. @@ -185,31 +185,31 @@ Please compare: Sample for Mach64 compatible chips: *********************************** -#define SPARSE_IO_BASE 0x03fcu -#define SPARSE_IO_SELECT 0xfc00u +#define SPARSE_IO_BASE 0x03fcu +#define SPARSE_IO_SELECT 0xfc00u -#define BLOCK_IO_BASE 0xff00u -#define BLOCK_IO_SELECT 0x00fcu +#define BLOCK_IO_BASE 0xff00u +#define BLOCK_IO_SELECT 0x00fcu -#define MM_IO_SELECT 0x03fcu -#define BLOCK_SELECT 0x0400u -#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT) +#define MM_IO_SELECT 0x03fcu +#define BLOCK_SELECT 0x0400u +#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT) -#define IO_BYTE_SELECT 0x0003u +#define IO_BYTE_SELECT 0x0003u -#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT) -#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT) +#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT) +#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT) -#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \ - (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \ - SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT)) -#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0) -#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect) +#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \ + (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \ + SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT)) +#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0) +#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect) ... -#define OVERLAY_Y_X_START BlockIOTag(0x100u) -#define OVERLAY_Y_X_END BlockIOTag(0x101u) +#define OVERLAY_Y_X_START BlockIOTag(0x100u) +#define OVERLAY_Y_X_END BlockIOTag(0x101u) ... @@ -231,8 +231,8 @@ OUTREG(OVERLAY_Y_X_END,((drw_x+drw_w)<<16)|(drw_y+drw_h)); ... -#define INREG(addr) readl((rage_mmio_base)+addr) -#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr) +#define INREG(addr) readl((rage_mmio_base)+addr) +#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr) ... @@ -263,7 +263,7 @@ GATOS was designed and introduced as General ATI TV and Overlay Sowfware. You will be able to find out there a lots of useful hacking utilities (at location gatos-ati/gatos): gfxdump - Program for dumping graphics chips registers on Linux and Windows 9X. - (it's more useful for Win9x to hack their values). + (it's more useful for Win9x to hack their values). xatitv - For working with tv-in (currently is under hard development) atitvout- For working with tv-out and lot of other stuff. @@ -271,11 +271,11 @@ BUT: After studing of Gatos and X11 stuffs I've found that they are bad optimized for movie playback. Please compare: radeon_vid - configures video overlay only once and provides DGA to it. - (doesn't require to be MMX optimized) + (doesn't require to be MMX optimized) gatos and X11 - configures video overlay at every slice of frame, then performs unoptimized copying of source stuff to video memory - often with using CopyMungedData (it's C-analog of YV12_to_YUY2) - since there are lacks in yv12 support. + often with using CopyMungedData (it's C-analog of YV12_to_YUY2) + since there are lacks in yv12 support. (is not MMX optimized that's gladly accepted, but probably will be never optimized due portability). diff --git a/drivers/mga_vid.c b/drivers/mga_vid.c index 8330be29d6..de96aa1b0a 100644 --- a/drivers/mga_vid.c +++ b/drivers/mga_vid.c @@ -131,130 +131,130 @@ MODULE_LICENSE("GPL"); static unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) { - unsigned long result = 0,value; - - if (!base) { - base = 10; - if (*cp == '0') { - base = 8; - cp++; - if ((*cp == 'x') && isxdigit(cp[1])) { - cp++; - base = 16; - } - } - } - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) - ? toupper(*cp) : *cp)-'A'+10) < base) { - result = result*base + value; + unsigned long result = 0,value; + + if (!base) { + base = 10; + if (*cp == '0') { + base = 8; + cp++; + if ((*cp == 'x') && isxdigit(cp[1])) { cp++; + base = 16; + } } - if (endp) - *endp = (char *)cp; - return result; + } + while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) + ? toupper(*cp) : *cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + if (endp) + *endp = (char *)cp; + return result; } static long simple_strtol(const char *cp,char **endp,unsigned int base) { - if(*cp=='-') - return -simple_strtoul(cp+1,endp,base); - return simple_strtoul(cp,endp,base); + if(*cp=='-') + return -simple_strtoul(cp+1,endp,base); + return simple_strtoul(cp,endp,base); } #endif typedef struct bes_registers_s { - //BES Control - uint32_t besctl; - //BES Global control - uint32_t besglobctl; - //Luma control (brightness and contrast) - uint32_t beslumactl; - //Line pitch - uint32_t bespitch; - - //Buffer A-1 Chroma 3 plane org - uint32_t besa1c3org; - //Buffer A-1 Chroma org - uint32_t besa1corg; - //Buffer A-1 Luma org - uint32_t besa1org; - - //Buffer A-2 Chroma 3 plane org - uint32_t besa2c3org; - //Buffer A-2 Chroma org - uint32_t besa2corg; - //Buffer A-2 Luma org - uint32_t besa2org; - - //Buffer B-1 Chroma 3 plane org - uint32_t besb1c3org; - //Buffer B-1 Chroma org - uint32_t besb1corg; - //Buffer B-1 Luma org - uint32_t besb1org; - - //Buffer B-2 Chroma 3 plane org - uint32_t besb2c3org; - //Buffer B-2 Chroma org - uint32_t besb2corg; - //Buffer B-2 Luma org - uint32_t besb2org; - - //BES Horizontal coord - uint32_t beshcoord; - //BES Horizontal inverse scaling [5.14] - uint32_t beshiscal; - //BES Horizontal source start [10.14] (for scaling) - uint32_t beshsrcst; - //BES Horizontal source ending [10.14] (for scaling) - uint32_t beshsrcend; - //BES Horizontal source last - uint32_t beshsrclst; - - - //BES Vertical coord - uint32_t besvcoord; - //BES Vertical inverse scaling [5.14] - uint32_t besviscal; - //BES Field 1 vertical source last position - uint32_t besv1srclst; - //BES Field 1 weight start - uint32_t besv1wght; - //BES Field 2 vertical source last position - uint32_t besv2srclst; - //BES Field 2 weight start - uint32_t besv2wght; - - - //configurable stuff - int blackie; + //BES Control + uint32_t besctl; + //BES Global control + uint32_t besglobctl; + //Luma control (brightness and contrast) + uint32_t beslumactl; + //Line pitch + uint32_t bespitch; + + //Buffer A-1 Chroma 3 plane org + uint32_t besa1c3org; + //Buffer A-1 Chroma org + uint32_t besa1corg; + //Buffer A-1 Luma org + uint32_t besa1org; + + //Buffer A-2 Chroma 3 plane org + uint32_t besa2c3org; + //Buffer A-2 Chroma org + uint32_t besa2corg; + //Buffer A-2 Luma org + uint32_t besa2org; + + //Buffer B-1 Chroma 3 plane org + uint32_t besb1c3org; + //Buffer B-1 Chroma org + uint32_t besb1corg; + //Buffer B-1 Luma org + uint32_t besb1org; + + //Buffer B-2 Chroma 3 plane org + uint32_t besb2c3org; + //Buffer B-2 Chroma org + uint32_t besb2corg; + //Buffer B-2 Luma org + uint32_t besb2org; + + //BES Horizontal coord + uint32_t beshcoord; + //BES Horizontal inverse scaling [5.14] + uint32_t beshiscal; + //BES Horizontal source start [10.14] (for scaling) + uint32_t beshsrcst; + //BES Horizontal source ending [10.14] (for scaling) + uint32_t beshsrcend; + //BES Horizontal source last + uint32_t beshsrclst; + + + //BES Vertical coord + uint32_t besvcoord; + //BES Vertical inverse scaling [5.14] + uint32_t besviscal; + //BES Field 1 vertical source last position + uint32_t besv1srclst; + //BES Field 1 weight start + uint32_t besv1wght; + //BES Field 2 vertical source last position + uint32_t besv2srclst; + //BES Field 2 weight start + uint32_t besv2wght; + + + //configurable stuff + int blackie; } bes_registers_t; #ifdef CRTC2 typedef struct crtc2_registers_s { - uint32_t c2ctl; - uint32_t c2datactl; - uint32_t c2misc; - uint32_t c2hparam; - uint32_t c2hsync; - uint32_t c2offset; - uint32_t c2pl2startadd0; - uint32_t c2pl2startadd1; - uint32_t c2pl3startadd0; - uint32_t c2pl3startadd1; - uint32_t c2preload; - uint32_t c2spicstartadd0; - uint32_t c2spicstartadd1; - uint32_t c2startadd0; - uint32_t c2startadd1; - uint32_t c2subpiclut; - uint32_t c2vcount; - uint32_t c2vparam; - uint32_t c2vsync; + uint32_t c2ctl; + uint32_t c2datactl; + uint32_t c2misc; + uint32_t c2hparam; + uint32_t c2hsync; + uint32_t c2offset; + uint32_t c2pl2startadd0; + uint32_t c2pl2startadd1; + uint32_t c2pl3startadd0; + uint32_t c2pl3startadd1; + uint32_t c2preload; + uint32_t c2spicstartadd0; + uint32_t c2spicstartadd1; + uint32_t c2startadd0; + uint32_t c2startadd1; + uint32_t c2subpiclut; + uint32_t c2vcount; + uint32_t c2vparam; + uint32_t c2vsync; } crtc2_registers_t; #endif @@ -348,10 +348,10 @@ typedef struct crtc2_registers_s #define BESVCOORD 0x3d2c #define BESSTATUS 0x3dc4 -#define CRTCX 0x1fd4 -#define CRTCD 0x1fd5 -#define IEN 0x1e1c -#define ICLEAR 0x1e18 +#define CRTCX 0x1fd4 +#define CRTCD 0x1fd5 +#define IEN 0x1e1c +#define ICLEAR 0x1e18 #define STATUS 0x1e14 @@ -365,42 +365,42 @@ typedef struct mga_card_s { // local devfs handle for /dev/mga_vidX #ifdef CONFIG_DEVFS_FS - devfs_handle_t dev_handle; + devfs_handle_t dev_handle; #endif - uint8_t *param_buff; // buffer for read() - uint32_t param_buff_size; - uint32_t param_buff_len; - bes_registers_t regs; + uint8_t *param_buff; // buffer for read() + uint32_t param_buff_size; + uint32_t param_buff_len; + bes_registers_t regs; #ifdef CRTC2 - crtc2_registers_t cregs; + crtc2_registers_t cregs; #endif - uint32_t vid_in_use; - uint32_t is_g400; - uint32_t vid_src_ready; - uint32_t vid_overlay_on; + uint32_t vid_in_use; + uint32_t is_g400; + uint32_t vid_src_ready; + uint32_t vid_overlay_on; - uint8_t *mmio_base; - uint32_t mem_base; - int src_base; // YUV buffer position in video memory - uint32_t ram_size; // how much megabytes videoram we have - uint32_t top_reserved; // reserved space for console font (matroxfb + fastfont) + uint8_t *mmio_base; + uint32_t mem_base; + int src_base; // YUV buffer position in video memory + uint32_t ram_size; // how much megabytes videoram we have + uint32_t top_reserved; // reserved space for console font (matroxfb + fastfont) - int brightness; // initial brightness - int contrast; // initial contrast + int brightness; // initial brightness + int contrast; // initial contrast - struct pci_dev *pci_dev; + struct pci_dev *pci_dev; - mga_vid_config_t config; - int configured; // set to 1 when the card is configured over ioctl + mga_vid_config_t config; + int configured; // set to 1 when the card is configured over ioctl - int colkey_saved; - int colkey_on; - unsigned char colkey_color[4]; - unsigned char colkey_mask[4]; + int colkey_saved; + int colkey_on; + unsigned char colkey_color[4]; + unsigned char colkey_mask[4]; - int irq; // = -1 - int next_frame; + int irq; // = -1 + int next_frame; } mga_card_t; #define MGA_MAX_CARDS 16 @@ -428,48 +428,48 @@ static void crtc2_frame_sel(mga_card_t * card, int frame) { switch(frame) { case 0: - card->cregs.c2pl2startadd0=card->regs.besa1corg; - card->cregs.c2pl3startadd0=card->regs.besa1c3org; - card->cregs.c2startadd0=card->regs.besa1org; - break; + card->cregs.c2pl2startadd0=card->regs.besa1corg; + card->cregs.c2pl3startadd0=card->regs.besa1c3org; + card->cregs.c2startadd0=card->regs.besa1org; + break; case 1: - card->cregs.c2pl2startadd0=card->regs.besa2corg; - card->cregs.c2pl3startadd0=card->regs.besa2c3org; - card->cregs.c2startadd0=card->regs.besa2org; - break; + card->cregs.c2pl2startadd0=card->regs.besa2corg; + card->cregs.c2pl3startadd0=card->regs.besa2c3org; + card->cregs.c2startadd0=card->regs.besa2org; + break; case 2: - card->cregs.c2pl2startadd0=card->regs.besb1corg; - card->cregs.c2pl3startadd0=card->regs.besb1c3org; - card->cregs.c2startadd0=card->regs.besb1org; - break; + card->cregs.c2pl2startadd0=card->regs.besb1corg; + card->cregs.c2pl3startadd0=card->regs.besb1c3org; + card->cregs.c2startadd0=card->regs.besb1org; + break; case 3: - card->cregs.c2pl2startadd0=card->regs.besb2corg; - card->cregs.c2pl3startadd0=card->regs.besb2c3org; - card->cregs.c2startadd0=card->regs.besb2org; - break; + card->cregs.c2pl2startadd0=card->regs.besb2corg; + card->cregs.c2pl3startadd0=card->regs.besb2c3org; + card->cregs.c2startadd0=card->regs.besb2org; + break; } - writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0); - writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0); - writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0); + writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0); + writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0); + writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0); } #endif static void mga_vid_frame_sel(mga_card_t * card, int frame) { if ( card->irq != -1 ) { - card->next_frame=frame; + card->next_frame=frame; } else { - //we don't need the vcount protection as we're only hitting - //one register (and it doesn't seem to be double buffered) - card->regs.besctl = (card->regs.besctl & ~0x07000000) + (frame << 25); - writel( card->regs.besctl, card->mmio_base + BESCTL ); + //we don't need the vcount protection as we're only hitting + //one register (and it doesn't seem to be double buffered) + card->regs.besctl = (card->regs.besctl & ~0x07000000) + (frame << 25); + writel( card->regs.besctl, card->mmio_base + BESCTL ); -// writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16), - writel( card->regs.besglobctl + (MGA_VSYNC_POS<<16), - card->mmio_base + BESGLOBCTL); +// writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16), + writel( card->regs.besglobctl + (MGA_VSYNC_POS<<16), + card->mmio_base + BESGLOBCTL); #ifdef CRTC2 - crtc2_frame_sel(card, frame); + crtc2_frame_sel(card, frame); #endif } @@ -478,236 +478,235 @@ static void mga_vid_frame_sel(mga_card_t * card, int frame) static void mga_vid_write_regs(mga_card_t * card, int restore) { - //Make sure internal registers don't get updated until we're done - writel( (readl(card->mmio_base + VCOUNT)-1)<<16, - card->mmio_base + BESGLOBCTL); + //Make sure internal registers don't get updated until we're done + writel( (readl(card->mmio_base + VCOUNT)-1)<<16, + card->mmio_base + BESGLOBCTL); - // color or coordinate keying + // color or coordinate keying - if(restore && card->colkey_saved){ - // restore it - card->colkey_saved=0; + if(restore && card->colkey_saved){ + // restore it + card->colkey_saved=0; #ifdef MP_DEBUG - printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n", - card->colkey_on,card->colkey_color[0],card->colkey_color[1],card->colkey_color[2]); + printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n", + card->colkey_on,card->colkey_color[0],card->colkey_color[1],card->colkey_color[2]); #endif - // Set color key registers: - writeb( XKEYOPMODE, card->mmio_base + PALWTADD); - writeb( card->colkey_on, card->mmio_base + X_DATAREG); - - writeb( XCOLKEY0RED, card->mmio_base + PALWTADD); - writeb( card->colkey_color[0], card->mmio_base + X_DATAREG); - writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD); - writeb( card->colkey_color[1], card->mmio_base + X_DATAREG); - writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD); - writeb( card->colkey_color[2], card->mmio_base + X_DATAREG); - writeb( X_COLKEY, card->mmio_base + PALWTADD); - writeb( card->colkey_color[3], card->mmio_base + X_DATAREG); - - writeb( XCOLMSK0RED, card->mmio_base + PALWTADD); - writeb( card->colkey_mask[0], card->mmio_base + X_DATAREG); - writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD); - writeb( card->colkey_mask[1], card->mmio_base + X_DATAREG); - writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD); - writeb( card->colkey_mask[2], card->mmio_base + X_DATAREG); - writeb( XCOLMSK, card->mmio_base + PALWTADD); - writeb( card->colkey_mask[3], card->mmio_base + X_DATAREG); - - } else if(!card->colkey_saved){ - // save it - card->colkey_saved=1; - // Get color key registers: - writeb( XKEYOPMODE, card->mmio_base + PALWTADD); - card->colkey_on=(unsigned char)readb(card->mmio_base + X_DATAREG) & 1; - - writeb( XCOLKEY0RED, card->mmio_base + PALWTADD); - card->colkey_color[0]=(unsigned char)readb(card->mmio_base + X_DATAREG); - writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD); - card->colkey_color[1]=(unsigned char)readb(card->mmio_base + X_DATAREG); - writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD); - card->colkey_color[2]=(unsigned char)readb(card->mmio_base + X_DATAREG); - writeb( X_COLKEY, card->mmio_base + PALWTADD); - card->colkey_color[3]=(unsigned char)readb(card->mmio_base + X_DATAREG); - - writeb( XCOLMSK0RED, card->mmio_base + PALWTADD); - card->colkey_mask[0]=(unsigned char)readb(card->mmio_base + X_DATAREG); - writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD); - card->colkey_mask[1]=(unsigned char)readb(card->mmio_base + X_DATAREG); - writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD); - card->colkey_mask[2]=(unsigned char)readb(card->mmio_base + X_DATAREG); - writeb( XCOLMSK, card->mmio_base + PALWTADD); - card->colkey_mask[3]=(unsigned char)readb(card->mmio_base + X_DATAREG); + // Set color key registers: + writeb( XKEYOPMODE, card->mmio_base + PALWTADD); + writeb( card->colkey_on, card->mmio_base + X_DATAREG); + + writeb( XCOLKEY0RED, card->mmio_base + PALWTADD); + writeb( card->colkey_color[0], card->mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD); + writeb( card->colkey_color[1], card->mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD); + writeb( card->colkey_color[2], card->mmio_base + X_DATAREG); + writeb( X_COLKEY, card->mmio_base + PALWTADD); + writeb( card->colkey_color[3], card->mmio_base + X_DATAREG); + + writeb( XCOLMSK0RED, card->mmio_base + PALWTADD); + writeb( card->colkey_mask[0], card->mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD); + writeb( card->colkey_mask[1], card->mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD); + writeb( card->colkey_mask[2], card->mmio_base + X_DATAREG); + writeb( XCOLMSK, card->mmio_base + PALWTADD); + writeb( card->colkey_mask[3], card->mmio_base + X_DATAREG); + + } else if(!card->colkey_saved){ + // save it + card->colkey_saved=1; + // Get color key registers: + writeb( XKEYOPMODE, card->mmio_base + PALWTADD); + card->colkey_on=(unsigned char)readb(card->mmio_base + X_DATAREG) & 1; + + writeb( XCOLKEY0RED, card->mmio_base + PALWTADD); + card->colkey_color[0]=(unsigned char)readb(card->mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD); + card->colkey_color[1]=(unsigned char)readb(card->mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD); + card->colkey_color[2]=(unsigned char)readb(card->mmio_base + X_DATAREG); + writeb( X_COLKEY, card->mmio_base + PALWTADD); + card->colkey_color[3]=(unsigned char)readb(card->mmio_base + X_DATAREG); + + writeb( XCOLMSK0RED, card->mmio_base + PALWTADD); + card->colkey_mask[0]=(unsigned char)readb(card->mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD); + card->colkey_mask[1]=(unsigned char)readb(card->mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD); + card->colkey_mask[2]=(unsigned char)readb(card->mmio_base + X_DATAREG); + writeb( XCOLMSK, card->mmio_base + PALWTADD); + card->colkey_mask[3]=(unsigned char)readb(card->mmio_base + X_DATAREG); #ifdef MP_DEBUG - printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n", - card->colkey_on, card->colkey_color[0], card->colkey_color[1], card->colkey_color[2]); + printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n", + card->colkey_on, card->colkey_color[0], card->colkey_color[1], card->colkey_color[2]); #endif - } - -if(!restore){ - writeb( XKEYOPMODE, card->mmio_base + PALWTADD); - writeb( card->config.colkey_on, card->mmio_base + X_DATAREG); - if ( card->config.colkey_on ) - { - uint32_t r=0, g=0, b=0; - - writeb( XMULCTRL, card->mmio_base + PALWTADD); - switch (readb (card->mmio_base + X_DATAREG)) - { - case BPP_8: - /* Need to look up the color index, just using color 0 for now. */ - break; - - case BPP_15: - r = card->config.colkey_red >> 3; - g = card->config.colkey_green >> 3; - b = card->config.colkey_blue >> 3; - break; - - case BPP_16: - r = card->config.colkey_red >> 3; - g = card->config.colkey_green >> 2; - b = card->config.colkey_blue >> 3; - break; - - case BPP_24: - case BPP_32_DIR: - case BPP_32_PAL: - r = card->config.colkey_red; - g = card->config.colkey_green; - b = card->config.colkey_blue; - break; - } - - // Disable color keying on alpha channel - writeb( XCOLMSK, card->mmio_base + PALWTADD); - writeb( 0x00, card->mmio_base + X_DATAREG); - writeb( X_COLKEY, card->mmio_base + PALWTADD); - writeb( 0x00, card->mmio_base + X_DATAREG); - - - // Set up color key registers - writeb( XCOLKEY0RED, card->mmio_base + PALWTADD); - writeb( r, card->mmio_base + X_DATAREG); - writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD); - writeb( g, card->mmio_base + X_DATAREG); - writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD); - writeb( b, card->mmio_base + X_DATAREG); - - // Set up color key mask registers - writeb( XCOLMSK0RED, card->mmio_base + PALWTADD); - writeb( 0xff, card->mmio_base + X_DATAREG); - writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD); - writeb( 0xff, card->mmio_base + X_DATAREG); - writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD); - writeb( 0xff, card->mmio_base + X_DATAREG); - } + } -} + if(!restore){ + writeb( XKEYOPMODE, card->mmio_base + PALWTADD); + writeb( card->config.colkey_on, card->mmio_base + X_DATAREG); + if ( card->config.colkey_on ) + { + uint32_t r=0, g=0, b=0; + + writeb( XMULCTRL, card->mmio_base + PALWTADD); + switch (readb (card->mmio_base + X_DATAREG)) + { + case BPP_8: + /* Need to look up the color index, just using color 0 for now. */ + break; + + case BPP_15: + r = card->config.colkey_red >> 3; + g = card->config.colkey_green >> 3; + b = card->config.colkey_blue >> 3; + break; + + case BPP_16: + r = card->config.colkey_red >> 3; + g = card->config.colkey_green >> 2; + b = card->config.colkey_blue >> 3; + break; + + case BPP_24: + case BPP_32_DIR: + case BPP_32_PAL: + r = card->config.colkey_red; + g = card->config.colkey_green; + b = card->config.colkey_blue; + break; + } + + // Disable color keying on alpha channel + writeb( XCOLMSK, card->mmio_base + PALWTADD); + writeb( 0x00, card->mmio_base + X_DATAREG); + writeb( X_COLKEY, card->mmio_base + PALWTADD); + writeb( 0x00, card->mmio_base + X_DATAREG); + + + // Set up color key registers + writeb( XCOLKEY0RED, card->mmio_base + PALWTADD); + writeb( r, card->mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, card->mmio_base + PALWTADD); + writeb( g, card->mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, card->mmio_base + PALWTADD); + writeb( b, card->mmio_base + X_DATAREG); + + // Set up color key mask registers + writeb( XCOLMSK0RED, card->mmio_base + PALWTADD); + writeb( 0xff, card->mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, card->mmio_base + PALWTADD); + writeb( 0xff, card->mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, card->mmio_base + PALWTADD); + writeb( 0xff, card->mmio_base + X_DATAREG); + } + } + + // Backend Scaler + writel( card->regs.besctl, card->mmio_base + BESCTL); + if(card->is_g400) + writel( card->regs.beslumactl, card->mmio_base + BESLUMACTL); + writel( card->regs.bespitch, card->mmio_base + BESPITCH); + + writel( card->regs.besa1org, card->mmio_base + BESA1ORG); + writel( card->regs.besa1corg, card->mmio_base + BESA1CORG); + writel( card->regs.besa2org, card->mmio_base + BESA2ORG); + writel( card->regs.besa2corg, card->mmio_base + BESA2CORG); + writel( card->regs.besb1org, card->mmio_base + BESB1ORG); + writel( card->regs.besb1corg, card->mmio_base + BESB1CORG); + writel( card->regs.besb2org, card->mmio_base + BESB2ORG); + writel( card->regs.besb2corg, card->mmio_base + BESB2CORG); + if(card->is_g400) + { + writel( card->regs.besa1c3org, card->mmio_base + BESA1C3ORG); + writel( card->regs.besa2c3org, card->mmio_base + BESA2C3ORG); + writel( card->regs.besb1c3org, card->mmio_base + BESB1C3ORG); + writel( card->regs.besb2c3org, card->mmio_base + BESB2C3ORG); + } + + writel( card->regs.beshcoord, card->mmio_base + BESHCOORD); + writel( card->regs.beshiscal, card->mmio_base + BESHISCAL); + writel( card->regs.beshsrcst, card->mmio_base + BESHSRCST); + writel( card->regs.beshsrcend, card->mmio_base + BESHSRCEND); + writel( card->regs.beshsrclst, card->mmio_base + BESHSRCLST); + + writel( card->regs.besvcoord, card->mmio_base + BESVCOORD); + writel( card->regs.besviscal, card->mmio_base + BESVISCAL); - // Backend Scaler - writel( card->regs.besctl, card->mmio_base + BESCTL); - if(card->is_g400) - writel( card->regs.beslumactl, card->mmio_base + BESLUMACTL); - writel( card->regs.bespitch, card->mmio_base + BESPITCH); - - writel( card->regs.besa1org, card->mmio_base + BESA1ORG); - writel( card->regs.besa1corg, card->mmio_base + BESA1CORG); - writel( card->regs.besa2org, card->mmio_base + BESA2ORG); - writel( card->regs.besa2corg, card->mmio_base + BESA2CORG); - writel( card->regs.besb1org, card->mmio_base + BESB1ORG); - writel( card->regs.besb1corg, card->mmio_base + BESB1CORG); - writel( card->regs.besb2org, card->mmio_base + BESB2ORG); - writel( card->regs.besb2corg, card->mmio_base + BESB2CORG); - if(card->is_g400) - { - writel( card->regs.besa1c3org, card->mmio_base + BESA1C3ORG); - writel( card->regs.besa2c3org, card->mmio_base + BESA2C3ORG); - writel( card->regs.besb1c3org, card->mmio_base + BESB1C3ORG); - writel( card->regs.besb2c3org, card->mmio_base + BESB2C3ORG); - } - - writel( card->regs.beshcoord, card->mmio_base + BESHCOORD); - writel( card->regs.beshiscal, card->mmio_base + BESHISCAL); - writel( card->regs.beshsrcst, card->mmio_base + BESHSRCST); - writel( card->regs.beshsrcend, card->mmio_base + BESHSRCEND); - writel( card->regs.beshsrclst, card->mmio_base + BESHSRCLST); - - writel( card->regs.besvcoord, card->mmio_base + BESVCOORD); - writel( card->regs.besviscal, card->mmio_base + BESVISCAL); - - writel( card->regs.besv1srclst, card->mmio_base + BESV1SRCLST); - writel( card->regs.besv1wght, card->mmio_base + BESV1WGHT); - writel( card->regs.besv2srclst, card->mmio_base + BESV2SRCLST); - writel( card->regs.besv2wght, card->mmio_base + BESV2WGHT); - - //update the registers somewhere between 1 and 2 frames from now. - writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16), - card->mmio_base + BESGLOBCTL); + writel( card->regs.besv1srclst, card->mmio_base + BESV1SRCLST); + writel( card->regs.besv1wght, card->mmio_base + BESV1WGHT); + writel( card->regs.besv2srclst, card->mmio_base + BESV2SRCLST); + writel( card->regs.besv2wght, card->mmio_base + BESV2WGHT); + + //update the registers somewhere between 1 and 2 frames from now. + writel( card->regs.besglobctl + ((readl(card->mmio_base + VCOUNT)+2)<<16), + card->mmio_base + BESGLOBCTL); #if 0 - printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); - printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", - readl(card->mmio_base + BESCTL)); - printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", - readl(card->mmio_base + BESGLOBCTL)); - printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", - readl(card->mmio_base + BESSTATUS)); + printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); + printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", + readl(card->mmio_base + BESCTL)); + printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", + readl(card->mmio_base + BESGLOBCTL)); + printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", + readl(card->mmio_base + BESSTATUS)); #endif #ifdef CRTC2 -// printk("c2ctl:0x%08x c2datactl:0x%08x\n", readl(card->mmio_base + C2CTL), readl(card->mmio_base + C2DATACTL)); -// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC)); -// printk("c2ctl:0x%08x c2datactl:0x%08x\n", card->cregs.c2ctl, card->cregs.c2datactl); +// printk("c2ctl:0x%08x c2datactl:0x%08x\n", readl(card->mmio_base + C2CTL), readl(card->mmio_base + C2DATACTL)); +// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC)); +// printk("c2ctl:0x%08x c2datactl:0x%08x\n", card->cregs.c2ctl, card->cregs.c2datactl); -// writel(card->cregs.c2ctl, card->mmio_base + C2CTL); +// writel(card->cregs.c2ctl, card->mmio_base + C2CTL); - writel(((readl(card->mmio_base + C2CTL) & ~0x03e00000) + (card->cregs.c2ctl & 0x03e00000)), card->mmio_base + C2CTL); - writel(((readl(card->mmio_base + C2DATACTL) & ~0x000000ff) + (card->cregs.c2datactl & 0x000000ff)), card->mmio_base + C2DATACTL); - // ctrc2 - // disable CRTC2 acording to specs -// writel(card->cregs.c2ctl & 0xfffffff0, card->mmio_base + C2CTL); + writel(((readl(card->mmio_base + C2CTL) & ~0x03e00000) + (card->cregs.c2ctl & 0x03e00000)), card->mmio_base + C2CTL); + writel(((readl(card->mmio_base + C2DATACTL) & ~0x000000ff) + (card->cregs.c2datactl & 0x000000ff)), card->mmio_base + C2DATACTL); + // ctrc2 + // disable CRTC2 acording to specs +// writel(card->cregs.c2ctl & 0xfffffff0, card->mmio_base + C2CTL); // je to treba ??? -// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0xa2, card->mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel -// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0x92, card->mmio_base + XMISCCTRL); -// writeb((readb(card->mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, card->mmio_base + XMISCCTRL); -// writel(card->cregs.c2datactl, card->mmio_base + C2DATACTL); -// writel(card->cregs.c2hparam, card->mmio_base + C2HPARAM); -// writel(card->cregs.c2hsync, card->mmio_base + C2HSYNC); -// writel(card->cregs.c2vparam, card->mmio_base + C2VPARAM); -// writel(card->cregs.c2vsync, card->mmio_base + C2VSYNC); - writel(card->cregs.c2misc, card->mmio_base + C2MISC); +// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0xa2, card->mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel +// writeb((readb(card->mmio_base + XMISCCTRL) & 0x19) | 0x92, card->mmio_base + XMISCCTRL); +// writeb((readb(card->mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, card->mmio_base + XMISCCTRL); +// writel(card->cregs.c2datactl, card->mmio_base + C2DATACTL); +// writel(card->cregs.c2hparam, card->mmio_base + C2HPARAM); +// writel(card->cregs.c2hsync, card->mmio_base + C2HSYNC); +// writel(card->cregs.c2vparam, card->mmio_base + C2VPARAM); +// writel(card->cregs.c2vsync, card->mmio_base + C2VSYNC); + writel(card->cregs.c2misc, card->mmio_base + C2MISC); #ifdef MP_DEBUG - printk("c2offset = %d\n",card->cregs.c2offset); + printk("c2offset = %d\n",card->cregs.c2offset); #endif - writel(card->cregs.c2offset, card->mmio_base + C2OFFSET); - writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0); -// writel(card->cregs.c2startadd1, card->mmio_base + C2STARTADD1); - writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0); -// writel(card->cregs.c2pl2startadd1, card->mmio_base + C2PL2STARTADD1); - writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0); -// writel(card->cregs.c2pl3startadd1, card->mmio_base + C2PL3STARTADD1); - writel(card->cregs.c2spicstartadd0, card->mmio_base + C2SPICSTARTADD0); -// writel(card->cregs.c2spicstartadd1, card->mmio_base + C2SPICSTARTADD1); -// writel(card->cregs.c2subpiclut, card->mmio_base + C2SUBPICLUT); -// writel(card->cregs.c2preload, card->mmio_base + C2PRELOAD); - // finaly enable everything -// writel(card->cregs.c2ctl, card->mmio_base + C2CTL); -// printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(card->mmio_base + C2CTL),readl(card->mmio_base + C2DATACTL)); -// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC)); + writel(card->cregs.c2offset, card->mmio_base + C2OFFSET); + writel(card->cregs.c2startadd0, card->mmio_base + C2STARTADD0); +// writel(card->cregs.c2startadd1, card->mmio_base + C2STARTADD1); + writel(card->cregs.c2pl2startadd0, card->mmio_base + C2PL2STARTADD0); +// writel(card->cregs.c2pl2startadd1, card->mmio_base + C2PL2STARTADD1); + writel(card->cregs.c2pl3startadd0, card->mmio_base + C2PL3STARTADD0); +// writel(card->cregs.c2pl3startadd1, card->mmio_base + C2PL3STARTADD1); + writel(card->cregs.c2spicstartadd0, card->mmio_base + C2SPICSTARTADD0); +// writel(card->cregs.c2spicstartadd1, card->mmio_base + C2SPICSTARTADD1); +// writel(card->cregs.c2subpiclut, card->mmio_base + C2SUBPICLUT); +// writel(card->cregs.c2preload, card->mmio_base + C2PRELOAD); + // finaly enable everything +// writel(card->cregs.c2ctl, card->mmio_base + C2CTL); +// printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(card->mmio_base + C2CTL),readl(card->mmio_base + C2DATACTL)); +// printk("c2misc:0x%08x\n", readl(card->mmio_base + C2MISC)); #endif } static int mga_vid_set_config(mga_card_t * card) { - int x, y, sw, sh, dw, dh; - int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; - mga_vid_config_t *config = &card->config; - int frame_size = card->config.frame_size; + int x, y, sw, sh, dw, dh; + int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; + mga_vid_config_t *config = &card->config; + int frame_size = card->config.frame_size; #ifdef CRTC2 #define right_margin 0 @@ -717,615 +716,609 @@ static int mga_vid_set_config(mga_card_t * card) #define vsync_len 4 #define upper_margin 39 - unsigned int hdispend = (config->src_width + 31) & ~31; - unsigned int hsyncstart = hdispend + (right_margin & ~7); - unsigned int hsyncend = hsyncstart + (hsync_len & ~7); - unsigned int htotal = hsyncend + (left_margin & ~7); - unsigned int vdispend = config->src_height; - unsigned int vsyncstart = vdispend + lower_margin; - unsigned int vsyncend = vsyncstart + vsync_len; - unsigned int vtotal = vsyncend + upper_margin; + unsigned int hdispend = (config->src_width + 31) & ~31; + unsigned int hsyncstart = hdispend + (right_margin & ~7); + unsigned int hsyncend = hsyncstart + (hsync_len & ~7); + unsigned int htotal = hsyncend + (left_margin & ~7); + unsigned int vdispend = config->src_height; + unsigned int vsyncstart = vdispend + lower_margin; + unsigned int vsyncend = vsyncstart + vsync_len; + unsigned int vtotal = vsyncend + upper_margin; #endif - x = config->x_org; - y = config->y_org; - sw = config->src_width; - sh = config->src_height; - dw = config->dest_width; - dh = config->dest_height; + x = config->x_org; + y = config->y_org; + sw = config->src_width; + sh = config->src_height; + dw = config->dest_width; + dh = config->dest_height; #ifdef MP_DEBUG - printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", - dw, dh, x, y, sw, sh, config->format); + printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", + dw, dh, x, y, sw, sh, config->format); #endif - if(sw<4 || sh<4 || dw<4 || dh<4){ - printk(KERN_ERR "mga_vid: Invalid src/dest dimenstions\n"); - return -1; - } + if(sw<4 || sh<4 || dw<4 || dh<4){ + printk(KERN_ERR "mga_vid: Invalid src/dest dimenstions\n"); + return -1; + } - //FIXME check that window is valid and inside desktop + //FIXME check that window is valid and inside desktop - //Setup the BES registers for a three plane 4:2:0 video source + //Setup the BES registers for a three plane 4:2:0 video source - card->regs.besglobctl = 0; + card->regs.besglobctl = 0; -switch(config->format){ + switch(config->format){ case MGA_VID_FORMAT_YV12: case MGA_VID_FORMAT_I420: case MGA_VID_FORMAT_IYUV: - card->regs.besctl = 1 // BES enabled - + (0<<6) // even start polarity - + (1<<10) // x filtering enabled - + (1<<11) // y filtering enabled - + (1<<16) // chroma upsampling - + (1<<17) // 4:2:0 mode - + (1<<18); // dither enabled + card->regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (1<<17) // 4:2:0 mode + + (1<<18); // dither enabled #if 0 - if(card->is_g400) - { - //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp - //disabled, rgb mode disabled - card->regs.besglobctl = (1<<5); - } - else - { - //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr - //in 1357, BES register update on besvcnt - card->regs.besglobctl = 0; - } + if(card->is_g400) + { + //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp + //disabled, rgb mode disabled + card->regs.besglobctl = (1<<5); + } + else + { + //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr + //in 1357, BES register update on besvcnt + card->regs.besglobctl = 0; + } #endif break; case MGA_VID_FORMAT_YUY2: - card->regs.besctl = 1 // BES enabled - + (0<<6) // even start polarity - + (1<<10) // x filtering enabled - + (1<<11) // y filtering enabled - + (1<<16) // chroma upsampling - + (0<<17) // 4:2:2 mode - + (1<<18); // dither enabled - - card->regs.besglobctl = 0; // YUY2 format selected + card->regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (0<<17) // 4:2:2 mode + + (1<<18); // dither enabled + + card->regs.besglobctl = 0;