/*
radeon_vid - VIDIX based video driver for Radeon and Rage128 chips
Copyrights 2002 Nick Kurshev. This file is based on sources from
GATOS (gatos.sf.net) and X11 (www.xfree86.org)
Licence: GPL
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <inttypes.h>
#include "../../libdha/pci_ids.h"
#include "../../libdha/pci_names.h"
#include "../vidix.h"
#include "../fourcc.h"
#include "../../libdha/libdha.h"
#include "radeon.h"
#ifdef RAGE128
#define RADEON_MSG "Rage128_vid:"
#define X_ADJUST 0
#else
#define RADEON_MSG "Radeon_vid:"
#define X_ADJUST 8
#ifndef RADEON
#define RADEON
#endif
#endif
static int __verbose = 0;
typedef struct bes_registers_s
{
/* base address of yuv framebuffer */
uint32_t yuv_base;
uint32_t fourcc;
uint32_t dest_bpp;
/* YUV BES registers */
uint32_t reg_load_cntl;
uint32_t h_inc;
uint32_t step_by;
uint32_t y_x_start;
uint32_t y_x_end;
uint32_t v_inc;
uint32_t p1_blank_lines_at_top;
uint32_t p23_blank_lines_at_top;
uint32_t vid_buf_pitch0_value;
uint32_t vid_buf_pitch1_value;
uint32_t p1_x_start_end;
uint32_t p2_x_start_end;
uint32_t p3_x_start_end;
uint32_t base_addr;
uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES];
uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES];
uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES];
uint32_t vid_nbufs;
uint32_t p1_v_accum_init;
uint32_t p1_h_accum_init;
uint32_t p23_v_accum_init;
uint32_t p23_h_accum_init;
uint32_t scale_cntl;
uint32_t exclusive_horz;
uint32_t auto_flip_cntl;
uint32_t filter_cntl;
uint32_t key_cntl;
uint32_t test;
/* Configurable stuff */
int double_buff;
int brightness;
int saturation;
int ckey_on;
uint32_t graphics_key_clr;
uint32_t graphics_key_msk;
uint32_t ckey_cntl;
int deinterlace_on;
uint32_t deinterlace_pattern;
} bes_registers_t;
typedef struct video_registers_s
{
const char * sname;
uint32_t name;
uint32_t value;
}video_registers_t;
static bes_registers_t besr;
#ifndef RAGE128
static int IsR200=0;
#endif
#define DECLARE_VREG(name) { #name, name, 0 }
static video_registers_t vregs[] =
{
DECLARE_VREG(VIDEOMUX_CNTL),
DECLARE_VREG(VIPPAD_MASK),
DECLARE_VREG(VIPPAD1_A),
DECLARE_VREG(VIPPAD1_EN),
DECLARE_VREG(VIPPAD1_Y),
DECLARE_VREG(OV0_Y_X_START),
DECLARE_VREG(OV0_Y_X_END),
DECLARE_VREG(OV0_PIPELINE_CNTL),
DECLARE_VREG(OV0_EXCLUSIVE_HORZ),
DECLARE_VREG(OV0_EXCLUSIVE_VERT),
DECLARE_VREG(OV0_REG_LOAD_CNTL),
DECLARE_VREG(OV0_SCALE_CNTL),
DECLARE_VREG(OV0_V_INC),
DECLARE_VREG(OV0_P1_V_ACCUM_INIT),
DECLARE_VREG(OV0_P23_V_ACCUM_INIT),
DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP),
DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP),
#ifdef RADEON
DECLARE_VREG(OV0_BASE_ADDR),
#endif
DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS),
DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS),
DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS),
DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS),
DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS),
DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS),
DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE),
DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE),
DECLARE_VREG(OV0_AUTO_FLIP_CNTL),
DECLARE_VREG(OV0_DEINTERLACE_PATTERN),
DECLARE_VREG(OV0_SUBMIT_HISTORY),
DECLARE_VREG(OV0_H_INC),
DECLARE_VREG(OV0_STEP_BY),
DECLARE_VREG(OV0_P1_H_ACCUM_INIT),
DECLARE_VREG(OV0_P23_H_ACCUM_INIT),
DECLARE_VREG(OV0_P1_X_START_END),
DECLARE_VREG(OV0_P2_X_START_END),
DECLARE_VREG(OV0_P3_X_START_END),
DECLARE_VREG(OV0_FILTER_CNTL),
DECLARE_VREG(OV0_FOUR_TAP_COEF_0),
DECLARE_VREG(OV0_FOUR_TAP_COEF_1),
DECLARE_VREG(OV0_FOUR_TAP_COEF_2),
DECLARE_VREG(OV0_FOUR_TAP_COEF_3),
DECLARE_VREG(OV0_FOUR_TAP_COEF_4),
DECLARE_VREG(OV0_FLAG_CNTL),
#ifdef RAGE128
DECLARE_VREG(OV0_COLOUR_CNTL),
#else
DECLARE_VREG(OV0_SLICE_CNTL),
#endif
DECLARE_VREG(OV0_VID_KEY_CLR),
DECLARE_VREG(OV0_VID_KEY_MSK),
DECLARE_VREG(OV0_GRAPHICS_KEY_CLR),
DECLARE_VREG(OV0_GRAPHICS_KEY_MSK),
DECLARE_VREG(OV0_KEY_CNTL),
DECLARE_VREG(OV0_TEST),
DECLARE_VREG(OV0_LIN_TRANS_A),
DECLARE_VREG(OV0_LIN_TRANS_B),
DECLARE_VREG(OV0_LIN_TRANS_C),
DECLARE_VREG(OV0_LIN_TRANS_D),
DECLARE_VREG(OV0_LIN_TRANS_E),
DECLARE_VREG(OV0_LIN_TRANS_F),
DECLARE_VREG(OV0_GAMMA_0_F),
DECLARE_VREG(OV0_GAMMA_10_1F),
DECLARE_VREG(OV0_GAMMA_20_3F),
DECLARE_VREG(OV0_GAMMA_40_7F),
DECLARE_VREG(OV0_GAMMA_380_3BF),
DECLARE_VREG(OV0_GAMMA_3C0_3FF),
DECLARE_VREG(SUBPIC_CNTL),
DECLARE_VREG(SUBPIC_DEFCOLCON),
DECLARE_VREG(SUBPIC_Y_X_START),
DECLARE_VREG(SUBPIC_Y_X_END),
DECLARE_VREG(SUBPIC_V_INC),
DECLARE_VREG(SUBPIC_H_INC),
DECLARE_VREG(SUBPIC_BUF0_OFFSET),
DECLARE_VREG(SUBPIC_BUF1_OFFSET),
DECLARE_VREG(SUBPIC_LC0_OFFSET),
DECLARE_VREG(SUBPIC_LC1_OFFSET),
DECLARE_VREG(SUBPIC_PITCH),
DECLARE_VREG(SUBPIC_BTN_HLI_COLCON),
DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START),
DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END),
DECLARE_VREG(SUBPIC_PALETTE_INDEX),
DECLARE_VREG(SUBPIC_PALETTE_DATA),
DECLARE_VREG(SUBPIC_H_ACCUM_INIT),
DECLARE_VREG(SUBPIC_V_ACCUM_INIT),
DECLARE_VREG(IDCT_RUNS),
DECLARE_VREG(IDCT_LEVELS),
DECLARE_VREG(IDCT_AUTH_CONTROL),
DECLARE_VREG(IDCT_AUTH),
DECLARE_VREG(IDCT_CONTROL)
};
static void * radeon_mmio_base = 0;
static void * radeon_mem_base = 0;
static int32_t radeon_overlay_off = 0;
static uint32_t radeon_ram_size = 0;
#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
#define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr)
#define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val)
#define INREG(addr) GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr)
#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val)
#define OUTREGP(addr,val,mask) \
do { \
unsigned int _tmp = INREG(addr); \
_tmp &= (mask); \
_tmp |= (val); \
OUTREG(addr, _tmp); \
} while (0)
static __inline__ uint32_t INPLL(uint32_t addr)
{
OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
return (INREG(CLOCK_CNTL_DATA));
}
#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
OUTREG(CLOCK_CNTL_DATA, val)
#define OUTPLLP(addr,val,mask) \
do { \
unsigned int _tmp = INPLL(addr); \
_tmp &= (mask); \
_tmp |= (val); \
OUTPLL(addr, _tmp); \
} while (0)
static uint32_t radeon_vid_get_dbpp( void )
{
uint32_t dbpp,retval;
dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF;
switch(dbpp)
{
case DST_8BPP: retval = 8; break;
case DST_15BPP: retval = 15; break;
case DST_16BPP: retval = 16; break;
case DST_24BPP: retval = 24; break;
default: retval=32; break;
}
return retval;
}
static int radeon_is_dbl_scan( void )
{
return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN;
}
static int radeon_is_interlace( void )
{
return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN;
}
static uint32_t radeon_get_xres( void )
{
/* FIXME: currently we extract that from CRTC!!!*/
uint32_t xres,h_total;
h_total = INREG(CRTC_H_TOTAL_DISP);
xres = (h_total >> 16) & 0xffff;
return (xres + 1)*8;
}
static uint32_t radeon_get_yres( void
|