diff options
Diffstat (limited to 'vidix/radeon_vid.c')
| -rw-r--r-- | vidix/radeon_vid.c | 3480 |
1 files changed, 0 insertions, 3480 deletions
diff --git a/vidix/radeon_vid.c b/vidix/radeon_vid.c deleted file mode 100644 index ee68653c2c..0000000000 --- a/vidix/radeon_vid.c +++ /dev/null @@ -1,3480 +0,0 @@ -/* - * VIDIX driver for ATI Rage128 and Radeon chipsets. - * - * This file is based on sources from - * GATOS (gatos.sf.net) and X11 (www.xfree86.org) - * - * Copyright (C) 2002 Nick Kurshev - * support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de) - * - * This file is part of MPlayer. - * - * MPlayer is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * MPlayer is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with MPlayer; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <math.h> -#include <inttypes.h> - -#include "config.h" -#include "libavutil/common.h" -#include "mpbswap.h" -#include "pci_ids.h" -#include "pci_names.h" -#include "vidix.h" -#include "fourcc.h" -#include "dha.h" -#include "radeon.h" - -#if !defined(RAGE128) && defined(CONFIG_X11) -#include <X11/Xlib.h> -static uint32_t firegl_shift = 0; -#endif - -#ifdef RAGE128 -#define RADEON_MSG "[rage128]" -#define X_ADJUST 0 -#else -#define RADEON_MSG "[radeon]" -#define X_ADJUST (((besr.chip_flags&R_OVL_SHIFT)==R_OVL_SHIFT)?8:0) -#ifndef RADEON -#define RADEON -#endif -#endif - -#define RADEON_ASSERT(msg) printf(RADEON_MSG"################# FATAL:"msg); - -#define VERBOSE_LEVEL 0 -static int verbosity = 0; -typedef struct bes_registers_s -{ - /* base address of yuv framebuffer */ - uint32_t yuv_base; - uint32_t fourcc; - uint32_t surf_id; - int load_prg_start; - int horz_pick_nearest; - int vert_pick_nearest; - int swap_uv; /* for direct support of bgr fourccs */ - uint32_t dest_bpp; - /* YUV BES registers */ - uint32_t reg_load_cntl; - uint32_t h_inc; - uint32_t step_by; - uint32_t y_x_start; - uint32_t y_x_end; - uint32_t v_inc; - uint32_t p1_blank_lines_at_top; - uint32_t p23_blank_lines_at_top; - uint32_t vid_buf_pitch0_value; - uint32_t vid_buf_pitch1_value; - uint32_t p1_x_start_end; - uint32_t p2_x_start_end; - uint32_t p3_x_start_end; - uint32_t base_addr; - uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; - uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; - uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; - uint32_t vid_nbufs; - - uint32_t p1_v_accum_init; - uint32_t p1_h_accum_init; - uint32_t p23_v_accum_init; - uint32_t p23_h_accum_init; - uint32_t scale_cntl; - uint32_t exclusive_horz; - uint32_t auto_flip_cntl; - uint32_t filter_cntl; - uint32_t four_tap_coeff[5]; - uint32_t key_cntl; - uint32_t test; - /* Configurable stuff */ - int double_buff; - - int brightness; - int saturation; - - int ckey_on; - uint32_t graphics_key_clr; - uint32_t graphics_key_msk; - uint32_t ckey_cntl; - uint32_t merge_cntl; - - int deinterlace_on; - uint32_t deinterlace_pattern; - - unsigned chip_flags; -} bes_registers_t; - -typedef struct video_registers_s -{ - const char * sname; - uint32_t name; - uint32_t value; -}video_registers_t; - -static bes_registers_t besr; -#define DECLARE_VREG(name) { #name, name, 0 } -static const video_registers_t vregs[] = -{ - DECLARE_VREG(VIDEOMUX_CNTL), - DECLARE_VREG(VIPPAD_MASK), - DECLARE_VREG(VIPPAD1_A), - DECLARE_VREG(VIPPAD1_EN), - DECLARE_VREG(VIPPAD1_Y), - DECLARE_VREG(OV0_Y_X_START), - DECLARE_VREG(OV0_Y_X_END), - DECLARE_VREG(OV1_Y_X_START), - DECLARE_VREG(OV1_Y_X_END), - DECLARE_VREG(OV0_PIPELINE_CNTL), - DECLARE_VREG(OV0_EXCLUSIVE_HORZ), - DECLARE_VREG(OV0_EXCLUSIVE_VERT), - DECLARE_VREG(OV0_REG_LOAD_CNTL), - DECLARE_VREG(OV0_SCALE_CNTL), - DECLARE_VREG(OV0_V_INC), - DECLARE_VREG(OV0_P1_V_ACCUM_INIT), - DECLARE_VREG(OV0_P23_V_ACCUM_INIT), - DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), - DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), -#ifdef RADEON - DECLARE_VREG(OV0_BASE_ADDR), -#endif - DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), - DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), - DECLARE_VREG(OV0_AUTO_FLIP_CNTL), - DECLARE_VREG(OV0_DEINTERLACE_PATTERN), - DECLARE_VREG(OV0_SUBMIT_HISTORY), - DECLARE_VREG(OV0_H_INC), - DECLARE_VREG(OV0_STEP_BY), - DECLARE_VREG(OV0_P1_H_ACCUM_INIT), - DECLARE_VREG(OV0_P23_H_ACCUM_INIT), - DECLARE_VREG(OV0_P1_X_START_END), - DECLARE_VREG(OV0_P2_X_START_END), - DECLARE_VREG(OV0_P3_X_START_END), - DECLARE_VREG(OV0_FILTER_CNTL), - DECLARE_VREG(OV0_FOUR_TAP_COEF_0), - DECLARE_VREG(OV0_FOUR_TAP_COEF_1), - DECLARE_VREG(OV0_FOUR_TAP_COEF_2), - DECLARE_VREG(OV0_FOUR_TAP_COEF_3), - DECLARE_VREG(OV0_FOUR_TAP_COEF_4), - DECLARE_VREG(OV0_FLAG_CNTL), -#ifdef RAGE128 - DECLARE_VREG(OV0_COLOUR_CNTL), -#else - DECLARE_VREG(OV0_SLICE_CNTL), -#endif - DECLARE_VREG(OV0_VID_KEY_CLR), - DECLARE_VREG(OV0_VID_KEY_MSK), - DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), - DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), - DECLARE_VREG(OV0_KEY_CNTL), - DECLARE_VREG(OV0_TEST), - DECLARE_VREG(OV0_LIN_TRANS_A), - DECLARE_VREG(OV0_LIN_TRANS_B), - DECLARE_VREG(OV0_LIN_TRANS_C), - DECLARE_VREG(OV0_LIN_TRANS_D), - DECLARE_VREG(OV0_LIN_TRANS_E), - DECLARE_VREG(OV0_LIN_TRANS_F), - DECLARE_VREG(OV0_GAMMA_0_F), - DECLARE_VREG(OV0_GAMMA_10_1F), - DECLARE_VREG(OV0_GAMMA_20_3F), - DECLARE_VREG(OV0_GAMMA_40_7F), - DECLARE_VREG(OV0_GAMMA_380_3BF), - DECLARE_VREG(OV0_GAMMA_3C0_3FF), - DECLARE_VREG(SUBPIC_CNTL), - DECLARE_VREG(SUBPIC_DEFCOLCON), - DECLARE_VREG(SUBPIC_Y_X_START), - DECLARE_VREG(SUBPIC_Y_X_END), - DECLARE_VREG(SUBPIC_V_INC), - DECLARE_VREG(SUBPIC_H_INC), - DECLARE_VREG(SUBPIC_BUF0_OFFSET), - DECLARE_VREG(SUBPIC_BUF1_OFFSET), - DECLARE_VREG(SUBPIC_LC0_OFFSET), - DECLARE_VREG(SUBPIC_LC1_OFFSET), - DECLARE_VREG(SUBPIC_PITCH), - DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), - DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), - DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), - DECLARE_VREG(SUBPIC_PALETTE_INDEX), - DECLARE_VREG(SUBPIC_PALETTE_DATA), - DECLARE_VREG(SUBPIC_H_ACCUM_INIT), - DECLARE_VREG(SUBPIC_V_ACCUM_INIT), - DECLARE_VREG(IDCT_RUNS), - DECLARE_VREG(IDCT_LEVELS), - DECLARE_VREG(IDCT_AUTH_CONTROL), - DECLARE_VREG(IDCT_AUTH), - DECLARE_VREG(IDCT_CONTROL), -#ifdef RAGE128 - DECLARE_VREG(BM_FRAME_BUF_OFFSET), - DECLARE_VREG(BM_SYSTEM_MEM_ADDR), - DECLARE_VREG(BM_COMMAND), - DECLARE_VREG(BM_STATUS), - DECLARE_VREG(BM_QUEUE_STATUS), - DECLARE_VREG(BM_QUEUE_FREE_STATUS), - DECLARE_VREG(BM_CHUNK_0_VAL), - DECLARE_VREG(BM_CHUNK_1_VAL), - DECLARE_VREG(BM_VIP0_BUF), - DECLARE_VREG(BM_VIP0_ACTIVE), - DECLARE_VREG(BM_VIP1_BUF), - DECLARE_VREG(BM_VIP1_ACTIVE), - DECLARE_VREG(BM_VIP2_BUF), - DECLARE_VREG(BM_VIP2_ACTIVE), - DECLARE_VREG(BM_VIP3_BUF), - DECLARE_VREG(BM_VIP3_ACTIVE), - DECLARE_VREG(BM_VIDCAP_BUF0), - DECLARE_VREG(BM_VIDCAP_BUF1), - DECLARE_VREG(BM_VIDCAP_BUF2), - DECLARE_VREG(BM_VIDCAP_ACTIVE), - DECLARE_VREG(BM_GUI), - DECLARE_VREG(BM_ABORT) -#else - DECLARE_VREG(DISP_MERGE_CNTL), - DECLARE_VREG(DMA_GUI_TABLE_ADDR), - DECLARE_VREG(DMA_GUI_SRC_ADDR), - DECLARE_VREG(DMA_GUI_DST_ADDR), - DECLARE_VREG(DMA_GUI_COMMAND), - DECLARE_VREG(DMA_GUI_STATUS), - DECLARE_VREG(DMA_GUI_ACT_DSCRPTR), - DECLARE_VREG(DMA_VID_SRC_ADDR), - DECLARE_VREG(DMA_VID_DST_ADDR), - DECLARE_VREG(DMA_VID_COMMAND), - DECLARE_VREG(DMA_VID_STATUS), - DECLARE_VREG(DMA_VID_ACT_DSCRPTR), -#endif -}; - -#define R_FAMILY 0x000000FF -#define R_100 0x00000001 -#define R_120 0x00000002 -#define R_150 0x00000004 -#define R_200 0x00000008 -#define R_250 0x00000010 -#define R_280 0x00000020 -#define R_300 0x00000040 -#define R_350 0x00000080 -#define R_370 0x00000100 -#define R_380 0x00000200 -#define R_420 0x00000400 -#define R_430 0x00000800 -#define R_480 0x00001000 -#define R_OVL_SHIFT 0x01000000 -#define R_INTEGRATED 0x02000000 -#define R_PCIE 0x04000000 - -typedef struct ati_card_ids_s -{ - unsigned short id; - unsigned flags; -}ati_card_ids_t; - -static const ati_card_ids_t ati_card_ids[] = -{ -#ifdef RAGE128 - /* - This driver should be compatible with Rage128 (pro) chips. - (include adaptive deinterlacing!!!). - Moreover: the same logic can be used with Mach64 chips. - (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). - but they are incompatible by i/o ports. So if enthusiasts will want - then they can redefine OUTREG and INREG macros and redefine OV0_* - constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY - fourccs (422 and 420 formats only). - */ -/* Rage128 Pro GL */ - { DEVICE_ATI_RAGE_128_PA_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PB_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PC_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PD_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PE_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PF_PRO, 0 }, -/* Rage128 Pro VR */ - { DEVICE_ATI_RAGE_128_PG_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PH_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PI_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PJ_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PK_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PL_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PM_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PN_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PO_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PP_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PQ_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PR_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PS_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PT_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PU_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PV_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PW_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PX_PRO, 0 }, -/* Rage128 GL */ - { DEVICE_ATI_RAGE_128_RE_SG, 0 }, - { DEVICE_ATI_RAGE_128_RF_SG, 0 }, - { DEVICE_ATI_RAGE_128_RG, 0 }, - { DEVICE_ATI_RAGE_128_RK_VR, 0 }, - { DEVICE_ATI_RAGE_128_RL_VR, 0 }, - { DEVICE_ATI_RAGE_128_SE_4X, 0 }, - { DEVICE_ATI_RAGE_128_SF_4X, 0 }, - { DEVICE_ATI_RAGE_128_SG_4X, 0 }, - { DEVICE_ATI_RAGE_128_SH, 0 }, - { DEVICE_ATI_RAGE_128_SK_4X, 0 }, - { DEVICE_ATI_RAGE_128_SL_4X, 0 }, - { DEVICE_ATI_RAGE_128_SM_4X, 0 }, - { DEVICE_ATI_RAGE_128_4X, 0 }, - { DEVICE_ATI_RAGE_128_PRO, 0 }, - { DEVICE_ATI_RAGE_128_PRO2, 0 }, - { DEVICE_ATI_RAGE_128_PRO3, 0 }, -/* these seem to be based on rage 128 instead of mach64 */ - { DEVICE_ATI_RAGE_MOBILITY_M3, 0 }, - { DEVICE_ATI_RAGE_MOBILITY_M32, 0 }, -#else -/* Radeon1 (indeed: Rage 256 Pro ;) */ - { DEVICE_ATI_RADEON_R100_QD, R_100|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_R100_QE, R_100|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_R100_QF, R_100|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_R100_QG, R_100|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_IGP_320, R_150|R_OVL_SHIFT|R_INTEGRATED }, - { DEVICE_ATI_RADEON_MOBILITY_U1, R_150|R_OVL_SHIFT|R_INTEGRATED }, - { DEVICE_ATI_RADEON_RV100_QY, R_120|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_RV100_QZ, R_120|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_MOBILITY_M7, R_150|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_RV200_LX, R_150|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_MOBILITY_M6, R_120|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_MOBILITY_M62, R_120|R_OVL_SHIFT }, -/* Radeon2 (indeed: Rage 512 Pro ;) */ - { DEVICE_ATI_R200_BB_RADEON, R_200 }, - { DEVICE_ATI_R200_BC_RADEON, R_200 }, - { DEVICE_ATI_RADEON_R200_QH, R_200 }, - { DEVICE_ATI_RADEON_R200_QI, R_200 }, - { DEVICE_ATI_RADEON_R200_QJ, R_200 }, - { DEVICE_ATI_RADEON_R200_QK, R_200 }, - { DEVICE_ATI_RADEON_R200_QL, R_200 }, - { DEVICE_ATI_RADEON_R200_QM, R_200 }, - { DEVICE_ATI_RADEON_R200_QN, R_200 }, - { DEVICE_ATI_RADEON_R200_QO, R_200 }, - { DEVICE_ATI_RADEON_R200_QH2, R_200 }, - { DEVICE_ATI_RADEON_R200_QI2, R_200 }, - { DEVICE_ATI_RADEON_R200_QJ2, R_200 }, - { DEVICE_ATI_RADEON_R200_QK2, R_200 }, - { DEVICE_ATI_RADEON_R200_QL2, R_200 }, - { DEVICE_ATI_RADEON_RV200_QW, R_150|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_RV200_QX, R_150|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_IGP330_340_350,R_200|R_INTEGRATED }, - { DEVICE_ATI_RADEON_IGP_330M_340M_350M,R_200|R_INTEGRATED }, - { DEVICE_ATI_RADEON_RV250_IG, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_7000_IGP, R_250|R_OVL_SHIFT|R_INTEGRATED }, - { DEVICE_ATI_RADEON_MOBILITY_7000, R_250|R_OVL_SHIFT|R_INTEGRATED }, - { DEVICE_ATI_RADEON_RV250_ID, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_RV250_IE, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_RV250_IF, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_RV250_IG, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_R250_LD, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_R250_LE, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_R250_MOBILITY, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_R250_LG, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RV250_RADEON_9000, R_250|R_OVL_SHIFT }, - { DEVICE_ATI_RADEON_RV250_RADEON2, R_250|R_OVL_SHIFT }, - // Only 92006 and 92007 tested to actually require this - { DEVICE_ATI_RV280_RADEON_9200, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_RV280_RADEON_92002, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_RV280_RADEON_92003, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_RV280_RADEON_92004, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_RV280_RADEON_92005, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_RV280_RADEON_92006, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_RV280_RADEON_92007, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_M9_5C61_RADEON, R_280|R_OVL_SHIFT }, - { DEVICE_ATI_M9_5C63_RADEON, R_280|R_OVL_SHIFT }, -/* Radeon3 (indeed: Rage 1024 Pro ;) */ - { DEVICE_ATI_R300_AG_FIREGL, R_300 }, - { DEVICE_ATI_RADEON_R300_ND, R_300 }, - { DEVICE_ATI_RADEON_R300_NE, R_300 }, - { DEVICE_ATI_RADEON_R300_NG, R_300 }, - { DEVICE_ATI_R300_AD_RADEON, R_300 }, - { DEVICE_ATI_R300_AE_RADEON, R_300 }, - { DEVICE_ATI_R300_AF_RADEON, R_300 }, - { DEVICE_ATI_RADEON_9100_IGP2, R_300|R_OVL_SHIFT|R_INTEGRATED }, - { DEVICE_ATI_RS300M_AGP_RADEON, R_300|R_INTEGRATED }, - { DEVICE_ATI_RS482_RADEON_XPRESS, R_350|R_INTEGRATED }, - { DEVICE_ATI_R350_AH_RADEON, R_350 }, - { DEVICE_ATI_R350_AI_RADEON, R_350 }, - { DEVICE_ATI_R350_AJ_RADEON, R_350 }, - { DEVICE_ATI_R350_AK_FIRE, R_350 }, - { DEVICE_ATI_RADEON_R350_RADEON2, R_350 }, - { DEVICE_ATI_RADEON_R350_RADEON3, R_350 }, - { DEVICE_ATI_RV350_NJ_RADEON, R_350 }, - { DEVICE_ATI_R350_NK_FIRE, R_350 }, - { DEVICE_ATI_RV350_AP_RADEON, R_350 }, - { DEVICE_ATI_RV350_AQ_RADEON, R_350 }, - { DEVICE_ATI_RV350_AR_RADEON, R_350 }, - { DEVICE_ATI_RV350_AS_RADEON, R_350 }, - { DEVICE_ATI_RV350_AT_FIRE, R_350 }, - { DEVICE_ATI_RV350_AU_FIRE, R_350 }, - { DEVICE_ATI_RV350_AV_FIRE, R_350 }, - { DEVICE_ATI_RV350_AW_FIRE, R_350 }, - { DEVICE_ATI_RV350_MOBILITY_RADEON, R_350 }, - { DEVICE_ATI_RV350_NF_RADEON, R_300 }, - { DEVICE_ATI_RV350_NJ_RADEON, R_300 }, - { DEVICE_ATI_RV350_AS_RADEON2, R_350 }, - { DEVICE_ATI_M10_NQ_RADEON, R_350 }, - { DEVICE_ATI_M10_NQ_RADEON2, R_350 }, - { DEVICE_ATI_RV350_MOBILITY_RADEON2, R_350 }, - { DEVICE_ATI_M10_NS_RADEON, R_350 }, - { DEVICE_ATI_M10_NT_FIREGL, R_350 }, - { DEVICE_ATI_M11_NV_FIREGL, R_350 }, - { DEVICE_ATI_RV370_5B60_RADEON, R_370|R_PCIE }, - { DEVICE_ATI_RV370_SAPPHIRE_X550, R_370 }, - { DEVICE_ATI_RV370_5B64_FIREGL, R_370|R_PCIE }, - { DEVICE_ATI_RV370_5B65_FIREGL, R_370|R_PCIE }, - { DEVICE_ATI_M24_1P_RADEON, R_370 }, - { DEVICE_ATI_M22_RADEON_MOBILITY, R_370 }, - { DEVICE_ATI_M24_1T_FIREGL, R_370 }, - { DEVICE_ATI_M24_RADEON_MOBILITY, R_370 }, - { DEVICE_ATI_RV370_RADEON_X300SE, R_370 }, - { DEVICE_ATI_RV370_SECONDARY_SAPPHIRE, R_370 }, - { DEVICE_ATI_RV370_5B64_FIREGL2, R_370 }, - { DEVICE_ATI_RV380_0X3E50_RADEON, R_380|R_PCIE }, - { DEVICE_ATI_RV380_0X3E54_FIREGL, R_380|R_PCIE }, - { DEVICE_ATI_RV380_RADEON_X600, R_380|R_PCIE }, - { DEVICE_ATI_RV380_RADEON_X6002, R_380 }, - { DEVICE_ATI_RV380_RADEON_X6003, R_380 }, - { DEVICE_ATI_RV410_FIREGL_V5000, R_420 }, - { DEVICE_ATI_RV410_FIREGL_V3300, R_420 }, - { DEVICE_ATI_RV410_RADEON_X700XT, R_420 }, - { DEVICE_ATI_RV410_RADEON_X700, R_420|R_PCIE }, - { DEVICE_ATI_RV410_RADEON_X700SE, R_420 }, - { DEVICE_ATI_RV410_RADEON_X7002, R_420|R_PCIE }, - { DEVICE_ATI_RV410_RADEON_X7003, R_420 }, - { DEVICE_ATI_RV410_RADEON_X7004, R_420|R_PCIE }, - { DEVICE_ATI_RV410_RADEON_X7005, R_420|R_PCIE }, - { DEVICE_ATI_M26_MOBILITY_FIREGL, R_420 }, - { DEVICE_ATI_M26_MOBILITY_FIREGL2, R_420 }, - { DEVICE_ATI_M26_RADEON_MOBILITY, R_420 }, - { DEVICE_ATI_M26_RADEON_MOBILITY2, R_420 }, - { DEVICE_ATI_RADEON_MOBILITY_X700, R_420 }, - { DEVICE_ATI_R420_JH_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R420_JI_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R420_JJ_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R420_JK_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R420_JL_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R420_JM_FIREGL, R_420|R_PCIE }, - { DEVICE_ATI_M18_JN_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R420_JP_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R420_RADEON_X800, R_420|R_PCIE }, - { DEVICE_ATI_R420_RADEON_X8002, R_420|R_PCIE }, - { DEVICE_ATI_R420_RADEON_X8003, R_420|R_PCIE }, - { DEVICE_ATI_R420_RADEON_X8004, R_420|R_PCIE }, - { DEVICE_ATI_R420_RADEON_X8005, R_420|R_PCIE }, - { DEVICE_ATI_R420_JM_FIREGL, R_420|R_PCIE }, - { DEVICE_ATI_R423_5F57_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R423_5F57_RADEON2, R_420|R_PCIE }, - { DEVICE_ATI_R423_UH_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R423_UI_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R423_UJ_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R423_UK_RADEON, R_420|R_PCIE }, - { DEVICE_ATI_R423_FIRE_GL, R_420|R_PCIE }, - { DEVICE_ATI_R423_UQ_FIREGL, R_420|R_PCIE }, - { DEVICE_ATI_R423_UR_FIREGL, R_420|R_PCIE }, - { DEVICE_ATI_R423_UT_FIREGL, R_420|R_PCIE }, - { DEVICE_ATI_R423_UI_RADEON2, R_420|R_PCIE }, - { DEVICE_ATI_R423GL_SE_ATI_FIREGL, R_420|R_PCIE }, - { DEVICE_ATI_R423_RADEON_X800XT, R_420|R_PCIE }, - { DEVICE_ATI_RADEON_R423_UK, R_420|R_PCIE }, - { DEVICE_ATI_M28_RADEON_MOBILITY, R_420 }, - { DEVICE_ATI_M28_MOBILITY_FIREGL, R_420 }, - { DEVICE_ATI_MOBILITY_RADEON_X800, R_420 }, - { DEVICE_ATI_R430_RADEON_X800, R_430|R_PCIE }, - { DEVICE_ATI_R430_RADEON_X8002, R_430|R_PCIE }, - { DEVICE_ATI_R430_RADEON_X8003, R_430|R_PCIE }, - { DEVICE_ATI_R430_RADEON_X8004, R_430|R_PCIE }, - { DEVICE_ATI_R480_RADEON_X800, R_480 }, - { DEVICE_ATI_R480_RADEON_X8002, R_480 }, - { DEVICE_ATI_R480_RADEON_X850XT, R_480 }, - { DEVICE_ATI_R480_RADEON_X850PRO, R_480 }, - { DEVICE_ATI_R481_RADEON_X850XT_PE, R_480|R_PCIE }, - { DEVICE_ATI_R480_RADEON_X850XT2, R_480 }, - { DEVICE_ATI_R480_RADEON_X850PRO2, R_480 }, - { DEVICE_ATI_R481_RADEON_X850XT_PE2, R_480|R_PCIE }, - { DEVICE_ATI_R480_RADEON_X850XT3, R_480|R_PCIE }, - { DEVICE_ATI_R480_RADEON_X850XT4, R_480|R_PCIE }, - { DEVICE_ATI_R480_RADEON_X850XT5, R_480|R_PCIE }, - { DEVICE_ATI_R480_RADEON_X850XT6, R_480|R_PCIE }, -#endif -}; - - -static void * radeon_mmio_base = 0; -static void * radeon_mem_base = 0; -static int32_t radeon_overlay_off = 0; -static uint32_t radeon_ram_size = 0; - -#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) -#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL - -#define INREG8(addr) GETREG(uint8_t,(uint8_t *)(radeon_mmio_base),addr) -#define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t *)(radeon_mmio_base),addr,val) -static inline uint32_t INREG (uint32_t addr) { - uint32_t tmp = GETREG(uint32_t,(uint8_t *)(radeon_mmio_base),addr); - return le2me_32(tmp); -} -#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t *)(radeon_mmio_base),addr,le2me_32(val)) -#define OUTREGP(addr,val,mask) \ - do { \ - unsigned int _tmp = INREG(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTREG(addr, _tmp); \ - } while (0) - -static __inline__ uint32_t INPLL(uint32_t addr) -{ - OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); - return INREG(CLOCK_CNTL_DATA); -} - -#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ - OUTREG(CLOCK_CNTL_DATA, val) -#define OUTPLLP(addr,val,mask) \ - do { \ - unsigned int _tmp = INPLL(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTPLL(addr, _tmp); \ - } while (0) - -#ifndef RAGE128 -enum radeon_montype -{ - MT_NONE, - MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */ - MT_LCD, /* Liquid Crystal Display */ - MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */ - MT_CTV, /* Composite TV out (not in VE) */ - MT_STV /* S-Video TV out (probably in VE only) */ -}; - -typedef struct radeon_info_s -{ - int hasCRTC2; - int crtDispType; - int dviDispType; -}rinfo_t; - -static rinfo_t rinfo; - -static char * GET_MON_NAME(int type) -{ - char *pret; - switch(type) - { - case MT_NONE: pret = "no"; break; - case MT_CRT: pret = "CRT"; break; - case MT_DFP: pret = "DFP"; break; - case MT_LCD: pret = "LCD"; break; - case MT_CTV: pret = "CTV"; break; - case MT_STV: pret = "STV"; break; - default: pret = "Unknown"; - } - return pret; -} - -static void radeon_get_moninfo (rinfo_t *rinfo) -{ - unsigned int tmp; - - tmp = INREG(RADEON_BIOS_4_SCRATCH); - - if (rinfo->hasCRTC2) { - /* primary DVI port */ - if (tmp & 0x08) - rinfo->dviDispType = MT_DFP; - else if (tmp & 0x4) - rinfo->dviDispType = MT_LCD; - else if (tmp & 0x200) - rinfo->dviDispType = MT_CRT; - else if (tmp & 0x10) - rinfo->dviDispType = MT_CTV; - else if (tmp & 0x20) - rinfo->dviDispType = MT_STV; - - /* secondary CRT port */ - if (tmp & 0x2) - rinfo->crtDispType = MT_CRT; - else if (tmp & 0x800) - rinfo->crtDispType = MT_DFP; - else if (tmp & 0x400) - rinfo->crtDispType = MT_LCD; - else if (tmp & 0x1000) - rinfo->crtDispType = MT_CTV; - else if (tmp & 0x2000) - rinfo->crtDispType = MT_STV; - } else { - rinfo->dviDispType = MT_NONE; - - tmp = INREG(FP_GEN_CNTL); - - if (tmp & FP_EN_TMDS) - rinfo->crtDispType = MT_DFP; - else - rinfo->crtDispType = MT_CRT; - } -} -#endif - -static uint32_t radeon_vid_get_dbpp( void ) -{ - uint32_t dbpp,retval; - dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; - switch(dbpp) - { - case DST_8BPP: retval = 8; break; - case DST_15BPP: retval = 15; break; - case DST_16BPP: retval = 16; break; - case DST_24BPP: retval = 24; break; - default: retval=32; break; - } - return retval; -} - -static int radeon_is_dbl_scan( void ) -{ - return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; -} - -static int radeon_is_interlace( void ) -{ - return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; -} - -static uint32_t radeon_get_xres( void ) -{ - uint32_t xres,h_total; -#ifndef RAGE128 - if(rinfo.hasCRTC2 && - (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV)) - h_total = INREG(CRTC2_H_TOTAL_DISP); - else -#endif - h_total = INREG(CRTC_H_TOTAL_DISP); - xres = (h_total >> 16) & 0xffff; - return (xres + 1)*8; -} - -static uint32_t radeon_get_yres( void ) -{ - uint32_t yres,v_total; -#ifndef RAGE128 - if(rinfo.hasCRTC2 && - (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV)) - v_total = INREG(CRTC2_V_TOTAL_DISP); - else -#endif - v_total = INREG(CRTC_V_TOTAL_DISP); - yres = (v_total >> 16) & 0xffff; - return yres + 1; -} - -static void radeon_wait_vsync(void) -{ - int i; - - OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); - for (i = 0; i < 2000000; i++) - { - if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; - } -} - -#ifdef RAGE128 -static void _radeon_engine_idle(void); -static void _radeon_fifo_wait(unsigned); -#define radeon_engine_idle() _radeon_engine_idle() -#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) -/* Flush all dirty data in the Pixel Cache to memory. */ -static __inline__ void radeon_engine_flush ( void ) -{ - unsigned i; - - OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); - for (i = 0; i < 2000000; i++) { - if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; - } -} - -/* Reset graphics card to known state. */ -static void radeon_engine_reset( void ) -{ - uint32_t clock_cntl_index; - uint32_t mclk_cntl; - uint32_t gen_reset_cntl; - - radeon_engine_flush(); - - clock_cntl_index = INREG(CLOCK_CNTL_INDEX); - mclk_cntl = INPLL(MCLK_CNTL); - - OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); - - gen_reset_cntl = INREG(GEN_RESET_CNTL); - - OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); - INREG(GEN_RESET_CNTL); - OUTREG(GEN_RESET_CNTL, - gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); - INREG(GEN_RESET_CNTL); - - OUTPLL(MCLK_CNTL, mclk_cntl); - OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); - OUTREG(GEN_RESET_CNTL, gen_reset_cntl); -} -#else - -static __inline__ void radeon_engine_flush ( void ) -{ - int i; - - /* initiate flush */ - OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); - - for (i=0; i < 2000000; i++) { - if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) - break; - } -} - -static void _radeon_engine_idle(void); -static void _radeon_fifo_wait(unsigned); -#define radeon_engine_idle() _radeon_engine_idle() -#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) - -static void radeon_engine_reset( void ) -{ - uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; - - radeon_engine_flush (); - - clock_cntl_index = INREG(CLOCK_CNTL_INDEX); - mclk_cntl = INPLL(MCLK_CNTL); - - OUTPLL(MCLK_CNTL, (mclk_cntl | - FORCEON_MCLKA | - FORCEON_MCLKB | - FORCEON_YCLKA | - FORCEON_YCLKB | - FORCEON_MC | - FORCEON_AIC)); - rbbm_soft_reset = INREG(RBBM_SOFT_RESET); - - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | - SOFT_RESET_CP | - SOFT_RESET_HI | - SOFT_RESET_SE | - SOFT_RESET_RE | - SOFT_RESET_PP | - SOFT_RESET_E2 | - SOFT_RESET_RB | - SOFT_RESET_HDP); - INREG(RBBM_SOFT_RESET); - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) - ~(SOFT_RESET_CP | - SOFT_RESET_HI | - SOFT_RESET_SE | - SOFT_RESET_RE | - SOFT_RESET_PP | - SOFT_RESET_E2 | - SOFT_RESET_RB | - SOFT_RESET_HDP)); - INREG(RBBM_SOFT_RESET); - - OUTPLL(MCLK_CNTL, mclk_cntl); - OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); - - return; -} -#endif -static void radeon_engine_restore( void ) -{ -#ifndef RAGE128 - int pitch64; - uint32_t xres,yres,bpp; - radeon_fifo_wait(1); - xres = radeon_get_xres(); - yres = radeon_get_yres(); - bpp = radeon_vid_get_dbpp(); - /* turn of all automatic flushing - we'll do it all */ - OUTREG(RB2D_DSTCACHE_MODE, 0); - - pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; - - radeon_fifo_wait(1); - OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | - (pitch64 << 22)); - - radeon_fifo_wait(1); -#if HAVE_BIGENDIAN - OUTREGP(DP_DATATYPE, - HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); -#else - OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); -#endif - - radeon_fifo_wait(1); - OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX - | DEFAULT_SC_BOTTOM_MAX)); - radeon_fifo_wait(1); - OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) - | GMC_BRUSH_SOLID_COLOR - | GMC_SRC_DATATYPE_COLOR)); - - radeon_fifo_wait(7); - OUTREG(DST_LINE_START, 0); - OUTREG(DST_LINE_END, 0); - OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); - OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); - OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); - OUTREG(DP_SRC_BKGD_CLR, 0x00000000); - OUTREG(DP_WRITE_MASK, 0xffffffff); - - radeon_engine_idle(); -#endif -} -#ifdef RAGE128 -static void _radeon_fifo_wait (unsigned entries) -{ - unsigned i; - - for(;;) - { - for (i=0; i<2000000; i++) - if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) - return; - radeon_engine_reset(); - radeon_engine_restore(); - } -} - -static void _radeon_engine_idle ( void ) -{ - unsigned i; - - /* ensure FIFO is empty before waiting for idle */ - radeon_fifo_wait (64); - for(;;) - { - for (i=0; i<2000000; i++) { - if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { - radeon_engine_flush (); - return; - } - } - radeon_engine_reset(); - radeon_engine_restore(); - } -} -#else -static void _radeon_fifo_wait (unsigned entries) -{ - unsigned i; - - for(;;) - { - for (i=0; i<2000000; i++) - if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) - return; - radeon_engine_reset(); - radeon_engine_restore(); - } -} -static void _radeon_engine_idle ( void ) -{ - int i; - - /* ensure FIFO is empty before waiting for idle */ - radeon_fifo_wait (64); - for(;;) - { - for (i=0; i<2000000; i++) { - if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { - radeon_engine_flush (); - return; - } - } - radeon_engine_reset(); - radeon_engine_restore(); - } -} -#endif - -#ifndef RAGE128 -/* Reference color space transform data */ -typedef struct tagREF_TRANSFORM -{ - float RefLuma; - float RefRCb; - float RefRCr; - float RefGCb; - float RefGCr; - float RefBCb; - float RefBCr; -} REF_TRANSFORM; - -/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ -static const REF_TRANSFORM trans[2] = -{ - {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ - {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ -}; -/**************************************************************************** - * SetTransform * - * Function: Calculates and sets color space transform from supplied * - * reference transform, gamma, brightness, contrast, hue and * - * saturation. * - * Inputs: bright - brightness * - * cont - contrast * - * sat - saturation * - * hue - hue * - * red_intensity - intense of red component * - * green_intensity - intense of green component * - * blue_intensity - intense of blue component * - * ref - index to the table of refernce transforms * - * Outputs: NONE * - ****************************************************************************/ - -static void radeon_set_transform(float bright, float cont, float sat, - float hue, float red_intensity, - float green_intensity,float blue_intensity, - unsigned ref) -{ - float OvHueSin, OvHueCos; - float CAdjLuma, CAdjOff; - float RedAdj,GreenAdj,BlueAdj; - float CAdjRCb, CAdjRCr; - float CAdjGCb, CAdjGCr; - float CAdjBCb, CAdjBCr; - float OvLuma, OvROff, OvGOff, OvBOff; - float OvRCb, OvRCr; - float OvGCb, OvGCr; - float OvBCb, OvBCr; - float Loff = 64.0; - float Coff = 512.0f; - - uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; - uint32_t dwOvRCb, dwOvRCr; - uint32_t dwOvGCb, dwOvGCr; - uint32_t dwOvBCb, dwOvBCr; - - if (ref >= 2) return; - - OvHueSin = sin((double)hue); - OvHueCos = cos((double)hue); - - CAdjLuma = cont * trans[ref].RefLuma; - CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; - RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; - GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; - BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; - - CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; - CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; - CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); - CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); - CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; - CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; - - OvLuma = CAdjLuma; - OvRCb = CAdjRCb; - OvRCr = CAdjRCr; - OvGCb = CAdjGCb; - OvGCr = CAdjGCr; - OvBCb = CAdjBCb; - OvBCr = CAdjBCr; - OvROff = RedAdj + CAdjOff - - OvLuma * Loff - (OvRCb + OvRCr) * Coff; - OvGOff = GreenAdj + CAdjOff - - OvLuma * Loff - (OvGCb + OvGCr) * Coff; - OvBOff = BlueAdj + CAdjOff - - OvLuma * Loff - (OvBCb + OvBCr) * Coff; - - dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; - dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; - dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; - /* Whatever docs say about R200 having 3.8 format instead of 3.11 - as in Radeon is a lie */ - - dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; - dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; - dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; - dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; - dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; - dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; - dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; - - OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); - OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); - OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); -} - -/* Gamma curve definition */ -typedef struct -{ - unsigned int gammaReg; - unsigned int gammaSlope; - unsigned int gammaOffset; -}GAMMA_SETTINGS; - -/* Recommended gamma curve parameters */ -static const GAMMA_SETTINGS r200_def_gamma[18] = -{ - {OV0_GAMMA_0_F, 0x100, 0x0000}, - {OV0_GAMMA_10_1F, 0x100, 0x0020}, - {OV0_GAMMA_20_3F, 0x100, 0x0040}, - {OV0_GAMMA_40_7F, 0x100, 0x0080}, - {OV0_GAMMA_80_BF, 0x100, 0x0100}, - {OV0_GAMMA_C0_FF, 0x100, 0x0100}, - {OV0_GAMMA_100_13F, 0x100, 0x0200}, - {OV0_GAMMA_140_17F, 0x100, 0x0200}, - {OV0_GAMMA_180_1BF, 0x100, 0x0300}, - {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, - {OV0_GAMMA_200_23F, 0x100, 0x0400}, - {OV0_GAMMA_240_27F, 0x100, 0x0400}, - {OV0_GAMMA_280_2BF, 0x100, 0x0500}, - {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, - {OV0_GAMMA_300_33F, 0x100, 0x0600}, - {OV0_GAMMA_340_37F, 0x100, 0x0600}, - {OV0_GAMMA_380_3BF, 0x100, 0x0700}, - {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} -}; - -static const GAMMA_SETTINGS r100_def_gamma[6] = -{ - {OV0_GAMMA_0_F, 0x100, 0x0000}, - {OV0_GAMMA_10_1F, 0x100, 0x0020}, - {OV0_GAMMA_20_3F, 0x100, 0x0040}, - {OV0_GAMMA_40_7F, 0x100, 0x0080}, - {OV0_GAMMA_380_3BF, 0x100, 0x0100}, - {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} -}; - -static void make_default_gamma_correction( void ) -{ - size_t i; - if((besr.chip_flags & R_100)==R_100|| |