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-rw-r--r--stream/url.c4
-rw-r--r--vidix/sis_regs.h26
2 files changed, 15 insertions, 15 deletions
diff --git a/stream/url.c b/stream/url.c
index c487045904..79a1eba19a 100644
--- a/stream/url.c
+++ b/stream/url.c
@@ -367,7 +367,7 @@ url_escape_string(char *outbuf, const char *inbuf) {
if(unesc) free(unesc);
}
-#ifdef __URL_DEBUG
+#ifdef URL_DEBUG
void
url_debug(const URL_t *url) {
if( url==NULL ) {
@@ -394,4 +394,4 @@ url_debug(const URL_t *url) {
printf("password=%s\n", url->password );
}
}
-#endif //__URL_DEBUG
+#endif /* URL_DEBUG */
diff --git a/vidix/sis_regs.h b/vidix/sis_regs.h
index ca150204c7..a559d0514e 100644
--- a/vidix/sis_regs.h
+++ b/vidix/sis_regs.h
@@ -27,12 +27,12 @@
#define inSISREG(base) INPORT8(base)
#define outSISREG(base,val) OUTPORT8(base, val)
#define orSISREG(base,val) do { \
- unsigned char __Temp = INPORT8(base); \
- outSISREG(base, __Temp | (val)); \
+ unsigned char tmp = INPORT8(base); \
+ outSISREG(base, tmp | (val)); \
} while (0)
#define andSISREG(base,val) do { \
- unsigned char __Temp = INPORT8(base); \
- outSISREG(base, __Temp & (val)); \
+ unsigned char tmp = INPORT8(base); \
+ outSISREG(base, tmp & (val)); \
} while (0)
#define inSISIDXREG(base,idx,var) do { \
@@ -42,22 +42,22 @@
OUTPORT8(base, idx); OUTPORT8((base)+1, val); \
} while (0)
#define orSISIDXREG(base,idx,val) do { \
- unsigned char __Temp; \
+ unsigned char tmp; \
OUTPORT8(base, idx); \
- __Temp = INPORT8((base)+1)|(val); \
- outSISIDXREG(base,idx,__Temp); \
+ tmp = INPORT8((base)+1)|(val); \
+ outSISIDXREG(base,idx,tmp); \
} while (0)
#define andSISIDXREG(base,idx,and) do { \
- unsigned char __Temp; \
+ unsigned char tmp; \
OUTPORT8(base, idx); \
- __Temp = INPORT8((base)+1)&(and); \
- outSISIDXREG(base,idx,__Temp); \
+ tmp = INPORT8((base)+1)&(and); \
+ outSISIDXREG(base,idx,tmp); \
} while (0)
#define setSISIDXREG(base,idx,and,or) do { \
- unsigned char __Temp; \
+ unsigned char tmp; \
OUTPORT8(base, idx); \
- __Temp = (INPORT8((base)+1)&(and))|(or); \
- outSISIDXREG(base,idx,__Temp); \
+ tmp = (INPORT8((base)+1)&(and))|(or); \
+ outSISIDXREG(base,idx,tmp); \
} while (0)
#define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))