updated the ati vidix driver with the one from upstream vidix, it now supports much more GPUs (including all Radeon > 9600 and X series)

git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@23062 b3059339-0415-0410-9bf9-f77b7e298cf2

2 files changed, 2106 insertions, 641 deletions

diff --git a/vidix/radeon.h b/vidix/radeon.h
index 6093356c1b..604e4283a1 100644
--- a/vidix/radeon.h
+++ b/vidix/radeon.h
@@ -148,13 +148,23 @@
 #define	AIC_TLB_DATA				0x01E8
 #define	DAC_CNTL				0x0058
 /* DAC_CNTL bit	constants */
+#	define DAC_RANGE_CNTL_MSK		0x00000003
+#	define DAC_RANGE_PAL			0x00000000
+#	define DAC_RANGE_NTSC			0x00000001
+#	define DAC_RANGE_PS2			0x00000002
+#	define DAC_BLANKING			0x00000004
+#	define DAC_CMP_EN			0x00000008
+#	define DAC_CMP_OUTPUT			0x00000080
 #	define DAC_8BIT_EN			0x00000100
 #	define DAC_4BPP_PIX_ORDER		0x00000200
+#	define DAC_TVO_EN			0x00000400
+#	define DAC_TVO_OVR_EXCL			0x00000800
+#	define DAC_TVO_16BPP_DITH_EN		0x00001000
+#	define DAC_VGA_ADR_EN			(1 << 13)
+#	define DAC_PWDN				(1 << 15)
 #	define DAC_CRC_EN			0x00080000
 #	define DAC_MASK_ALL			(0xff << 24)
-#	define DAC_VGA_ADR_EN			(1 << 13)
 #	define DAC_RANGE_CNTL			(3 << 0)
-#	define DAC_BLANKING			(1 << 2)
 #define	DAC_CNTL2				0x007c
 /* DAC_CNTL2 bit constants */
 #	define DAC2_DAC_CLK_SEL			(1 <<  0)
@@ -191,6 +201,7 @@
 #	define CRTC2_DISP_DIS			(1 << 23)
 #	define CRTC2_EN				(1 << 25)
 #	define CRTC2_DISP_REQ_EN_B		(1 << 26)
+#       define CRTC2_CSYNC_EN			(1 << 27)
 #	define CRTC2_HSYNC_DIS			(1 << 28)
 #	define CRTC2_VSYNC_DIS			(1 << 29)
 #define	MEM_CNTL				0x0140
@@ -284,6 +295,19 @@
 #	define CRTC_DISPLAY_DIS_BYTE		(1 <<  2)
 #define	RB3D_CNTL				0x1C3C
 #define	WAIT_UNTIL				0x1720
+#	define EVENT_CRTC_OFFSET		0x00000001
+#	define EVENT_RE_CRTC_VLINE		0x00000002
+#	define EVENT_FE_CRTC_VLINE		0x00000004
+#	define EVENT_CRTC_VLINE			0x00000008
+#	define EVENT_BM_VIP0_IDLE		0x00000010
+#	define EVENT_BM_VIP1_IDLE		0x00000020
+#	define EVENT_BM_VIP2_IDLE		0x00000040
+#	define EVENT_BM_VIP3_IDLE		0x00000080
+#	define EVENT_BM_VIDCAP_IDLE		0x00000100
+#	define EVENT_BM_GUI_IDLE		0x00000200
+#	define EVENT_CMDFIFO			0x00000400
+#	define EVENT_OV0_FLIP			0x00000800
+#	define EVENT_CMDFIFO_ENTRIES		0x07F00000
 #define	ISYNC_CNTL				0x1724
 #define	RBBM_GUICNTL				0x172C
 #define	RBBM_STATUS				0x0E40
@@ -563,7 +587,7 @@
 #	define SCALER_SOURCE_UNK7		0x00000F00L /* 16BPP_ARGB4444 */
 #	define SCALER_ADAPTIVE_DEINT		0x00001000L
 #	define R200_SCALER_TEMPORAL_DEINT	0x00002000L
-#	define SCALER_UNKNOWN_FLAG1		0x00004000L /* ??? */
+#	define SCALER_USE_OV1			0x00004000L /* Use/force Ov1 instead of Ov0 */
 #	define SCALER_SMART_SWITCH		0x00008000L
 #ifdef RAGE128
 #	define SCALER_BURST_PER_PLANE		0x00ff0000L
@@ -574,9 +598,7 @@
 #	define SCALER_UNKNOWN_FLAG3		0x02000000L /* ??? */
 #	define SCALER_UNKNOWN_FLAG4		0x04000000L /* ??? */
 #	define SCALER_DIS_LIMIT			0x08000000L
-#ifdef RAGE128
 #	define SCALER_PRG_LOAD_START		0x10000000L
-#endif
 #	define SCALER_INT_EMU			0x20000000L
 #	define SCALER_ENABLE			0x40000000L
 #	define SCALER_SOFT_RESET		0x80000000L
@@ -599,32 +621,32 @@
 #define	OV0_VID_BUF0_BASE_ADRS			0x0440
 #	define VIF_BUF0_PITCH_SEL		0x00000001L
 #	define VIF_BUF0_TILE_ADRS		0x00000002L
-#	define VIF_BUF0_BASE_ADRS_MASK		0x03fffff0L
+#	define VIF_BUF0_BASE_ADRS_MASK		0x0ffffff0L
 #	define VIF_BUF0_1ST_LINE_LSBS_MASK	0x48000000L
 #define	OV0_VID_BUF1_BASE_ADRS			0x0444
 #	define VIF_BUF1_PITCH_SEL		0x00000001L
 #	define VIF_BUF1_TILE_ADRS		0x00000002L
-#	define VIF_BUF1_BASE_ADRS_MASK		0x03fffff0L
+#	define VIF_BUF1_BASE_ADRS_MASK		0x0ffffff0L
 #	define VIF_BUF1_1ST_LINE_LSBS_MASK	0x48000000L
 #define	OV0_VID_BUF2_BASE_ADRS			0x0448
 #	define VIF_BUF2_PITCH_SEL		0x00000001L
 #	define VIF_BUF2_TILE_ADRS		0x00000002L
-#	define VIF_BUF2_BASE_ADRS_MASK		0x03fffff0L
+#	define VIF_BUF2_BASE_ADRS_MASK		0x0ffffff0L
 #	define VIF_BUF2_1ST_LINE_LSBS_MASK	0x48000000L
 #define	OV0_VID_BUF3_BASE_ADRS			0x044C
 #	define VIF_BUF3_PITCH_SEL		0x00000001L
 #	define VIF_BUF3_TILE_ADRS		0x00000002L
-#	define VIF_BUF3_BASE_ADRS_MASK		0x03fffff0L
+#	define VIF_BUF3_BASE_ADRS_MASK		0x0ffffff0L
 #	define VIF_BUF3_1ST_LINE_LSBS_MASK	0x48000000L
 #define	OV0_VID_BUF4_BASE_ADRS			0x0450
 #	define VIF_BUF4_PITCH_SEL		0x00000001L
 #	define VIF_BUF4_TILE_ADRS		0x00000002L
-#	define VIF_BUF4_BASE_ADRS_MASK		0x03fffff0L
+#	define VIF_BUF4_BASE_ADRS_MASK		0x0ffffff0L
 #	define VIF_BUF4_1ST_LINE_LSBS_MASK	0x48000000L
 #define	OV0_VID_BUF5_BASE_ADRS			0x0454
 #	define VIF_BUF5_PITCH_SEL		0x00000001L
 #	define VIF_BUF5_TILE_ADRS		0x00000002L
-#	define VIF_BUF5_BASE_ADRS_MASK		0x03fffff0L
+#	define VIF_BUF5_BASE_ADRS_MASK		0x0ffffff0L
 #	define VIF_BUF5_1ST_LINE_LSBS_MASK	0x48000000L
 #define	OV0_VID_BUF_PITCH0_VALUE		0x0460
 #define	OV0_VID_BUF_PITCH1_VALUE		0x0464
@@ -735,6 +757,18 @@
 #	define CMP_MIX_OR			0x00000000L
 #	define CMP_MIX_AND			0x00000100L
 #define	OV0_TEST				0x04F8
+#	define OV0_SCALER_Y2R_DISABLE		0x00000001L
+#	define OV0_SUBPIC_ONLY			0x00000008L
+#	define OV0_EXTENSE			0x00000010L
+#	define OV0_SWAP_UV			0x00000020L
+#define OV0_COL_CONV				0x04FC
+#	define OV0_CB_TO_B			0x0000007FL
+#	define OV0_CB_TO_G			0x0000FF00L
+#	define OV0_CR_TO_G			0x00FF0000L
+#	define OV0_CR_TO_R			0x7F000000L
+#	define OV0_NEW_COL_CONV			0x80000000L
+#define OV1_Y_X_START				0x0600
+#define OV1_Y_X_END				0x0604
 #define	OV0_LIN_TRANS_A				0x0D20
 #define	OV0_LIN_TRANS_B				0x0D24
 #define	OV0_LIN_TRANS_C				0x0D28
@@ -774,9 +808,25 @@
 #define IDCT_CONTROL				0x1FBC
 
 #define SE_MC_SRC2_CNTL				0x19D4
+#	define SECONDARY_SCALE_HACC		0x00001FFFL
+#	define SECONDARY_SCALE_VACC		0x0FFF0000L
+#	define SECONDARY_SCALE_PICTH_ADJ	0xC0000000L
 #define SE_MC_SRC1_CNTL				0x19D8
+#	define SCALE_HACC			0x00001FFFL
+#	define SCALE_VACC			0x0FFF0000L
+#	define IDCT_EN				0x10000000L
+#	define SECONDARY_TEX_EN			0x20000000L
+#	define SCALE_PICTH_ADJ			0xC0000000L
 #define SE_MC_DST_CNTL				0x19DC
+#	define DST_Y				0x00003FFFL
+#	define DST_X				0x3FFF0000L
+#	define DST_PITCH_ADJ			0xC0000000L
 #define SE_MC_CNTL_START			0x19E0
+#	define SCALE_OFFSET_PTR			0x0000000FL
+#	define DST_OFFSET			0x00FFFFF0L
+#	define ALPHA_EN				0x01000000L
+#	define SECONDARY_OFFSET_PTR		0x1E000000L
+#	define MC_DST_HEIGHT_WIDTH		0xE0000000L
 #ifndef RAGE128
 #define SE_MC_BUF_BASE				0x19E4
 #define PP_MC_CONTEXT				0x19E8
@@ -817,6 +867,7 @@
 #define CP_CSQ_CNTL				0x0740
 #define SCRATCH_UMSK				0x0770
 #define SCRATCH_ADDR				0x0774
+#ifndef RAGE128
 #define DMA_GUI_TABLE_ADDR			0x0780
 #	define DMA_GUI_COMMAND__BYTE_COUNT_MASK	0x001fffff
 #	define DMA_GUI_COMMAND__INTDIS		0x40000000
@@ -832,6 +883,7 @@
 #define DMA_VID_COMMAND				0x07AC
 #define DMA_VID_STATUS				0x07B0
 #define DMA_VID_ACT_DSCRPTR			0x07B4
+#endif
 #define CP_ME_CNTL				0x07D0
 #define CP_ME_RAM_ADDR				0x07D4
 #define CP_ME_RAM_RADDR				0x07D8
@@ -1031,6 +1083,20 @@
 #ifdef RAGE128
 #define GUI_STAT				0x1740
 #	define GUI_FIFOCNT_MASK			0x0fff
+#	define PM4_BUSY				(1 << 16)
+#	define MICRO_BUSY			(1 << 17)
+#	define FPU_BUSY				(1 << 18)
+#	define VC_BUSY				(1 << 19)
+#	define IDCT_BUSY			(1 << 20)
+#	define ENG_EV_BUSY			(1 << 21)
+#	define SETUP_BUSY			(1 << 22)
+#	define EDGE_WALK_BUSY			(1 << 23)
+#	define ADDRESSING_BUSY			(1 << 24)
+#	define ENG_3D_BUSY			(1 << 25)
+#	define ENG_2D_SM_BUSY			(1 << 26)
+#	define ENG_2D_BUSY			(1 << 27)
+#	define GUI_WB_BUSY			(1 << 28)
+#	define CACHE_BUSY			(1 << 29)
 #	define GUI_ACTIVE			(1 << 31)
 #endif
 #define	SRC_CLUT_ADDRESS			0x1780
@@ -1211,7 +1277,7 @@
 #define	RB2D_DSTCACHE_CTLSTAT			0x342C
 #define	RB2D_DSTCACHE_MODE			0x3428
 
-#define	BASE_CODE				0x0f0b
+#define	BASE_CODE				0x0f0b/*0x0f08*/
 #define	RADEON_BIOS_0_SCRATCH			0x0010
 #define	RADEON_BIOS_1_SCRATCH			0x0014
 #define	RADEON_BIOS_2_SCRATCH			0x0018
@@ -1303,6 +1369,7 @@
 #define	PPLL_POST3_DIV_MASK		0x00070000
 
 /* BUS MASTERING */
+#ifdef RAGE128
 #define BM_FRAME_BUF_OFFSET			0xA00
 #define BM_SYSTEM_MEM_ADDR			0xA04
 #define BM_COMMAND				0xA08
@@ -1338,7 +1405,8 @@
 #define BM_VIDCAP_BUF2				0xA68
 #define BM_VIDCAP_ACTIVE			0xA6c
 #define BM_GUI					0xA80
-
+#define BM_ABORT				0xA88
+#endif
 /* RAGE	THEATER	REGISTERS */
 
 #define DMA_VIPH0_COMMAND			0x0A00
diff --git a/vidix/radeon_vid.c b/vidix/radeon_vid.c
index 6a0436ee6e..6891bfe8ef 100644
--- a/vidix/radeon_vid.c
+++ b/vidix/radeon_vid.c
@@ -15,6 +15,7 @@
 #include <string.h>
 #include <math.h>
 #include <inttypes.h>
+#include <sys/mman.h>
 
 #include "config.h"
 #include "libavutil/common.h"
@@ -27,8 +28,9 @@
 #include "dha.h"
 #include "radeon.h"
 
-#ifdef HAVE_X11
+#if !defined(RAGE128) && defined(HAVE_X11)
 #include <X11/Xlib.h>
+static uint32_t firegl_shift = 0;
 #endif
 
 #ifdef RAGE128
@@ -36,22 +38,26 @@
 #define X_ADJUST 0
 #else
 #define RADEON_MSG "[radeon]"
-#define X_ADJUST (is_shift_required ? 8 : 0)
+#define X_ADJUST (((besr.chip_flags&R_OVL_SHIFT)==R_OVL_SHIFT)?8:0)
 #ifndef RADEON
 #define RADEON
 #endif
 #endif
 
-static int __verbose = 0;
-#ifdef RADEON
-static int is_shift_required = 0;
-#endif
+#define RADEON_ASSERT(msg) printf(RADEON_MSG"################# FATAL:"msg);
 
+#define VERBOSE_LEVEL 0
+static int __verbose = 0;
 typedef struct bes_registers_s
 {
   /* base address of yuv framebuffer */
   uint32_t yuv_base;
   uint32_t fourcc;
+  uint32_t surf_id;
+  int load_prg_start;
+  int horz_pick_nearest;
+  int vert_pick_nearest;
+  int swap_uv; /* for direct support of bgr fourccs */
   uint32_t dest_bpp;
   /* YUV BES registers */
   uint32_t reg_load_cntl;
@@ -81,6 +87,7 @@ typedef struct bes_registers_s
   uint32_t exclusive_horz;
   uint32_t auto_flip_cntl;
   uint32_t filter_cntl;
+  uint32_t four_tap_coeff[5];
   uint32_t key_cntl;
   uint32_t test;
   /* Configurable stuff */
@@ -93,10 +100,12 @@ typedef struct bes_registers_s
   uint32_t graphics_key_clr;
   uint32_t graphics_key_msk;
   uint32_t ckey_cntl;
+  uint32_t merge_cntl;
   
   int deinterlace_on;
   uint32_t deinterlace_pattern;
   
+  unsigned chip_flags;
 } bes_registers_t;
 
 typedef struct video_registers_s
@@ -107,9 +116,6 @@ typedef struct video_registers_s
 }video_registers_t;
 
 static bes_registers_t besr;
-#ifndef RAGE128
-static int RadeonFamily=100;
-#endif
 #define DECLARE_VREG(name) { #name, name, 0 }
 static video_registers_t vregs[] = 
 {
@@ -120,6 +126,8 @@ static video_registers_t vregs[] =
   DECLARE_VREG(VIPPAD1_Y),
   DECLARE_VREG(OV0_Y_X_START),
   DECLARE_VREG(OV0_Y_X_END),
+  DECLARE_VREG(OV1_Y_X_START),
+  DECLARE_VREG(OV1_Y_X_END),
   DECLARE_VREG(OV0_PIPELINE_CNTL),
   DECLARE_VREG(OV0_EXCLUSIVE_HORZ),
   DECLARE_VREG(OV0_EXCLUSIVE_VERT),
@@ -204,47 +212,380 @@ static video_registers_t vregs[] =
   DECLARE_VREG(IDCT_AUTH_CONTROL),
   DECLARE_VREG(IDCT_AUTH),
   DECLARE_VREG(IDCT_CONTROL),
-  DECLARE_VREG(CONFIG_CNTL)
+#ifdef RAGE128
+  DECLARE_VREG(BM_FRAME_BUF_OFFSET),
+  DECLARE_VREG(BM_SYSTEM_MEM_ADDR),
+  DECLARE_VREG(BM_COMMAND),
+  DECLARE_VREG(BM_STATUS),
+  DECLARE_VREG(BM_QUEUE_STATUS),
+  DECLARE_VREG(BM_QUEUE_FREE_STATUS),
+  DECLARE_VREG(BM_CHUNK_0_VAL),
+  DECLARE_VREG(BM_CHUNK_1_VAL),
+  DECLARE_VREG(BM_VIP0_BUF),
+  DECLARE_VREG(BM_VIP0_ACTIVE),
+  DECLARE_VREG(BM_VIP1_BUF),
+  DECLARE_VREG(BM_VIP1_ACTIVE),
+  DECLARE_VREG(BM_VIP2_BUF),
+  DECLARE_VREG(BM_VIP2_ACTIVE),
+  DECLARE_VREG(BM_VIP3_BUF),
+  DECLARE_VREG(BM_VIP3_ACTIVE),
+  DECLARE_VREG(BM_VIDCAP_BUF0),
+  DECLARE_VREG(BM_VIDCAP_BUF1),
+  DECLARE_VREG(BM_VIDCAP_BUF2),
+  DECLARE_VREG(BM_VIDCAP_ACTIVE),
+  DECLARE_VREG(BM_GUI),
+  DECLARE_VREG(BM_ABORT)
+#else
+  DECLARE_VREG(DMA_GUI_TABLE_ADDR),
+  DECLARE_VREG(DMA_GUI_SRC_ADDR),
+  DECLARE_VREG(DMA_GUI_DST_ADDR),
+  DECLARE_VREG(DMA_GUI_COMMAND),
+  DECLARE_VREG(DMA_GUI_STATUS),
+  DECLARE_VREG(DMA_GUI_ACT_DSCRPTR),
+  DECLARE_VREG(DMA_VID_SRC_ADDR),
+  DECLARE_VREG(DMA_VID_DST_ADDR),
+  DECLARE_VREG(DMA_VID_COMMAND),
+  DECLARE_VREG(DMA_VID_STATUS),
+  DECLARE_VREG(DMA_VID_ACT_DSCRPTR),
+#endif
 };
 
-#ifdef HAVE_X11
-static uint32_t firegl_shift = 0;
+#define R_FAMILY	0x000000FF
+#define R_100		0x00000001
+#define R_120		0x00000002
+#define R_150		0x00000003
+#define R_200		0x00000004
+#define R_250		0x00000005
+#define R_280		0x00000006
+#define R_300		0x00000007
+#define R_350		0x00000008
+#define R_370		0x00000010
+#define R_380		0x00000020
+#define R_420		0x00000040
+#define R_430		0x00000080
+#define R_480		0x00000100
+#define R_520		0x00000200
+#define R_530		0x00000400
+#define R_580		0x00000800
+#define R_OVL_SHIFT	0x01000000
+#define R_INTEGRATED	0x02000000
+#define R_PCIE		0x04000000
+
+typedef struct ati_card_ids_s
+{
+    unsigned short id;
+    unsigned flags;
+}ati_card_ids_t;
+
+static const ati_card_ids_t ati_card_ids[] = 
+{
+#ifdef RAGE128
+ /*
+    This driver should be compatible with Rage128 (pro) chips.
+    (include adaptive deinterlacing!!!).
+    Moreover: the same logic can be used with Mach64 chips.
+    (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility).
+    but they are incompatible by i/o ports. So if enthusiasts will want
+    then they can redefine OUTREG and INREG macros and redefine OV0_*
+    constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY
+    fourccs (422 and 420 formats only).
+  */
+/* Rage128 Pro GL */
+ { DEVICE_ATI_RAGE_128_PA_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PB_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PC_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PD_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PE_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PF_PRO, 0 },
+/* Rage128 Pro VR */
+ { DEVICE_ATI_RAGE_128_PG_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PH_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PI_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PJ_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PK_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PL_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PM_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PN_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PO_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PP_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PQ_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PR_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PS_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PT_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PU_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PV_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PW_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PX_PRO, 0 },
+/* Rage128 GL */
+ { DEVICE_ATI_RAGE_128_RE_SG, 0 },
+ { DEVICE_ATI_RAGE_128_RF_SG, 0 },
+ { DEVICE_ATI_RAGE_128_RG, 0 },
+ { DEVICE_ATI_RAGE_128_RK_VR, 0 },
+ { DEVICE_ATI_RAGE_128_RL_VR, 0 },
+ { DEVICE_ATI_RAGE_128_SE_4X, 0 },
+ { DEVICE_ATI_RAGE_128_SF_4X, 0 },
+ { DEVICE_ATI_RAGE_128_SG_4X, 0 },
+ { DEVICE_ATI_RAGE_128_SH, 0 },
+ { DEVICE_ATI_RAGE_128_SK_4X, 0 },
+ { DEVICE_ATI_RAGE_128_SL_4X, 0 },
+ { DEVICE_ATI_RAGE_128_SM_4X, 0 },
+ { DEVICE_ATI_RAGE_128_4X, 0 },
+ { DEVICE_ATI_RAGE_128_PRO, 0 },
+ { DEVICE_ATI_RAGE_128_PRO2, 0 },
+ { DEVICE_ATI_RAGE_128_PRO3, 0 },
+/* these seem to be based on rage 128 instead of mach64 */
+ { DEVICE_ATI_RAGE_MOBILITY_M3, 0 },
+ { DEVICE_ATI_RAGE_MOBILITY_M32, 0 },
+#else
+/* Radeon1 (indeed: Rage 256 Pro ;) */
+ { DEVICE_ATI_RADEON_R100_QD,		R_100|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_R100_QE,		R_100|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_R100_QF,		R_100|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_R100_QG,		R_100|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_IGP_320,		R_150|R_OVL_SHIFT|R_INTEGRATED },
+ { DEVICE_ATI_RADEON_MOBILITY_U1,	R_150|R_OVL_SHIFT|R_INTEGRATED },
+ { DEVICE_ATI_RADEON_RV100_QY,		R_120|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_RV100_QZ,		R_120|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_MOBILITY_M7,	R_150|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_RV200_LX,		R_150|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_MOBILITY_M6,	R_120|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_MOBILITY_M62,	R_120|R_OVL_SHIFT },
+/* Radeon2 (indeed: Rage 512 Pro ;) */
+ { DEVICE_ATI_R200_BB_RADEON,		R_200 },
+ { DEVICE_ATI_R200_BC_RADEON,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QH,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QI,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QJ,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QK,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QL,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QM,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QN,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QO,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QH2,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QI2,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QJ2,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QK2,		R_200 },
+ { DEVICE_ATI_RADEON_R200_QL2,		R_200 },
+ { DEVICE_ATI_RADEON_RV200_QW,		R_150|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_RV200_QX,		R_150|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_IGP330_340_350,R_200|R_INTEGRATED },
+ { DEVICE_ATI_RADEON_IGP_330M_340M_350M,R_200|R_INTEGRATED },
+ { DEVICE_ATI_RADEON_RV250_IG,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_7000_IGP,		R_250|R_OVL_SHIFT|R_INTEGRATED },
+ { DEVICE_ATI_RADEON_MOBILITY_7000,	R_250|R_OVL_SHIFT|R_INTEGRATED },
+ { DEVICE_ATI_RADEON_RV250_ID,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_RV250_IE,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_RV250_IF,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_RV250_IG,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_R250_LD,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_R250_LE,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_R250_MOBILITY,	R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_R250_LG,		R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RV250_RADEON_9000,	R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RADEON_RV250_RADEON2,	R_250|R_OVL_SHIFT },
+ { DEVICE_ATI_RV280_RADEON_9200,	R_280 },
+ { DEVICE_ATI_RV280_RADEON_92002,	R_280 },
+ { DEVICE_ATI_RV280_RADEON_92003,	R_280 },
+ { DEVICE_ATI_RV280_RADEON_92004,	R_280 },
+ { DEVICE_ATI_RV280_RADEON_92005,	R_280 },
+ { DEVICE_ATI_RV280_RADEON_92006,	R_280 },
+ { DEVICE_ATI_RV280_RADEON_92007,	R_280 },
+ { DEVICE_ATI_M9_5C61_RADEON,		R_280 },
+ { DEVICE_ATI_M9_5C63_RADEON,		R_280 },
+/* Radeon3 (indeed: Rage 1024 Pro ;) */
+ { DEVICE_ATI_R300_AG_FIREGL,		R_300 },
+ { DEVICE_ATI_RADEON_R300_ND,		R_300 },
+ { DEVICE_ATI_RADEON_R300_NE,		R_300 },
+ { DEVICE_ATI_RADEON_R300_NG,		R_300 },
+ { DEVICE_ATI_R300_AD_RADEON,		R_300 },
+ { DEVICE_ATI_R300_AE_RADEON,		R_300 },
+ { DEVICE_ATI_R300_AF_RADEON,		R_300 },
+ { DEVICE_ATI_RADEON_9100_IGP2,		R_300|R_OVL_SHIFT|R_INTEGRATED },
+ { DEVICE_ATI_RS300M_AGP_RADEON,	R_300|R_INTEGRATED },
+ { DEVICE_ATI_R350_AH_RADEON,		R_350 },
+ { DEVICE_ATI_R350_AI_RADEON,		R_350 },
+ { DEVICE_ATI_R350_AJ_RADEON,		R_350 },
+ { DEVICE_ATI_R350_AK_FIRE,		R_350 },
+ { DEVICE_ATI_RADEON_R350_RADEON2,	R_350 },
+ { DEVICE_ATI_RADEON_R350_RADEON3,	R_350 },
+ { DEVICE_ATI_RV350_NJ_RADEON,		R_350 },
+ { DEVICE_ATI_R350_NK_FIRE,		R_350 },
+ { DEVICE_ATI_RV350_AP_RADEON,		R_350 },
+ { DEVICE_ATI_RV350_AQ_RADEON,		R_350 },
+ { DEVICE_ATI_RV350_AR_RADEON,		R_350 },
+ { DEVICE_ATI_RV350_AS_RADEON,		R_350 },
+ { DEVICE_ATI_RV350_AT_FIRE,		R_350 },
+ { DEVICE_ATI_RV350_AU_FIRE,		R_350 },
+ { DEVICE_ATI_RV350_AV_FIRE,		R_350 },
+ { DEVICE_ATI_RV350_AW_FIRE,		R_350 },
+ { DEVICE_ATI_RV350_MOBILITY_RADEON,	R_350 },
+ { DEVICE_ATI_RV350_NF_RADEON,		R_300 },
+ { DEVICE_ATI_RV350_NJ_RADEON,		R_300 },
+ { DEVICE_ATI_RV350_AS_RADEON2,		R_350 },
+ { DEVICE_ATI_M10_NQ_RADEON,		R_350 },
+ { DEVICE_ATI_M10_NQ_RADEON2,		R_350 },
+ { DEVICE_ATI_RV350_MOBILITY_RADEON2,	R_350 },
+ { DEVICE_ATI_M10_NS_RADEON,		R_350 },
+ { DEVICE_ATI_M10_NT_FIREGL,		R_350 },
+ { DEVICE_ATI_M11_NV_FIREGL,		R_350 },
+ { DEVICE_ATI_RV370_5B60_RADEON,	R_370|R_PCIE  },
+ { DEVICE_ATI_RV370_SAPPHIRE_X550,	R_370 },
+ { DEVICE_ATI_RV370_5B64_FIREGL,	R_370|R_PCIE  },
+ { DEVICE_ATI_RV370_5B65_FIREGL,	R_370|R_PCIE  },
+ { DEVICE_ATI_M24_1P_RADEON,		R_370  },
+ { DEVICE_ATI_M22_RADEON_MOBILITY,	R_370  },
+ { DEVICE_ATI_M24_1T_FIREGL,		R_370  },
+ { DEVICE_ATI_M24_RADEON_MOBILITY,	R_370  },
+ { DEVICE_ATI_RV370_RADEON_X300SE,	R_370  },
+ { DEVICE_ATI_RV370_SECONDARY_SAPPHIRE,	R_370  },
+ { DEVICE_ATI_RV370_5B64_FIREGL2,	R_370  },
+ { DEVICE_ATI_RV380_0X3E50_RADEON,	R_380|R_PCIE  },
+ { DEVICE_ATI_RV380_0X3E54_FIREGL,	R_380|R_PCIE  },
+ { DEVICE_ATI_RV380_RADEON_X600,	R_380|R_PCIE  },
+ { DEVICE_ATI_RV380_RADEON_X6002,	R_380  },
+ { DEVICE_ATI_RV380_RADEON_X6003,	R_380  },
+ { DEVICE_ATI_RV410_FIREGL_V5000,	R_420  },
+ { DEVICE_ATI_RV410_FIREGL_V3300,	R_420  },
+ { DEVICE_ATI_RV410_RADEON_X700XT,	R_420  },
+ { DEVICE_ATI_RV410_RADEON_X700,	R_420|R_PCIE  },
+ { DEVICE_ATI_RV410_RADEON_X700SE,	R_420  },
+ { DEVICE_ATI_RV410_RADEON_X7002,	R_420|R_PCIE  },
+ { DEVICE_ATI_RV410_RADEON_X7003,	R_420  },
+ { DEVICE_ATI_RV410_RADEON_X7004,	R_420|R_PCIE  },
+ { DEVICE_ATI_RV410_RADEON_X7005,	R_420|R_PCIE  },
+ { DEVICE_ATI_M26_MOBILITY_FIREGL,	R_420  },
+ { DEVICE_ATI_M26_MOBILITY_FIREGL2,	R_420  },
+ { DEVICE_ATI_M26_RADEON_MOBILITY,	R_420  },
+ { DEVICE_ATI_M26_RADEON_MOBILITY2,	R_420  },
+ { DEVICE_ATI_RADEON_MOBILITY_X700,	R_420  },
+ { DEVICE_ATI_R420_JH_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_JI_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_JJ_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_JK_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_JL_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_JM_FIREGL,		R_420|R_PCIE  },
+ { DEVICE_ATI_M18_JN_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_JP_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_RADEON_X800,		R_420|R_PCIE  },
+ { DEVICE_ATI_R420_RADEON_X8002,	R_420|R_PCIE  },
+ { DEVICE_ATI_R420_RADEON_X8003,	R_420|R_PCIE  },
+ { DEVICE_ATI_R420_RADEON_X8004,	R_420|R_PCIE  },
+ { DEVICE_ATI_R420_RADEON_X8005,	R_420|R_PCIE  },
+ { DEVICE_ATI_R420_JM_FIREGL,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_5F57_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_5F57_RADEON2,	R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UH_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UI_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UJ_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UK_RADEON,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_FIRE_GL,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UQ_FIREGL,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UR_FIREGL,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UT_FIREGL,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423_UI_RADEON2,		R_420|R_PCIE  },
+ { DEVICE_ATI_R423GL_SE_ATI_FIREGL,	R_420|R_PCIE  },
+ { DEVICE_ATI_R423_RADEON_X800XT,	R_420|R_PCIE  },
+ { DEVICE_ATI_RADEON_R423_UK,		R_420|R_PCIE  },
+ { DEVICE_ATI_M28_RADEON_MOBILITY,	R_420  },
+ { DEVICE_ATI_M28_MOBILITY_FIREGL,	R_420  },
+ { DEVICE_ATI_MOBILITY_RADEON_X800,	R_420  },
+ { DEVICE_ATI_R430_RADEON_X800,		R_430|R_PCIE  },
+ { DEVICE_ATI_R430_RADEON_X8002,	R_430|R_PCIE  },
+ { DEVICE_ATI_R430_RADEON_X8003,	R_430|R_PCIE  },
+ { DEVICE_ATI_R430_RADEON_X8004,	R_430|R_PCIE  },
+ { DEVICE_ATI_R480_RADEON_X800,		R_480  },
+ { DEVICE_ATI_R480_RADEON_X8002,	R_480  },
+ { DEVICE_ATI_R480_RADEON_X850XT,	R_480  },
+ { DEVICE_ATI_R480_RADEON_X850PRO,	R_480  },
+ { DEVICE_ATI_R481_RADEON_X850XT_PE,	R_480|R_PCIE  },
+ { DEVICE_ATI_R480_RADEON_X850XT2,	R_480  },
+ { DEVICE_ATI_R480_RADEON_X850PRO2,	R_480  },
+ { DEVICE_ATI_R481_RADEON_X850XT_PE2,	R_480|R_PCIE  },
+ { DEVICE_ATI_R480_RADEON_X850XT3,	R_480|R_PCIE  },
+ { DEVICE_ATI_R480_RADEON_X850XT4,	R_480|R_PCIE  },
+ { DEVICE_ATI_R480_RADEON_X850XT5,	R_480|R_PCIE  },
+ { DEVICE_ATI_R480_RADEON_X850XT6,	R_480|R_PCIE  },
+ { DEVICE_ATI_R520_FIREGL,		R_520  },
+ { DEVICE_ATI_R520_GL_ATI,		R_520  },
+ { DEVICE_ATI_R520_GL_ATI2,		R_520  },
+ { DEVICE_ATI_R520_RADEON_X1800,	R_520  },
+ { DEVICE_ATI_R520_RADEON_X18002,	R_520  },
+ { DEVICE_ATI_R520_RADEON_X18003,	R_520  },
+ { DEVICE_ATI_R520_RADEON_X18004,	R_520  },
+ { DEVICE_ATI_R520_RADEON_X18005,	R_520  },
+ { DEVICE_ATI_R520_RADEON_X18006,	R_520  },
+ { DEVICE_ATI_R520_RADEON_X18007,	R_520  },
+ { DEVICE_ATI_M58_RADEON_MOBILITY,	R_520  },
+ { DEVICE_ATI_M58_RADEON_MOBILITY2,	R_520  },
+ { DEVICE_ATI_M58_MOBILITY_FIREGL,	R_520  },
+ { DEVICE_ATI_M58_MOBILITY_FIREGL2,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X1600,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X1300,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X13002,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X13003,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X13004,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X13005,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X13006,	R_520  },
+ { DEVICE_ATI_RV515_RADEON_X13007,	R_520  },
+ { DEVICE_ATI_RV515_GL_ATI,		R_520  },
+ { DEVICE_ATI_RV515_GL_ATI2,		R_520  },
+ { DEVICE_ATI_RADEON_MOBILITY_X1400,	R_520  },
+ { DEVICE_ATI_M52_ATI_MOBILITY,		R_520  },
+ { DEVICE_ATI_M52_ATI_MOBILITY2,	R_520  },
+ { DEVICE_ATI_M52_ATI_MOBILITY3,	R_520  },
+ { DEVICE_ATI_M52_ATI_MOBILITY4,	R_520  },
+ { DEVICE_ATI_RV516_RADEON_X1300,	R_520  },
+ { DEVICE_ATI_RV516_RADEON_X13002,	R_520  },
+ { DEVICE_ATI_RV516_XT_RADEON,		R_520  },
+ { DEVICE_ATI_RV516_XT_RADEON2,		R_520  },
+ { DEVICE_ATI_RV530_RADEON_X1600,	R_520  },
+ { DEVICE_ATI_RV530_RADEON_X16002,	R_520  },
+ { DEVICE_ATI_M56GL_ATI_MOBILITY,	R_520  },
+ { DEVICE_ATI_M56P_RADEON_MOBILITY,	R_520  },
+ { DEVICE_ATI_M66_P_ATI_MOBILITY,	R_520  },
+ { DEVICE_ATI_M66_XT_ATI_MOBILITY,	R_520  },
+ { DEVICE_ATI_RV530LE_RADEON_X1600,	R_520  },
+ { DEVICE_ATI_RV530LE_RADEON_X16002,	R_520  },
+ { DEVICE_ATI_RV530LE_RADEON_X16003,	R_520  },
+ { DEVICE_ATI_RV530_RADEON_X16003,	R_520  },
+ { DEVICE_ATI_RV530_RADEON_X16004,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X1900,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19002,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19003,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19004,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19005,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19006,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19007,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19008,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X19009,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X190010,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X190011,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X190012,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X190013,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X190014,	R_520  },
+ { DEVICE_ATI_R580_RADEON_X190015,	R_520  },
+ { DEVICE_ATI_R580_FIREGL_V7300_V7350,	R_520  },
+ { DEVICE_ATI_R580_FIREGL_V7300_V73502,	R_520  },
 #endif
+};
+
+
 static void * radeon_mmio_base = 0;
 static void * radeon_mem_base = 0; 
 static int32_t radeon_overlay_off = 0;
 static uint32_t radeon_ram_size = 0;
-/* Restore on exit */
-static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0;
-static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0;
-static uint32_t SAVED_OV0_VID_KEY_CLR = 0;
-static uint32_t SAVED_OV0_VID_KEY_MSK = 0;
-static uint32_t SAVED_OV0_KEY_CNTL = 0;
-#ifdef WORDS_BIGENDIAN
-static uint32_t SAVED_CONFIG_CNTL = 0;
-#if defined(RAGE128)
-#define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0)
-#define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0)
-#else
-#define RADEON_SURFACE_CNTL                 0x0b00
-#define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
-#define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
-#endif
-#endif
 
 #define GETREG(TYPE,PTR,OFFZ)		(*((volatile TYPE*)((PTR)+(OFFZ))))
 #define SETREG(TYPE,PTR,OFFZ,VAL)	(*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
 
-#define INREG8(addr)		GETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr)
-#define OUTREG8(addr,val)	SETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr,val)
-
+#define INREG8(addr)		GETREG(uint8_t,(uint8_t *)(radeon_mmio_base),addr)
+#define OUTREG8(addr,val)	SETREG(uint8_t,(uint8_t *)(radeon_mmio_base),addr,val)
 static inline uint32_t INREG (uint32_t addr) {
-	uint32_t tmp = GETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr);
-	return le2me_32(tmp);
+    uint32_t tmp = GETREG(uint32_t,(uint8_t *)(radeon_mmio_base),addr);
+    return le2me_32(tmp);
 }
-//#define OUTREG(addr,val)	SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,val)
-#define OUTREG(addr,val)	SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,le2me_32(val))
-#define OUTREGP(addr,val,mask)  					\
+#define OUTREG(addr,val)	SETREG(uint32_t,(uint8_t *)(radeon_mmio_base),addr,le2me_32(val))
+#define OUTREGP(addr,val,mask)						\
 	do {								\
 		unsigned int _tmp = INREG(addr);			\
 		_tmp &= (mask);						\
@@ -260,7 +601,7 @@ static __inline__ uint32_t INPLL(uint32_t addr)
 
 #define OUTPLL(addr,val)	OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
 				OUTREG(CLOCK_CNTL_DATA, val)
-#define OUTPLLP(addr,val,mask)  					\
+#define OUTPLLP(addr,val,mask)						\
 	do {								\
 		unsigned int _tmp = INPLL(addr);			\
 		_tmp &= (mask);						\
@@ -268,6 +609,85 @@ static __inline__ uint32_t INPLL(uint32_t addr)
 		OUTPLL(addr, _tmp);					\
 	} while (0)
 
+#ifndef RAGE128
+enum radeon_montype
+{
+    MT_NONE,
+    MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
+    MT_LCD, /* Liquid Crystal Display */
+    MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
+    MT_CTV, /* Composite TV out (not in VE) */
+    MT_STV  /* S-Video TV out (probably in VE only) */
+};
+
+typedef struct radeon_info_s
+{
+	int hasCRTC2;
+	int crtDispType;
+	int dviDispType;
+}rinfo_t;
+
+static rinfo_t rinfo;
+
+static char * GET_MON_NAME(int type)
+{
+  char *pret;
+  switch(type)
+  {
+    case MT_NONE: pret = "no"; break;
+    case MT_CRT:  pret = "CRT"; break;
+    case MT_DFP:  pret = "DFP"; break;
+    case MT_LCD:  pret = "LCD"; break;
+    case MT_CTV:  pret = "CTV"; break;
+    case MT_STV:  pret = "STV"; break;
+    default:	  pret = "Unknown";
+  }
+  return pret;
+}
+
+static void radeon_get_moninfo (rinfo_t *rinfo)
+{
+	unsigned int tmp;
+
+	tmp = INREG(RADEON_BIOS_4_SCRATCH);
+
+	if (rinfo->hasCRTC2) {
+		/* primary DVI port */
+		if (tmp & 0x08)
+			rinfo->dviDispType = MT_DFP;
+		else if (tmp & 0x4)
+			rinfo->dviDispType = MT_LCD;
+		else if (tmp & 0x200)
+			rinfo->dviDispType = MT_CRT;
+		else if (tmp & 0x10)
+			rinfo->dviDispType = MT_CTV;
+		else if (tmp & 0x20)
+			rinfo->dviDispType = MT_STV;
+
+		/* secondary CRT port */
+		if (tmp & 0x2)
+			rinfo->crtDispType = MT_CRT;
+		else if (tmp & 0x800)
+			rinfo->crtDispType = MT_DFP;
+		else if (tmp & 0x400)
+			rinfo->crtDispType = MT_LCD;
+		else if (tmp & 0x1000)
+			rinfo->crtDispType = MT_CTV;
+		else if (tmp & 0x2000)
+			rinfo->crtDispType = MT_STV;
+	} else {
+		rinfo->dviDispType = MT_NONE;
+
+		tmp = INREG(FP_GEN_CNTL);
+
+		if (tmp & FP_EN_TMDS)
+			rinfo->crtDispType = MT_DFP;
+		else
+			rinfo->crtDispType = MT_CRT;
+	}
+}
+#endif
+
 static uint32_t radeon_vid_get_dbpp( void )
 {
   uint32_t dbpp,retval;
@@ -295,35 +715,32 @@ static int radeon_is_interlace( void )
 
 static uint32_t radeon_get_xres( void )
 {
-  /* FIXME: currently we extract that from CRTC!!!*/
   uint32_t xres,h_total;
-  h_total = INREG(CRTC_H_TOTAL_DISP);
+#ifndef RAGE128
+  if(rinfo.hasCRTC2 && 
+       (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV))
+	h_total = INREG(CRTC2_H_TOTAL_DISP);
+  else
+#endif
+	h_total = INREG(CRTC_H_TOTAL_DISP);
   xres = (h_total >> 16) & 0xffff;
   return (xres + 1)*8;
 }
 
 static uint32_t radeon_get_yres( void )
 {
-  /* FIXME: currently we extract that from CRTC!!!*/
   uint32_t yres,v_total;
-  v_total = INREG(CRTC_V_TOTAL_DISP);
+#ifndef RAGE128
+  if(rinfo.hasCRTC2 && 
+       (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV))
+	v_total = INREG(CRTC2_V_TOTAL_DISP);
+  else
+#endif
+	v_total = INREG(CRTC_V_TOTAL_DISP);
   yres = (v_total >> 16) & 0xffff;
   return yres + 1;
 }
 
-/* get flat panel x resolution*/
-static uint32_t radeon_get_fp_xres( void ){
-  uint32_t xres=(INREG(FP_HORZ_STRETCH)&0x00fff000)>>16;
-  xres=(xres+1)*8;
-  return xres;
-}
-
-/* get flat panel y resolution*/
-static uint32_t radeon_get_fp_yres( void ){
-  uint32_t yres=(INREG(FP_VERT_STRETCH)&0x00fff000)>>12;
-  return yres+1;
-}
-
 static void radeon_wait_vsync(void)
 {
     int i;
@@ -361,7 +778,7 @@ static void radeon_engine_reset( void )
     radeon_engine_flush();
 
     clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
-    mclk_cntl        = INPLL(MCLK_CNTL);
+    mclk_cntl	     = INPLL(MCLK_CNTL);
 
     OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP);
 
@@ -373,7 +790,7 @@ static void radeon_engine_reset( void )
 	gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI));
     INREG(GEN_RESET_CNTL);
 
-    OUTPLL(MCLK_CNTL,        mclk_cntl);
+    OUTPLL(MCLK_CNTL,	     mclk_cntl);
     OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
     OUTREG(GEN_RESET_CNTL,   gen_reset_cntl);
 }
@@ -385,7 +802,7 @@ static __inline__ void radeon_engine_flush ( void )
 
 	/* initiate flush */
 	OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
-	        ~RB2D_DC_FLUSH_ALL);
+		~RB2D_DC_FLUSH_ALL);
 
 	for (i=0; i < 2000000; i++) {
 		if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
@@ -464,9 +881,8 @@ static void radeon_engine_restore( void )
 
     radeon_fifo_wait(1);
 #if defined(WORDS_BIGENDIAN)
-#ifdef RADEON
-    OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
-#endif
+    OUTREGP(DP_DATATYPE,
+	    HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
 #else
     OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
 #endif
@@ -578,19 +994,19 @@ REF_TRANSFORM trans[2] =
 	{1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0}  /* BT.709 */
 };
 /****************************************************************************
- * SetTransform                                                             *
- *  Function: Calculates and sets color space transform from supplied       *
- *            reference transform, gamma, brightness, contrast, hue and     *
- *            saturation.                                                   *
- *    Inputs: bright - brightness                                           *
- *            cont - contrast                                               *
- *            sat - saturation                                              *
- *            hue - hue                                                     *
- *            red_intensity - intense of red component                      *
- *            green_intensity - intense of green component                  *
- *            blue_intensity - intense of blue component                    *
- *            ref - index to the table of refernce transforms               *
- *   Outputs: NONE                                                          *
+ * SetTransform								    *
+ *  Function: Calculates and sets color space transform from supplied	    *
+ *	      reference transform, gamma, brightness, contrast, hue and	    *
+ *	      saturation.						    *
+ *    Inputs: bright - brightness					    *
+ *	      cont - contrast						    *
+ *	      sat - saturation						    *
+ *	      hue - hue							    *
+ *	      red_intensity - intense of red component			    *
+ *	      green_intensity - intense of green component		    *
+ *	      blue_intensity - intense of blue component		    *
+ *	      ref - index to the table of refernce transforms		    *
+ *   Outputs: NONE							    *
  ****************************************************************************/
 
 static void radeon_set_transform(float bright, float cont, float sat,
@@ -635,7 +1051,7 @@ static void radeon_set_transform(float bright, float cont, float sat,
 	CAdjBCr = sat * OvHueSin * trans[ref].RefBCb;
     
 #if 0 /* default constants */
-        CAdjLuma = 1.16455078125;
+	CAdjLuma = 1.16455078125;
 
 	CAdjRCb = 0.0;
 	CAdjRCr = 1.59619140625;
@@ -669,7 +1085,7 @@ static void radeon_set_transform(float bright, float cont, float sat,
 	/* Whatever docs say about R200 having 3.8 format instead of 3.11
 	   as in Radeon is a lie */
 #if 0
-	if(RadeonFamily == 100)
+	if(!IsR200)
 	{
 #endif
 		dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17;
@@ -744,7 +1160,9 @@ GAMMA