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git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@4692 b3059339-0415-0410-9bf9-f77b7e298cf2

3 files changed, 2674 insertions, 1 deletions

diff --git a/vidix/drivers/Makefile b/vidix/drivers/Makefile
index cec08f342e..256561d9da 100644
--- a/vidix/drivers/Makefile
+++ b/vidix/drivers/Makefile
@@ -17,6 +17,12 @@ RAGE128_OBJS=rage128_vid.o
 RAGE128_LIBS=-L../../libdha -ldha
 RAGE128_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W -DRAGE128
 
+MACH64_VID=mach64_vid.so
+MACH64_SRCS=mach64_vid.c
+MACH64_OBJS=mach64_vid.o
+MACH64_LIBS=-L../../libdha -ldha
+MACH64_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W -DRAGE128
+
 NVIDIA_VID=nvidia_vid.so
 NVIDIA_SRCS=nvidia_vid.c
 NVIDIA_OBJS=nvidia_vid.o
@@ -41,7 +47,7 @@ MGA_CRTC2_OBJS=mga_crtc2_vid.o
 MGA_CRTC2_LIBS=-L../../libdha -ldha -lm
 MGA_CRTC2_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W -DCRTC2
 
-all:    $(RADEON_VID) $(RAGE128_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID)
+all:    $(RADEON_VID) $(RAGE128_VID) $(MACH64_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID)
 
 
 .SUFFIXES: .c .o
@@ -60,6 +66,12 @@ $(RAGE128_OBJS):    $(RAGE128_SRCS)
 $(RAGE128_VID):     $(RAGE128_OBJS)
 	$(LD) $(RAGE128_LIBS) -shared -soname $(RAGE128_VID) -o $(RAGE128_VID) $(RAGE128_OBJS)
 
+$(MACH64_OBJS):    $(MACH64_SRCS)
+	$(CC) -c $(MACH64_CFLAGS) -o $@ $<
+
+$(MACH64_VID):     $(MACH64_OBJS)
+	$(LD) $(MACH64_LIBS) -shared -soname $(MACH64_VID) -o $(MACH64_VID) $(MACH64_OBJS)
+
 $(NVIDIA_OBJS):    $(NVIDIA_SRCS)
 	$(CC) -c $(NVIDIA_CFLAGS) -o $@ $<
 
diff --git a/vidix/drivers/mach64.h b/vidix/drivers/mach64.h
new file mode 100644
index 0000000000..23a95f2378
--- /dev/null
+++ b/vidix/drivers/mach64.h
@@ -0,0 +1,2410 @@
+/*
+ * mach64.h
+ * This	software has been released under the terms of the GNU Public
+ * license. See	http://www.gnu.org/copyleft/gpl.html for details.
+ *
+ * It's	based on radeonfb, X11,	GATOS sources
+*/
+
+#ifndef __MACH64_INCLUDED
+#define __MACH64_INCLUDED 1
+
+/* Note: this model of accessing to IO space is based on MMIO technology.
+This means that this sources don't support ISA and VLB cards */
+#define BlockIOTag(val) (val)
+#define IOPortTag(sparce,val) (val)
+
+/* MDA/[M]CGA/EGA/VGA I/O ports */
+#define GENVS			0x0102u		/* Write (and Read on uC only) */
+
+#define R_GENLPS		0x03b9u		/* Read */
+
+#define GENHP			0x03bfu
+
+#define ATTRX			0x03c0u
+#define ATTRD			0x03c1u
+#define GENS0			0x03c2u		/* Read */
+#define GENMO			0x03c2u		/* Write */
+#define GENENB			0x03c3u		/* Read */
+#define SEQX			0x03c4u
+#define SEQD			0x03c5u
+#define VGA_DAC_MASK		0x03c6u
+#define VGA_DAC_READ		0x03c7u
+#define VGA_DAC_WRITE		0x03c8u
+#define VGA_DAC_DATA		0x03c9u
+#define R_GENFC			0x03cau		/* Read */
+/*	?			0x03cbu */
+#define R_GENMO			0x03ccu		/* Read */
+/*	?			0x03cdu */
+#define GRAX			0x03ceu
+#define GRAD			0x03cfu
+
+#define GENB			0x03d9u
+
+#define GENLPS			0x03dcu		/* Write */
+#define KCX			0x03ddu
+#define KCD			0x03deu
+
+#define GENENA			0x46e8u		/* Write */
+
+/* I/O port base numbers */
+#define MonochromeIOBase	0x03b0u
+#define ColourIOBase		0x03d0u
+
+/* Other MDA/[M]CGA/EGA/VGA I/O ports */
+/*	?(_IOBase)		((_IOBase) + 0x00u) */	/* CRTX synonym */
+/*	?(_IOBase)		((_IOBase) + 0x01u) */	/* CRTD synonym */
+/*	?(_IOBase)		((_IOBase) + 0x02u) */	/* CRTX synonym */
+/*	?(_IOBase)		((_IOBase) + 0x03u) */	/* CRTD synonym */
+#define CRTX(_IOBase)		((_IOBase) + 0x04u)
+#define CRTD(_IOBase)		((_IOBase) + 0x05u)
+/*	?(_IOBase)		((_IOBase) + 0x06u) */
+/*	?(_IOBase)		((_IOBase) + 0x07u) */
+#define GENMC(_IOBase)		((_IOBase) + 0x08u)
+/*	?(_IOBase)		((_IOBase) + 0x09u) */	/* R_GENLPS/GENB */
+#define GENS1(_IOBase)		((_IOBase) + 0x0au)	/* Read */
+#define GENFC(_IOBase)		((_IOBase) + 0x0au)	/* Write */
+#define GENLPC(_IOBase)		((_IOBase) + 0x0bu)
+/*	?(_IOBase)		((_IOBase) + 0x0cu) */	/* /GENLPS */
+/*	?(_IOBase)		((_IOBase) + 0x0du) */	/* /KCX */
+/*	?(_IOBase)		((_IOBase) + 0x0eu) */	/* /KCD */
+/*	?(_IOBase)		((_IOBase) + 0x0fu) */	/* GENHP/ */
+
+/* 8514/A VESA approved register definitions */
+#define DISP_STAT		0x02e8u		/* Read */
+#define SENSE				0x0001u	/* Presumably belong here */
+#define VBLANK				0x0002u
+#define HORTOG				0x0004u
+#define H_TOTAL			0x02e8u		/* Write */
+#define IBM_DAC_MASK		0x02eau
+#define IBM_DAC_READ		0x02ebu
+#define IBM_DAC_WRITE		0x02ecu
+#define IBM_DAC_DATA		0x02edu
+#define H_DISP			0x06e8u		/* Write */
+#define H_SYNC_STRT		0x0ae8u		/* Write */
+#define H_SYNC_WID		0x0ee8u		/* Write */
+#define HSYNCPOL_POS			0x0000u
+#define HSYNCPOL_NEG			0x0020u
+#define H_POLARITY_POS			HSYNCPOL_POS	/* Sigh */
+#define H_POLARITY_NEG			HSYNCPOL_NEG	/* Sigh */
+#define V_TOTAL			0x12e8u		/* Write */
+#define V_DISP			0x16e8u		/* Write */
+#define V_SYNC_STRT		0x1ae8u		/* Write */
+#define V_SYNC_WID		0x1ee8u		/* Write */
+#define VSYNCPOL_POS			0x0000u
+#define VSYNCPOL_NEG			0x0020u
+#define V_POLARITY_POS			VSYNCPOL_POS	/* Sigh */
+#define V_POLARITY_NEG			VSYNCPOL_NEG	/* Sigh */
+#define DISP_CNTL		0x22e8u		/* Write */
+#define ODDBNKENAB			0x0001u
+#define MEMCFG_2			0x0000u
+#define MEMCFG_4			0x0002u
+#define MEMCFG_6			0x0004u
+#define MEMCFG_8			0x0006u
+#define DBLSCAN				0x0008u
+#define INTERLACE			0x0010u
+#define DISPEN_NC			0x0000u
+#define DISPEN_ENAB			0x0020u
+#define DISPEN_DISAB			0x0040u
+#define R_H_TOTAL		0x26e8u		/* Read */
+/*	?			0x2ae8u */
+/*	?			0x2ee8u */
+/*	?			0x32e8u */
+/*	?			0x36e8u */
+/*	?			0x3ae8u */
+/*	?			0x3ee8u */
+#define SUBSYS_STAT		0x42e8u		/* Read */
+#define VBLNKFLG			0x0001u
+#define PICKFLAG			0x0002u
+#define INVALIDIO			0x0004u
+#define GPIDLE				0x0008u
+#define MONITORID_MASK			0x0070u
+/*	MONITORID_?				0x0000u */
+#define MONITORID_8507				0x0010u
+#define MONITORID_8514				0x0020u
+/*	MONITORID_?				0x0030u */
+/*	MONITORID_?				0x0040u */
+#define MONITORID_8503				0x0050u
+#define MONITORID_8512				0x0060u
+#define MONITORID_8513				0x0060u
+#define MONITORID_NONE				0x0070u
+#define _8PLANE				0x0080u
+#define SUBSYS_CNTL		0x42e8u		/* Write */
+#define RVBLNKFLG			0x0001u
+#define RPICKFLAG			0x0002u
+#define RINVALIDIO			0x0004u
+#define RGPIDLE				0x0008u
+#define IVBLNKFLG			0x0100u
+#define IPICKFLAG			0x0200u
+#define IINVALIDIO			0x0400u
+#define IGPIDLE				0x0800u
+#define CHPTEST_NC			0x0000u
+#define CHPTEST_NORMAL			0x1000u
+#define CHPTEST_ENAB			0x2000u
+#define GPCTRL_NC			0x0000u
+#define GPCTRL_ENAB			0x4000u
+#define GPCTRL_RESET			0x8000u
+#define ROM_PAGE_SEL		0x46e8u		/* Write */
+#define ADVFUNC_CNTL		0x4ae8u		/* Write */
+#define DISABPASSTHRU			0x0001u
+#define CLOKSEL				0x0004u
+/*	?			0x4ee8u */
+#define EXT_CONFIG_0		0x52e8u		/* C & T 82C480 */
+#define EXT_CONFIG_1		0x56e8u		/* C & T 82C480 */
+#define EXT_CONFIG_2		0x5ae8u		/* C & T 82C480 */
+#define EXT_CONFIG_3		0x5ee8u		/* C & T 82C480 */
+/*	?			0x62e8u */
+/*	?			0x66e8u */
+/*	?			0x6ae8u */
+/*	?			0x6ee8u */
+/*	?			0x72e8u */
+/*	?			0x76e8u */
+/*	?			0x7ae8u */
+/*	?			0x7ee8u */
+#define CUR_Y			0x82e8u
+#define CUR_X			0x86e8u
+#define DESTY_AXSTP		0x8ae8u		/* Write */
+#define DESTX_DIASTP		0x8ee8u		/* Write */
+#define ERR_TERM		0x92e8u
+#define MAJ_AXIS_PCNT		0x96e8u		/* Write */
+#define GP_STAT			0x9ae8u		/* Read */
+#define GE_STAT			0x9ae8u		/* Alias */
+#define DATARDY				0x0100u
+#define DATA_READY			DATARDY	/* Alias */
+#define GPBUSY				0x0200u
+#define CMD			0x9ae8u		/* Write */
+#define WRTDATA				0x0001u
+#define PLANAR				0x0002u
+#define LASTPIX				0x0004u
+#define LINETYPE			0x0008u
+#define DRAW				0x0010u
+#define INC_X				0x0020u
+#define YMAJAXIS			0x0040u
+#define INC_Y				0x0080u
+#define PCDATA				0x0100u
+#define _16BIT				0x0200u
+#define CMD_NOP				0x0000u
+#define CMD_OP_MSK			0xf000u
+#define BYTSEQ					0x1000u
+#define CMD_LINE				0x2000u
+#define CMD_RECT				0x4000u
+#define CMD_RECTV1				0x6000u
+#define CMD_RECTV2				0x8000u
+#define CMD_LINEAF				0xa000u
+#define CMD_BITBLT				0xc000u
+#define SHORT_STROKE		0x9ee8u		/* Write */
+#define SSVDRAW				0x0010u
+#define VECDIR_000			0x0000u
+#define VECDIR_045			0x0020u
+#define VECDIR_090			0x0040u
+#define VECDIR_135			0x0060u
+#define VECDIR_180			0x0080u
+#define VECDIR_225			0x00a0u
+#define VECDIR_270			0x00c0u
+#define VECDIR_315			0x00e0u
+#define BKGD_COLOR		0xa2e8u		/* Write */
+#define FRGD_COLOR		0xa6e8u		/* Write */
+#define WRT_MASK		0xaae8u		/* Write */
+#define RD_MASK			0xaee8u		/* Write */
+#define COLOR_CMP		0xb2e8u		/* Write */
+#define BKGD_MIX		0xb6e8u		/* Write */
+/*					0x001fu	See MIX_* definitions below */
+#define BSS_BKGDCOL			0x0000u
+#define BSS_FRGDCOL			0x0020u
+#define BSS_PCDATA			0x0040u
+#define BSS_BITBLT			0x0060u
+#define FRGD_MIX		0xbae8u		/* Write */
+/*					0x001fu	See MIX_* definitions below */
+#define FSS_BKGDCOL			0x0000u
+#define FSS_FRGDCOL			0x0020u
+#define FSS_PCDATA			0x0040u
+#define FSS_BITBLT			0x0060u
+#define MULTIFUNC_CNTL		0xbee8u		/* Write */
+#define MIN_AXIS_PCNT			0x0000u
+#define SCISSORS_T			0x1000u
+#define SCISSORS_L			0x2000u
+#define SCISSORS_B			0x3000u
+#define SCISSORS_R			0x4000u
+#define M32_MEM_CNTL			0x5000u
+#define HORCFG_4				0x0000u
+#define HORCFG_5				0x0001u
+#define HORCFG_8				0x0002u
+#define HORCFG_10				0x0003u
+#define VRTCFG_2				0x0000u
+#define VRTCFG_4				0x0004u
+#define VRTCFG_6				0x0008u
+#define VRTCFG_8				0x000cu
+#define BUFSWP					0x0010u
+#define PATTERN_L			0x8000u
+#define PATTERN_H			0x9000u
+#define PIX_CNTL			0xa000u
+#define PLANEMODE				0x0004u
+#define COLCMPOP_F				0x0000u
+#define COLCMPOP_T				0x0008u
+#define COLCMPOP_GE				0x0010u
+#define COLCMPOP_LT				0x0018u
+#define COLCMPOP_NE				0x0020u
+#define COLCMPOP_EQ				0x0028u
+#define COLCMPOP_LE				0x0030u
+#define COLCMPOP_GT				0x0038u
+#define MIXSEL_FRGDMIX				0x0000u
+#define MIXSEL_PATT				0x0040u
+#define MIXSEL_EXPPC				0x0080u
+#define MIXSEL_EXPBLT				0x00c0u
+/*	?			0xc2e8u */
+/*	?			0xc6e8u */
+/*	?			0xcae8u */
+/*	?			0xcee8u */
+/*	?			0xd2e8u */
+/*	?			0xd6e8u */
+/*	?			0xdae8u */
+/*	?			0xdee8u */
+#define PIX_TRANS		0xe2e8u
+/*	?			0xe6e8u */
+/*	?			0xeae8u */
+/*	?			0xeee8u */
+/*	?			0xf2e8u */
+/*	?			0xf6e8u */
+/*	?			0xfae8u */
+/*	?			0xfee8u */
+
+/* ATI Mach8 & Mach32 register definitions */
+#define OVERSCAN_COLOR_8	0x02eeu		/* Write */	/* Mach32 */
+#define OVERSCAN_BLUE_24	0x02efu		/* Write */	/* Mach32 */
+#define OVERSCAN_GREEN_24	0x06eeu		/* Write */	/* Mach32 */
+#define OVERSCAN_RED_24		0x06efu		/* Write */	/* Mach32 */
+#define CURSOR_OFFSET_LO	0x0aeeu		/* Write */	/* Mach32 */
+#define CURSOR_OFFSET_HI	0x0eeeu		/* Write */	/* Mach32 */
+#define CONFIG_STATUS_1		0x12eeu		/* Read */
+#define CLK_MODE			0x0001u			/* Mach8 */
+#define BUS_16				0x0002u			/* Mach8 */
+#define MC_BUS				0x0004u			/* Mach8 */
+#define EEPROM_ENA			0x0008u			/* Mach8 */
+#define DRAM_ENA			0x0010u			/* Mach8 */
+#define MEM_INSTALLED			0x0060u			/* Mach8 */
+#define ROM_ENA				0x0080u			/* Mach8 */
+#define ROM_PAGE_ENA			0x0100u			/* Mach8 */
+#define ROM_LOCATION			0xfe00u			/* Mach8 */
+#define _8514_ONLY			0x0001u			/* Mach32 */
+#define BUS_TYPE			0x000eu			/* Mach32 */
+#define ISA_16_BIT				0x0000u		/* Mach32 */
+#define EISA					0x0002u		/* Mach32 */
+#define MICRO_C_16_BIT				0x0004u		/* Mach32 */
+#define MICRO_C_8_BIT				0x0006u		/* Mach32 */
+#define LOCAL_386SX				0x0008u		/* Mach32 */
+#define LOCAL_386DX				0x000au		/* Mach32 */
+#define LOCAL_486				0x000cu		/* Mach32 */
+#define PCI					0x000eu		/* Mach32 */
+#define MEM_TYPE			0x0070u			/* Mach32 */
+#define CHIP_DIS			0x0080u			/* Mach32 */
+#define TST_VCTR_ENA			0x0100u			/* Mach32 */
+#define DACTYPE				0x0e00u			/* Mach32 */
+#define MC_ADR_DECODE			0x1000u			/* Mach32 */
+#define CARD_ID				0xe000u			/* Mach32 */
+#define HORZ_CURSOR_POSN	0x12eeu		/* Write */	/* Mach32 */
+#define CONFIG_STATUS_2		0x16eeu		/* Read */
+#define SHARE_CLOCK			0x0001u			/* Mach8 */
+#define HIRES_BOOT			0x0002u			/* Mach8 */
+#define EPROM_16_ENA			0x0004u			/* Mach8 */
+#define WRITE_PER_BIT			0x0008u			/* Mach8 */
+#define FLASH_ENA			0x0010u			/* Mach8 */
+#define SLOW_SEQ_EN			0x0001u			/* Mach32 */
+#define MEM_ADDR_DIS			0x0002u			/* Mach32 */
+#define ISA_16_ENA			0x0004u			/* Mach32 */
+#define KOR_TXT_MODE_ENA		0x0008u			/* Mach32 */
+#define LOCAL_BUS_SUPPORT		0x0030u			/* Mach32 */
+#define LOCAL_BUS_CONFIG_2		0x0040u			/* Mach32 */
+#define LOCAL_BUS_RD_DLY_ENA		0x0080u			/* Mach32 */
+#define LOCAL_DAC_EN			0x0100u			/* Mach32 */
+#define LOCAL_RDY_EN			0x0200u			/* Mach32 */
+#define EEPROM_ADR_SEL			0x0400u			/* Mach32 */
+#define GE_STRAP_SEL			0x0800u			/* Mach32 */
+#define VESA_RDY			0x1000u			/* Mach32 */
+#define Z4GB				0x2000u			/* Mach32 */
+#define LOC2_MDRAM			0x4000u			/* Mach32 */
+#define VERT_CURSOR_POSN	0x16eeu		/* Write */	/* Mach32 */
+#define FIFO_TEST_DATA		0x1aeeu		/* Read */	/* Mach32 */
+#define CURSOR_COLOR_0		0x1aeeu		/* Write */	/* Mach32 */
+#define CURSOR_COLOR_1		0x1aefu		/* Write */	/* Mach32 */
+#define HORZ_CURSOR_OFFSET	0x1eeeu		/* Write */	/* Mach32 */
+#define VERT_CURSOR_OFFSET	0x1eefu		/* Write */	/* Mach32 */
+#define PCI_CNTL		0x22eeu				/* Mach32-PCI */
+#define CRT_PITCH		0x26eeu		/* Write */
+#define CRT_OFFSET_LO		0x2aeeu		/* Write */
+#define CRT_OFFSET_HI		0x2eeeu		/* Write */
+#define LOCAL_CNTL		0x32eeu				/* Mach32 */
+#define FIFO_OPT		0x36eeu		/* Write */	/* Mach8 */
+#define MISC_OPTIONS		0x36eeu				/* Mach32 */
+#define W_STATE_ENA			0x0000u			/* Mach32 */
+#define HOST_8_ENA			0x0001u			/* Mach32 */
+#define MEM_SIZE_ALIAS			0x000cu			/* Mach32 */
+#define MEM_SIZE_512K				0x0000u		/* Mach32 */
+#define MEM_SIZE_1M				0x0004u		/* Mach32 */
+#define MEM_SIZE_2M				0x0008u		/* Mach32 */
+#define MEM_SIZE_4M				0x000cu		/* Mach32 */
+#define DISABLE_VGA			0x0010u			/* Mach32 */
+#define _16_BIT_IO			0x0020u			/* Mach32 */
+#define DISABLE_DAC			0x0040u			/* Mach32 */
+#define DLY_LATCH_ENA			0x0080u			/* Mach32 */
+#define TEST_MODE			0x0100u			/* Mach32 */
+#define BLK_WR_ENA			0x0400u			/* Mach32 */
+#define _64_DRAW_ENA			0x0800u			/* Mach32 */
+#define FIFO_TEST_TAG		0x3aeeu		/* Read */	/* Mach32 */
+#define EXT_CURSOR_COLOR_0	0x3aeeu		/* Write */	/* Mach32 */
+#define EXT_CURSOR_COLOR_1	0x3eeeu		/* Write */	/* Mach32 */
+#define MEM_BNDRY		0x42eeu				/* Mach32 */
+#define MEM_PAGE_BNDRY			0x000fu			/* Mach32 */
+#define MEM_BNDRY_ENA			0x0010u			/* Mach32 */
+#define SHADOW_CTL		0x46eeu		/* Write */
+#define CLOCK_SEL		0x4aeeu
+/*	DISABPASSTHRU			0x0001u	See ADVFUNC_CNTL */
+#define VFIFO_DEPTH_1			0x0100u			/* Mach32 */
+#define VFIFO_DEPTH_2			0x0200u			/* Mach32 */
+#define VFIFO_DEPTH_3			0x0300u			/* Mach32 */
+#define VFIFO_DEPTH_4			0x0400u			/* Mach32 */
+#define VFIFO_DEPTH_5			0x0500u			/* Mach32 */
+#define VFIFO_DEPTH_6			0x0600u			/* Mach32 */
+#define VFIFO_DEPTH_7			0x0700u			/* Mach32 */
+#define VFIFO_DEPTH_8			0x0800u			/* Mach32 */
+#define VFIFO_DEPTH_9			0x0900u			/* Mach32 */
+#define VFIFO_DEPTH_A			0x0a00u			/* Mach32 */
+#define VFIFO_DEPTH_B			0x0b00u			/* Mach32 */
+#define VFIFO_DEPTH_C			0x0c00u			/* Mach32 */
+#define VFIFO_DEPTH_D			0x0d00u			/* Mach32 */
+#define VFIFO_DEPTH_E			0x0e00u			/* Mach32 */
+#define VFIFO_DEPTH_F			0x0f00u			/* Mach32 */
+#define COMPOSITE_SYNC			0x1000u
+/*	?			0x4eeeu */
+#define ROM_ADDR_1		0x52eeu
+#define BIOS_BASE_SEGMENT		0x007fu			/* Mach32 */
+/*	?				0xff80u */		/* Mach32 */
+#define ROM_ADDR_2		0x56eeu		/* Sick ... */
+#define SHADOW_SET		0x5aeeu		/* Write */
+#define MEM_CFG			0x5eeeu				/* Mach32 */
+#define MEM_APERT_SEL			0x0003u			/* Mach32 */
+#define MEM_APERT_PAGE			0x000cu			/* Mach32 */
+#define MEM_APERT_LOC			0xfff0u			/* Mach32 */
+#define EXT_GE_STATUS		0x62eeu		/* Read */	/* Mach32 */
+#define HORZ_OVERSCAN		0x62eeu		/* Write */	/* Mach32 */
+#define VERT_OVERSCAN		0x66eeu		/* Write */	/* Mach32 */
+#define MAX_WAITSTATES		0x6aeeu
+#define GE_OFFSET_LO		0x6eeeu		/* Write */
+#define BOUNDS_LEFT		0x72eeu		/* Read */
+#define GE_OFFSET_HI		0x72eeu		/* Write */
+#define BOUNDS_TOP		0x76eeu		/* Read */
+#define GE_PITCH		0x76eeu		/* Write */
+#define BOUNDS_RIGHT		0x7aeeu		/* Read */
+#define EXT_GE_CONFIG		0x7aeeu		/* Write */	/* Mach32 */
+#define MONITOR_ALIAS			0x0007u			/* Mach32 */
+/*	MONITOR_?				0x0000u */	/* Mach32 */
+#define MONITOR_8507				0x0001u		/* Mach32 */
+#define MONITOR_8514				0x0002u		/* Mach32 */
+/*	MONITOR_?				0x0003u */	/* Mach32 */
+/*	MONITOR_?				0x0004u */	/* Mach32 */
+#define MONITOR_8503				0x0005u		/* Mach32 */
+#define MONITOR_8512				0x0006u		/* Mach32 */
+#define MONITOR_8513				0x0006u		/* Mach32 */
+#define MONITOR_NONE				0x0007u		/* Mach32 */
+#define ALIAS_ENA			0x0008u			/* Mach32 */
+#define PIXEL_WIDTH_4			0x0000u			/* Mach32 */
+#define PIXEL_WIDTH_8			0x0010u			/* Mach32 */
+#define PIXEL_WIDTH_16			0x0020u			/* Mach32 */
+#define PIXEL_WIDTH_24			0x0030u			/* Mach32 */
+#define RGB16_555			0x0000u			/* Mach32 */
+#define RGB16_565			0x0040u			/* Mach32 */
+#define RGB16_655			0x0080u			/* Mach32 */
+#define RGB16_664			0x00c0u			/* Mach32 */
+#define MULTIPLEX_PIXELS		0x0100u			/* Mach32 */
+#define RGB24				0x0000u			/* Mach32 */
+#define RGBx24				0x0200u			/* Mach32 */
+#define BGR24				0x0400u			/* Mach32 */
+#define xBGR24				0x0600u			/* Mach32 */
+#define DAC_8_BIT_EN			0x4000u			/* Mach32 */
+#define ORDER_16BPP_565			RGB16_565		/* Mach32 */
+#define BOUNDS_BOTTOM		0x7eeeu		/* Read */
+#define MISC_CNTL		0x7eeeu		/* Write */	/* Mach32 */
+#define PATT_DATA_INDEX		0x82eeu
+/*	?			0x86eeu */
+/*	?			0x8aeeu */
+#define R_EXT_GE_CONFIG		0x8eeeu		/* Read */	/* Mach32 */
+#define PATT_DATA		0x8eeeu		/* Write */
+#define R_MISC_CNTL		0x92eeu		/* Read */	/* Mach32 */
+#define BRES_COUNT		0x96eeu
+#define EXT_FIFO_STATUS		0x9aeeu		/* Read */
+#define LINEDRAW_INDEX		0x9aeeu		/* Write */
+/*	?			0x9eeeu */
+#define LINEDRAW_OPT		0xa2eeu
+#define BOUNDS_RESET			0x0100u
+#define CLIP_MODE_0			0x0000u	/* Clip exception disabled */
+#define CLIP_MODE_1			0x0200u	/* Line segments */
+#define CLIP_MODE_2			0x0400u	/* Polygon boundary lines */
+#define CLIP_MODE_3			0x0600u	/* Patterned lines */
+#define DEST_X_START		0xa6eeu		/* Write */
+#define DEST_X_END		0xaaeeu		/* Write */
+#define DEST_Y_END		0xaeeeu		/* Write */
+#define R_H_TOTAL_DISP		0xb2eeu		/* Read */	/* Mach32 */
+#define SRC_X_STRT		0xb2eeu		/* Write */
+#define R_H_SYNC_STRT		0xb6eeu		/* Read */	/* Mach32 */
+#define ALU_BG_FN		0xb6eeu		/* Write */
+#define R_H_SYNC_WID		0xbaeeu		/* Read */	/* Mach32 */
+#define ALU_FG_FN		0xbaeeu		/* Write */
+#define SRC_X_END		0xbeeeu		/* Write */
+#define R_V_TOTAL		0xc2eeu		/* Read */
+#define SRC_Y_DIR		0xc2eeu		/* Write */
+#define R_V_DISP		0xc6eeu		/* Read */	/* Mach32 */
+#define EXT_SHORT_STROKE	0xc6eeu		/* Write */
+#define R_V_SYNC_STRT		0xcaeeu		/* Read */	/* Mach32 */
+#define SCAN_X			0xcaeeu		/* Write */
+#define VERT_LINE_CNTR		0xceeeu		/* Read */	/* Mach32 */
+#define DP_CONFIG		0xceeeu		/* Write */
+#define READ_WRITE			0x0001u
+#define DATA_WIDTH			0x0200u
+#define DATA_ORDER			0x1000u
+#define FG_COLOR_SRC_FG			0x2000u
+#define FG_COLOR_SRC_BLIT		0x6000u
+#define R_V_SYNC_WID		0xd2eeu		/* Read */
+#define PATT_LENGTH		0xd2eeu		/* Write */
+#define PATT_INDEX		0xd6eeu		/* Write */
+#define READ_SRC_X		0xdaeeu		/* Read */	/* Mach32 */
+#define EXT_SCISSOR_L		0xdaeeu		/* Write */
+#define READ_SRC_Y		0xdeeeu		/* Read */	/* Mach32 */
+#define EXT_SCISSOR_T		0xdeeeu		/* Write */
+#define EXT_SCISSOR_R		0xe2eeu		/* Write */
+#define EXT_SCISSOR_B		0xe6eeu		/* Write */
+/*	?			0xeaeeu */
+#define DEST_COMP_FN		0xeeeeu		/* Write */
+#define DEST_COLOR_CMP_MASK	0xf2eeu		/* Write */	/* Mach32 */
+/*	?			0xf6eeu */
+#define CHIP_ID			0xfaeeu		/* Read */	/* Mach32 */
+#define CHIP_CODE_0			0x001fu			/* Mach32 */
+#define CHIP_CODE_1			0x03e0u			/* Mach32 */
+#define CHIP_CLASS			0x0c00u			/* Mach32 */
+#define CHIP_REV			0xf000u			/* Mach32 */
+#define LINEDRAW		0xfeeeu		/* Write */
+
+/* ATI Mach64 register definitions */
+#define CRTC_H_TOTAL_DISP	IOPortTag(0x00u, 0x00u)
+#define CRTC_H_TOTAL			0x000001fful
+/*	?				0x0000fe00ul */
+#define CRTC_H_DISP			0x01ff0000ul
+/*	?				0xfe000000ul */
+#define CRTC_H_SYNC_STRT_WID	IOPortTag(0x01u, 0x01u)
+#define CRTC_H_SYNC_STRT		0x000000fful
+#define CRTC_H_SYNC_DLY			0x00000700ul
+/*	?				0x00000800ul */
+#define CRTC_H_SYNC_STRT_HI		0x00001000ul
+/*	?				0x0000e000ul */
+#define CRTC_H_SYNC_WID			0x001f0000ul
+#define CRTC_H_SYNC_POL			0x00200000ul
+/*	?				0xffc00000ul */
+#define CRTC_V_TOTAL_DISP	IOPortTag(0x02u, 0x02u)
+#define CRTC_V_TOTAL			0x000007fful
+/*	?				0x0000f800ul */
+#define CRTC_V_DISP			0x07ff0000ul
+/*	?				0xf8000000ul */
+#define CRTC_V_SYNC_STRT_WID	IOPortTag(0x03u, 0x03u)
+#define CRTC_V_SYNC_STRT		0x000007fful
+/*	?				0x0000f800ul */
+#define CRTC_V_SYNC_WID			0x001f0000ul
+#define CRTC_V_SYNC_POL			0x00200000ul
+/*	?				0xffc00000ul */
+#define CRTC_VLINE_CRNT_VLINE	IOPortTag(0x04u, 0x04u)
+#define CRTC_VLINE			0x000007fful
+/*	?				0x0000f800ul */
+#define CRTC_CRNT_VLINE			0x07ff0000ul
+/*	?				0xf8000000ul */
+#define CRTC_OFF_PITCH		IOPortTag(0x05u, 0x05u)
+#define CRTC_OFFSET			0x000ffffful
+#define CRTC_OFFSET_VGA			0x0003fffful
+#define CRTC_OFFSET_LOCK		0x00100000ul	/* XC/XL */
+/*	?				0x00200000ul */
+#define CRTC_PITCH			0xffc00000ul
+#define CRTC_INT_CNTL		IOPortTag(0x06u, 0x06u)
+#define CRTC_VBLANK			0x00000001ul
+#define CRTC_VBLANK_INT_EN		0x00000002ul
+#define CRTC_VBLANK_INT			0x00000004ul
+#define CRTC_VLINE_INT_EN		0x00000008ul
+#define CRTC_VLINE_INT			0x00000010ul
+#define CRTC_VLINE_SYNC			0x00000020ul
+#define CRTC_FRAME			0x00000040ul
+#define CRTC_SNAPSHOT_INT_EN		0x00000080ul	/* GTPro */
+#define CRTC_SNAPSHOT_INT		0x00000100ul	/* GTPro */
+#define CRTC_I2C_INT_EN			0x00000200ul	/* GTPro */
+#define CRTC_I2C_INT			0x00000400ul	/* GTPro */
+#define CRTC2_VBLANK			0x00000800ul	/* LTPro */
+#define CRTC2_VBLANK_INT_EN		0x00001000ul	/* LTPro */
+#define CRTC2_VBLANK_INT		0x00002000ul	/* LTPro */
+#define CRTC2_VLINE_INT_EN		0x00004000ul	/* LTPro */
+#define CRTC2_VLINE_INT			0x00008000ul	/* LTPro */
+#define CRTC_CAPBUF0_INT_EN		0x00010000ul	/* VT/GT */
+#define CRTC_CAPBUF0_INT		0x00020000ul	/* VT/GT */
+#define CRTC_CAPBUF1_INT_EN		0x00040000ul	/* VT/GT */
+#define CRTC_CAPBUF1_INT		0x00080000ul	/* VT/GT */
+#define CRTC_OVERLAY_EOF_INT_EN		0x00100000ul	/* VT/GT */
+#define CRTC_OVERLAY_EOF_INT		0x00200000ul	/* VT/GT */
+#define CRTC_ONESHOT_CAP_INT_EN		0x00400000ul	/* VT/GT */
+#define CRTC_ONESHOT_CAP_INT		0x00800000ul	/* VT/GT */
+#define CRTC_BUSMASTER_EOL_INT_EN	0x01000000ul	/* VTB/GTB/LT */
+#define CRTC_BUSMASTER_EOL_INT		0x02000000ul	/* VTB/GTB/LT */
+#define CRTC_GP_INT_EN			0x04000000ul	/* VTB/GTB/LT */
+#define CRTC_GP_INT			0x08000000ul	/* VTB/GTB/LT */
+#define CRTC2_VLINE_SYNC		0x10000000ul	/* LTPro */
+#define CRTC_SNAPSHOT2_INT_EN		0x20000000ul	/* LTPro */
+#define CRTC_SNAPSHOT2_INT		0x40000000ul	/* LTPro */
+#define CRTC_VBLANK_BIT2_INT		0x80000000ul	/* GTPro */
+#define CRTC_INT_ENS	/* *** UPDATE ME *** */		\
+		(					\
+			CRTC_VBLANK_INT_EN |		\
+			CRTC_VLINE_INT_EN |		\
+			CRTC_SNAPSHOT_INT_EN |		\
+			CRTC_I2C_INT_EN |		\
+			CRTC2_VBLANK_INT_EN |		\
+			CRTC2_VLINE_INT_EN |		\
+			CRTC_CAPBUF0_INT_EN |		\
+			CRTC_CAPBUF1_INT_EN |		\
+			CRTC_OVERLAY_EOF_INT_EN |	\
+			CRTC_ONESHOT_CAP_INT_EN |	\
+			CRTC_BUSMASTER_EOL_INT_EN |	\
+			CRTC_GP_INT_EN |		\
+			CRTC_SNAPSHOT2_INT_EN |		\
+			0				\
+		)
+#define CRTC_INT_ACKS	/* *** UPDATE ME *** */		\
+		(					\
+			CRTC_VBLANK_INT |		\
+			CRTC_VLINE_INT |		\
+			CRTC_SNAPSHOT_INT |		\
+			CRTC_I2C_INT |			\
+			CRTC2_VBLANK_INT |		\
+			CRTC2_VLINE_INT |		\
+			CRTC_CAPBUF0_INT |		\
+			CRTC_CAPBUF1_INT |		\
+			CRTC_OVERLAY_EOF_INT |		\
+			CRTC_ONESHOT_CAP_INT |		\
+			CRTC_BUSMASTER_EOL_INT |	\
+			CRTC_GP_INT |			\
+			CRTC_SNAPSHOT2_INT |		\
+			CRTC_VBLANK_BIT2_INT |		\
+			0				\
+		)
+#define CRTC_GEN_CNTL		IOPortTag(0x07u, 0x07u)
+#define CRTC_DBL_SCAN_EN		0x00000001ul
+#define CRTC_INTERLACE_EN		0x00000002ul
+#define CRTC_HSYNC_DIS			0x00000004ul
+#define CRTC_VSYNC_DIS			0x00000008ul
+#define CRTC_CSYNC_EN			0x00000010ul
+#define CRTC_PIX_BY_2_EN		0x00000020ul
+#define CRTC2_DBL_SCAN_EN		0x00000020ul	/* LTPro */
+#define CRTC_DISPLAY_DIS		0x00000040ul
+#define CRTC_VGA_XOVERSCAN		0x00000080ul
+#define CRTC_PIX_WIDTH			0x00000700ul
+#define CRTC_BYTE_PIX_ORDER		0x00000800ul
+#define CRTC_VSYNC_INT_EN		0x00001000ul	/* XC/XL */
+#define CRTC_VSYNC_INT			0x00002000ul	/* XC/XL */
+#define CRTC_FIFO_OVERFILL		0x0000c000ul	/* VT/GT */
+#define CRTC2_VSYNC_INT_EN		0x00004000ul	/* XC/XL */
+#define CRTC2_VSYNC_INT			0x00008000ul	/* XC/XL */
+#define CRTC_FIFO_LWM			0x000f0000ul
+#define CRTC_HVSYNC_IO_DRIVE		0x00010000ul	/* XC/XL */
+#define CRTC2_PIX_WIDTH			0x000e0000ul	/* LTPro */
+#define CRTC_VGA_128KAP_PAGING		0x00100000ul	/* VT/GT */
+#define CRTC_DISPREQ_ONLY		0x00200000ul	/* VT/GT */
+#define CRTC_VFC_SYNC_TRISTATE		0x00200000ul	/* VTB/GTB/LT */
+#define CRTC2_EN			0x00200000ul	/* LTPro */
+#define CRTC_LOCK_REGS			0x00400000ul	/* VT/GT */
+#define CRTC_SYNC_TRISTATE		0x00800000ul	/* VT/GT */
+#define CRTC_EXT_DISP_EN		0x01000000ul
+#define CRTC_EN				0x02000000ul
+#define CRTC_DISP_REQ_EN		0x04000000ul
+#define CRTC_VGA_LINEAR			0x08000000ul
+#define CRTC_VSYNC_FALL_EDGE		0x10000000ul
+#define CRTC_VGA_TEXT_132		0x20000000ul
+#define CRTC_CNT_EN			0x40000000ul
+#define CRTC_CUR_B_TEST			0x80000000ul
+#define CRTC_INT_ENS_X	/* *** UPDATE ME *** */		\
+		(					\
+			CRTC_VSYNC_INT_EN |		\
+			CRTC2_VSYNC_INT_EN |		\
+			0				\
+		)
+#define CRTC_INT_ACKS_X	/* *** UPDATE ME *** */		\
+		(					\
+			CRTC_VSYNC_INT |		\
+			CRTC2_VSYNC_INT |		\
+			0				\
+		)
+#define DSP_CONFIG		BlockIOTag(0x08u)	/* VTB/GTB/LT */
+#define DSP_XCLKS_PER_QW		0x00003ffful
+/*	?				0x00004000ul */
+#define DSP_FLUSH_WB			0x00008000ul
+#define DSP_LOOP_LATENCY		0x000f0000ul
+#define DSP_PRECISION			0x00700000ul
+/*	?				0xff800000ul */
+#define DSP_ON_OFF		BlockIOTag(0x09u)	/* VTB/GTB/LT */
+#define DSP_OFF				0x000007fful
+/*	?				0x0000f800ul */
+#define DSP_ON				0x07ff0000ul
+/*	?				0xf8000000ul */
+#define TIMER_CONFIG		BlockIOTag(0x0au)	/* VTB/GTB/LT */
+#define MEM_BUF_CNTL		BlockIOTag(0x0bu)	/* VTB/GTB/LT */
+#define SHARED_CNTL		BlockIOTag(0x0cu)	/* VTB/GTB/LT */
+#define SHARED_MEM_CONFIG	BlockIOTag(0x0du)	/* VTB/GTB/LT */
+#define MEM_ADDR_CONFIG		BlockIOTag(0x0du)	/* GTPro */
+#define SHARED_CNTL_CTD		BlockIOTag(0x0eu)	/* CTD */
+/*	?				0x00fffffful */
+#define CTD_FIFO5			0x01000000ul
+/*	?				0xfe000000ul */
+#define CRT_TRAP		BlockIOTag(0x0eu)	/* VTB/GTB/LT */
+#define DSTN_CONTROL		BlockIOTag(0x0fu)	/* LT */
+#define I2C_CNTL_0		BlockIOTag(0x0fu)	/* GTPro */
+#define OVR_CLR			IOPortTag(0x08u, 0x10u)
+#define OVR_CLR_8			0x000000fful
+#define OVR_CLR_B			0x0000ff00ul
+#define OVR_CLR_G			0x00ff0000ul
+#define OVR_CLR_R			0xff000000ul
+#define OVR_WID_LEFT_RIGHT	IOPortTag(0x09u, 0x11u)
+#define OVR_WID_LEFT			0x0000003ful	/* 0x0f on <LT */
+/*	?				0x0000ffc0ul */
+#define OVR_WID_RIGHT			0x003f0000ul	/* 0x0f0000 on <LT */
+/*	?				0xffc00000ul */
+#define OVR_WID_TOP_BOTTOM	IOPortTag(0x0au, 0x12u)
+#define OVR_WID_TOP			0x000001fful	/* 0x00ff on <LT */
+/*	?				0x0000fe00ul */
+#define OVR_WID_BOTTOM			0x01ff0000ul	/* 0x00ff0000 on <LT */
+/*	?				0xfe000000ul */
+#define VGA_DSP_CONFIG		BlockIOTag(0x13u)	/* VTB/GTB/LT */
+#define VGA_DSP_XCLKS_PER_QW		DSP_XCLKS_PER_QW
+/*	?				0x000fc000ul */
+#define VGA_DSP_PREC_PCLKBY2		0x00700000ul
+/*	?				0x00800000ul */
+#define VGA_DSP_PREC_PCLK		0x07000000ul
+/*	?				0xf8000000ul */
+#define VGA_DSP_ON_OFF		BlockIOTag(0x14u)	/* VTB/GTB/LT */
+#define VGA_DSP_OFF			DSP_OFF
+/*	?				0x0000f800ul */
+#define VGA_DSP_ON			DSP_ON
+/*	?				0xf8000000ul */
+#define DSP2_CONFIG		BlockIOTag(0x15u)	/* LTPro */
+#define DSP2_ON_OFF		BlockIOTag(0x16u)	/* LTPro */
+#define EXT_CRTC_GEN_CNTL	BlockIOTag(0x17u)	/* VT-A4 (W) */
+#define CRTC2_OFF_PITCH		BlockIOTag(0x17u)	/* LTPro */
+#define CUR_CLR0		IOPortTag(0x0bu, 0x18u)
+#define CUR_CLR1		IOPortTag(0x0cu, 0x19u)
+/* These are for both CUR_CLR0 and CUR_CLR1 */
+#define CUR_CLR_I			0x000000fful
+#define CUR_CLR_B			0x0000ff00ul
+#define CUR_CLR_G			0x00ff0000ul
+#define CUR_CLR_R			0xff000000ul
+#define CUR_CLR				(CUR_CLR_R | CUR_CLR_G | CUR_CLR_B)
+#define CUR_OFFSET		IOPortTag(0x0du, 0x1au)
+#define CUR_HORZ_VERT_POSN	IOPortTag(0x0eu, 0x1bu)
+#define CUR_HORZ_POSN			0x000007fful
+/*	?				0x0000f800ul */
+#define CUR_VERT_POSN			0x07ff0000ul
+/*	?				0xf8000000ul */
+#define CUR_HORZ_VERT_OFF	IOPortTag(0x0fu, 0x1cu)
+#define CUR_HORZ_OFF			0x0000007ful
+/*	?				0x0000ff80ul */
+#define CUR_VERT_OFF			0x007f0000ul
+/*	?				0xff800000ul */
+#define CONFIG_PANEL		BlockIOTag(0x1du)	/* LT */
+#define PANEL_FORMAT			0x00000007ul
+/*	?				0x00000008ul */
+#define PANEL_TYPE			0x000000f0ul
+#define NO_OF_GREY			0x00000700ul
+#define MOD_GEN				0x00001800ul
+#define EXT_LVDS_CLK			0x00001800ul	/* LTPro */
+#define BLINK_RATE			0x00006000ul
+#define BLINK_RATE_PRO			0x00002000ul	/* LTPro */
+#define DONT_SHADOW_HEND		0x00004000ul	/* LTPro */
+#define DONT_USE_F32KHZ			0x00008000ul
+#define LCD_IO_DRIVE			0x00008000ul	/* XC/XL */
+#define FP_POL				0x00010000ul
+#define LP_POL				0x00020000ul
+#define DTMG_POL			0x00040000ul
+#define SCK_POL				0x00080000ul
+#define DITHER_SEL			0x00300000ul
+#define INVERSE_VIDEO_EN		0x00400000ul
+#define BL_CLK_SEL			0x01800000ul
+#define BL_LEVEL			0x0e000000ul
+#define BL_CLK_SEL_PRO			0x00800000ul	/* LTPro */
+#define BL_LEVEL_PRO			0x03000000ul	/* LTPro */
+#define BIAS_LEVEL_PRO			0x0c000000ul	/* LTPro */
+#define HSYNC_DELAY			0xf0000000ul
+#define TV_OUT_INDEX		BlockIOTag(0x1du)	/* LTPro */
+#define TV_REG_INDEX			0x000000fful
+#define TV_ON				0x00000100ul
+/*	?				0xfffffe00ul */
+#define GP_IO			IOPortTag(0x1eu, 0x1eu)	/* VT/GT */
+#define GP_IO_CNTL		BlockIOTag(0x1fu)	/* VT/GT */
+#define HW_DEBUG		BlockIOTag(0x1fu)	/* VTB/GTB/LT */
+#define FAST_SRCCOPY_DIS		0x00000001ul
+#define BYPASS_SUBPIC_DBF		0x00000001ul	/* XL/XC */
+#define SRC_AUTONA_FIX_DIS		0x00000002ul
+#define SYNC_PD_EN			0x00000002ul	/* Mobility */
+#define DISP_QW_FIX_DIS			0x00000004ul
+#define GUIDST_WB_EXP_DIS		0x00000008ul
+#define CYC_ALL_FIX_DIS			0x00000008ul	/* GTPro */
+#define AGPPLL_FIX_EN			0x00000008ul	/* Mobility */
+#define SRC_AUTONA_ALWAYS_EN		0x00000010ul
+#define GUI_BEATS_HOST_P		0x00000010ul	/* GTPro */
+#define DRV_CNTL_DQMB_WEB		0x00000020ul
+#define FAST_FILL_SCISSOR_DIS		0x00000020ul	/* GT2c/VT4 */
+#define INTER_BLIT_FIX_DIS		0x00000020ul	/* GTPro */
+#define DRV_CNTL_MA			0x00000040ul
+#define AUTO_BLKWRT_COLOR_DIS		0x00000040ul	/* GT2c/VT4 */
+#define INTER_PRIM_DIS			0x00000040ul	/* GTPro */
+#define DRV_CNTL_MD			0x00000080ul
+#define CHG_DEV_ID			0x00000100ul
+#define SRC_TRACK_DST_FIX_DIS		0x00000200ul
+#define HCLK_FB_SKEW			0x00000380ul	/* GT2c/VT4 */
+#define SRC_TRACK_DST_FIX_DIS_P		0x00000080ul	/* GTPro */
+#define AUTO_BLKWRT_COLOR_DIS_P		0x00000100ul	/* GTPro */
+#define INTER_LINE_OVERLAP_DIS		0x00000200ul	/* GTPro */
+#define MEM_OE_PULLBACK			0x00000400ul
+#define DBL_BUFFER_EN			0x00000400ul	/* GTPro */
+#define MEM_WE_FIX_DIS			0x00000800ul
+#define MEM_OE_PULLBACK_B		0x00000800ul	/* GT2c/VT4 */
+#define CMDFIFO_SIZE_DIS_P		0x00000800ul	/* GTPro */
+#define RD_EN_FIX_DIS			0x00001000ul
+#define MEM_WE_FIX_DIS_B		0x00001000ul
+#define AUTO_FF_DIS			0x00001000ul	/* GTPro */
+#define CMDFIFO_SIZE_DIS		0x00002000ul	/* GT2c/VT4 */
+#define AUTO_BLKWRT_DIS			0x00002000ul	/* GTPro */
+#define GUI_BEATS_HOST			0x00004000ul	/* GT2c/VT4 */
+#define ORED_INVLD_RB_CACHE		0x00004000ul	/* GTPro */
+#define BLOCK_DBL_BUF			0x00008000ul	/* GTPro */
+#define R2W_TURNAROUND_DELAY		0x00020000ul	/* GT2c/VT4 */
+#define ENA_32BIT_DATA_BUS		0x00040000ul	/* GT2c/VT4 */
+#define HCLK_FB_SKEW_P			0x00070000ul	/* GTPro */
+#define ENA_FLASH_ROM			0x00080000ul	/* GT2c/VT4 */
+#define DISABLE_SWITCH_FIX		0x00080000ul	/* GTPro */
+#define MCLK_START_EN			0x00080000ul	/* LTPro */
+#define SEL_VBLANK_BDL_BUF		0x00100000ul	/* GTPro */
+#define CMDFIFO_64EN			0x00200000ul	/* GTPro */
+#define BM_FIX_DIS			0x00400000ul	/* GTPro */
+#define Z_SWITCH_EN			0x00800000ul	/* LTPro */
+#define FLUSH_HOST_WB			0x01000000ul	/* GTPro */
+#define HW_DEBUG_WRITE_MSK_FIX_DIS	0x02000000ul	/* LTPro */
+#define Z_NO_WRITE_EN			0x04000000ul	/* LTPro */
+#define DISABLE_PCLK_RESET_P		0x08000000ul	/* LTPro */
+#define PM_D3_SUPPORT_ENABLE_P		0x10000000ul	/* LTPro */
+#define STARTCYCLE_FIX_ENABLE		0x20000000ul	/* LTPro */
+#define DONT_RST_CHAREN			0x20000000ul	/* XL/XC */
+#define C3_FIX_ENABLE			0x40000000ul	/* LTPro */
+#define BM_HOSTRA_EN			0x40000000ul	/* XL/XC */
+#define PKGBGAb				0x80000000ul	/* XL/XC */
+#define AUTOEXP_HORZ_FIX		0x80000000ul	/* Mobility */
+#define SCRATCH_REG0		IOPortTag(0x10u, 0x20u)
+#define SCRATCH_REG1		IOPortTag(0x11u, 0x21u)
+/*	BIOS_BASE_SEGMENT		0x0000007ful */	/* As above */
+/*	?				0x00000f80ul */
+#define BIOS_INIT_DAC_SUBTYPE		0x0000f000ul
+/*	?				0xffff0000ul */
+#define SCRATCH_REG2		BlockIOTag(0x22u)	/* LT */
+#define SCRATCH_REG3		BlockIOTag(0x23u)	/* GTPro */
+#define CLOCK_CNTL		IOPortTag(0x12u, 0x24u)
+#define CLOCK_BIT			0x00000004ul	/* For ICS2595 */
+#define CLOCK_PULSE			0x00000008ul	/* For ICS2595 */
+#define CLOCK_SELECT			0x0000000ful
+#define CLOCK_DIVIDER			0x00000030ul
+#define CLOCK_STROBE			0x00000040ul
+#define CLOCK_DATA			0x00000080ul
+/*	?				0x00000100ul */
+#define PLL_WR_EN			0x00000200ul	/* For internal PLL */
+#define PLL_ADDR			0x0000fc00ul	/* For internal PLL */
+#define PLL_DATA			0x00ff0000ul	/* For internal PLL */
+/*	?				0xff000000ul */
+#define CONFIG_STAT64_1		BlockIOTag(0x25u)	/* GTPro */
+#define CFG_SUBSYS_DEV_ID		0x000000fful
+#define CFG_SUBSYS_VEN_ID		0x00ffff00ul
+/*	?				0x1f000000ul */
+#define CFG_DIMM_TYPE			0xe0000000ul
+#define CFG_PCI_SUBSYS_DEV_ID		0x0000fffful	/* XC/XL */
+#define CFG_PCI_SUBSYS_VEN_ID		0xffff0000ul	/* XC/XL */
+#define CONFIG_STAT64_2		BlockIOTag(0x26u)	/* GTPro */
+#define CFG_DIMM_TYPE_3			0x00000001ul
+/*	?				0x0000001eul */
+#define CFG_ROMWRTEN			0x00000020ul
+#define CFG_AGPVCOGAIN			0x000000c0ul
+#define CFG_PCI_TYPE			0x00000100ul
+#define CFG_AGPSKEW			0x00000e00ul
+#define CFG_X1CLKSKEW			0x00007000ul
+#define CFG_PANEL_ID_P			0x000f8000ul	/* LTPro */
+/*	?				0x00100000ul */
+#define CFG_PREFETCH_EN			0x00200000ul
+#define CFG_ID_DISABLE			0x00400000ul
+#define CFG_PRE_TESTEN			0x00800000ul
+/*	?				0x01000000ul */
+#define CFG_PCI5VEN			0x02000000ul	/* LTPro */
+#define CFG_VGA_DISABLE			0x04000000ul
+#define CFG_ENINTB			0x08000000ul
+/*	?				0x10000000ul */
+#define CFG_ROM_REMAP_2			0x20000000ul
+#define CFG_IDSEL			0x40000000ul
+/*	?				0x80000000ul */
+#define TV_OUT_DATA		BlockIOTag(0x27u)	/* LTPro */
+#define BUS_CNTL		IOPortTag(0x13u, 0x28u)
+#define BUS_WS				0x0000000ful
+#define BUS_DBL_RESYNC			0x00000001ul	/* VTB/GTB/LT */
+#define BUS_MSTR_RESET			0x00000002ul	/* VTB/GTB/LT */
+#define BUS_FLUSH_BUF			0x00000004ul	/* VTB/GTB/LT */
+#define BUS_STOP_REQ_DIS		0x00000008ul	/* VTB/GTB/LT */
+#define BUS_ROM_WS			0x000000f0ul
+#define BUS_APER_REG_DIS		0x00000010ul	/* VTB/GTB/LT */
+#define BUS_EXTRA_PIPE_DIS		0x00000020ul	/* VTB/GTB/LT */
+#define BUS_MASTER_DIS			0x00000040ul	/* VTB/GTB/LT */
+#define BUS_ROM_WRT_EN			0x00000080ul	/* GTPro */
+#define BUS_ROM_PAGE			0x00000f00ul
+#define BUS_MINOR_REV_ID		0x00000700ul	/* LTPro */
+/*		First silicom - Prototype (A11)	0x00000000ul */
+/*		Metal mask spin (A12 & A13)	0x00000100ul */
+/*		All layer spin (A21)		0x00000200ul */
+/*		Fast metal spin (A22) - Prod.	0x00000300ul */
+/*		All layer spin (A31)		0x00000700ul */
+/*	?				0x00000800ul */	/* LTPro */
+#define BUS_CHIP_HIDDEN_REV		0x00000300ul	/* XC/XL */
+/*	?				0x00001c00ul */	/* XC/XL */
+#define BUS_ROM_DIS			0x00001000ul
+#define BUS_IO_16_EN			0x00002000ul	/* GX */
+#define BUS_PCI_READ_RETRY_EN		0x00002000ul	/* VTB/GTB/LT */
+#define BUS_DAC_SNOOP_EN		0x00004000ul
+#define BUS_PCI_RETRY_EN		0x00008000ul	/* VT/GT */
+#define BUS_PCI_WRT_RETRY_EN		0x00008000ul	/* VTB/GTB/LT */
+#define BUS_FIFO_WS			0x000f0000ul