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| author | nick <nick@b3059339-0415-0410-9bf9-f77b7e298cf2> | 2002-01-30 08:47:44 +0000 |
|---|---|---|
| committer | nick <nick@b3059339-0415-0410-9bf9-f77b7e298cf2> | 2002-01-30 08:47:44 +0000 |
| commit | 4181bcf08e7f0e35c657c93211a131db002ea4af (patch) | |
| tree | 64a875415a3c128312bf6ebfb3fe059ac5202987 /vidix | |
| parent | 6454ae3740f22fa9975dbce96a7ac51addbd31c7 (diff) | |
| download | mpv-4181bcf08e7f0e35c657c93211a131db002ea4af.tar.bz2 mpv-4181bcf08e7f0e35c657c93211a131db002ea4af.tar.xz | |
Correcting pointers on second buffer
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@4413 b3059339-0415-0410-9bf9-f77b7e298cf2
Diffstat (limited to 'vidix')
| -rw-r--r-- | vidix/drivers/radeon_vid.c | 35 |
1 files changed, 23 insertions, 12 deletions
diff --git a/vidix/drivers/radeon_vid.c b/vidix/drivers/radeon_vid.c index 18a7962f55..e85208d25e 100644 --- a/vidix/drivers/radeon_vid.c +++ b/vidix/drivers/radeon_vid.c @@ -53,7 +53,6 @@ typedef struct bes_registers_s uint32_t p3_x_start_end; uint32_t base_addr; uint32_t vid_buf0_base_adrs; - /* These ones are for auto flip: maybe in the future */ uint32_t vid_buf1_base_adrs; uint32_t vid_buf2_base_adrs; uint32_t vid_buf3_base_adrs; @@ -1051,25 +1050,37 @@ int vixPlaybackOff( void ) int vixPlaybackFrameSelect(unsigned frame) { - uint32_t off0,off1,off2; -/* if(!besr.double_buff) return; */ + uint32_t off[6]; + /* + buf3-5 always should point onto second buffer for better + deinterlacing and TV-in + */ if(frame%2) { - off0 = besr.vid_buf3_base_adrs; - off1 = besr.vid_buf4_base_adrs; - off2 = besr.vid_buf5_base_adrs; + off[0] = besr.vid_buf3_base_adrs; + off[1] = besr.vid_buf4_base_adrs; + off[2] = besr.vid_buf5_base_adrs; + off[3] = besr.vid_buf0_base_adrs; + off[4] = besr.vid_buf1_base_adrs; + off[5] = besr.vid_buf2_base_adrs; } else { - off0 = besr.vid_buf0_base_adrs; - off1 = besr.vid_buf1_base_adrs; - off2 = besr.vid_buf2_base_adrs; + off[0] = besr.vid_buf0_base_adrs; + off[1] = besr.vid_buf1_base_adrs; + off[2] = besr.vid_buf2_base_adrs; + off[3] = besr.vid_buf3_base_adrs; + off[4] = besr.vid_buf4_base_adrs; + off[5] = besr.vid_buf5_base_adrs; } OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); - OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); - OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); - OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); + OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); + OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); + OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); + OUTREG(OV0_VID_BUF0_BASE_ADRS, off[3]); + OUTREG(OV0_VID_BUF1_BASE_ADRS, off[4]); + OUTREG(OV0_VID_BUF2_BASE_ADRS, off[5]); OUTREG(OV0_REG_LOAD_CNTL, 0); if(__verbose > 1) radeon_vid_dump_regs(); return 0; |