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authorfaust3 <faust3@b3059339-0415-0410-9bf9-f77b7e298cf2>2004-10-09 13:13:28 +0000
committerfaust3 <faust3@b3059339-0415-0410-9bf9-f77b7e298cf2>2004-10-09 13:13:28 +0000
commitfd60a3de4b7b713bab6fbbd915ea05f87c2e628e (patch)
tree466bfaf35d1c0eaf672149c4dfd889639cd95f37 /vidix/drivers/radeon_vid.c
parente5b4b495c38856a740dd2fcbbc030b87218eb8fc (diff)
downloadmpv-fd60a3de4b7b713bab6fbbd915ea05f87c2e628e.tar.bz2
mpv-fd60a3de4b7b713bab6fbbd915ea05f87c2e628e.tar.xz
correct scaling when the screen resolution is smaller than the flat panel resolution
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@13595 b3059339-0415-0410-9bf9-f77b7e298cf2
Diffstat (limited to 'vidix/drivers/radeon_vid.c')
-rw-r--r--vidix/drivers/radeon_vid.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/vidix/drivers/radeon_vid.c b/vidix/drivers/radeon_vid.c
index 09b4a18543..b0cb77f208 100644
--- a/vidix/drivers/radeon_vid.c
+++ b/vidix/drivers/radeon_vid.c
@@ -309,6 +309,19 @@ static uint32_t radeon_get_yres( void )
return yres + 1;
}
+/* get flat panel x resolution*/
+static uint32_t radeon_get_fp_xres( void ){
+ uint32_t xres=(INREG(FP_HORZ_STRETCH)&0x00fff000)>>16;
+ xres=(xres+1)*8;
+ return xres;
+}
+
+/* get flat panel y resolution*/
+static uint32_t radeon_get_fp_yres( void ){
+ uint32_t yres=(INREG(FP_VERT_STRETCH)&0x00fff000)>>12;
+ return yres+1;
+}
+
static void radeon_wait_vsync(void)
{
int i;
@@ -1292,6 +1305,7 @@ static void radeon_vid_dump_regs( void )
printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off);
printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size);
printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp());
+ printf(RADEON_MSG"flatpanel size: %ux%u\n",radeon_get_fp_xres(),radeon_get_fp_yres());
printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n");
for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name));
@@ -1569,7 +1583,12 @@ static int radeon_vid_init_video( vidix_playback_t *config )
if(radeon_is_dbl_scan()) dest_h *= 2;
besr.dest_bpp = radeon_vid_get_dbpp();
besr.fourcc = config->fourcc;
- besr.v_inc = (src_h << 20) / dest_h;
+
+ /* flat panel */
+ if(INREG(FP_VERT_STRETCH)&VERT_STRETCH_ENABLE){
+ besr.v_inc = (src_h * radeon_get_yres() / radeon_get_fp_yres() << 20) / dest_h;
+ }
+ else besr.v_inc = (src_h << 20) / dest_h;
if(radeon_is_interlace()) besr.v_inc *= 2;
h_inc = (src_w << 12) / dest_w;