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| author | arpi_esp <arpi_esp@b3059339-0415-0410-9bf9-f77b7e298cf2> | 2001-05-02 00:29:16 +0000 |
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| committer | arpi_esp <arpi_esp@b3059339-0415-0410-9bf9-f77b7e298cf2> | 2001-05-02 00:29:16 +0000 |
| commit | cd6ae34f71a50657b0e6adb23cca43b2e12eb77c (patch) | |
| tree | 8e7fd72159d05bb26a218ed2a7e23eeaa13c9d34 /libvo/fastmemcpy.h | |
| parent | 31a47d368fc2cae955b252e5827f1b7a6f5e7c9d (diff) | |
| download | mpv-cd6ae34f71a50657b0e6adb23cca43b2e12eb77c.tar.bz2 mpv-cd6ae34f71a50657b0e6adb23cca43b2e12eb77c.tar.xz | |
SSE+2.2.x+SIGILL bug fixed - SSE code disabled...
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@686 b3059339-0415-0410-9bf9-f77b7e298cf2
Diffstat (limited to 'libvo/fastmemcpy.h')
| -rw-r--r-- | libvo/fastmemcpy.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/libvo/fastmemcpy.h b/libvo/fastmemcpy.h index fe65a5fdb5..b6dcb38f45 100644 --- a/libvo/fastmemcpy.h +++ b/libvo/fastmemcpy.h @@ -4,6 +4,13 @@ #ifdef USE_FASTMEMCPY #include <stddef.h> +// Enable this code, if SSE version works (faster) for you! +#if 0 +#ifdef HAVE_SSE +#define FASTMEMCPY_SSE +#endif +#endif + /* This part of code was taken by from Linux-2.4.3 and slightly modified for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned @@ -54,7 +61,7 @@ If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru. #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX ) #undef HAVE_MMX1 -#if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE) +#if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(FASTMEMCPY_SSE) /* means: mmx v.1. Note: Since we added alignment of destinition it speedups of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus standard (non MMX-optimized) version. @@ -82,7 +89,7 @@ __asm__ __volatile__(\ : "memory");\ } -#ifdef HAVE_SSE +#ifdef FASTMEMCPY_SSE #define MMREG_SIZE 16 #else #define MMREG_SIZE 8 @@ -141,7 +148,7 @@ inline static void * fast_memcpy(void * to, const void * from, size_t len) perform reading and writing to be multiple to a number of processor's decoders, but it's not always possible. */ -#ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */ +#ifdef FASTMEMCPY_SSE /* Only P3 (may be Cyrix3) */ if(((unsigned long)from) & 15) /* if SRC is misaligned */ for(; i>0; i--) @@ -215,7 +222,7 @@ inline static void * fast_memcpy(void * to, const void * from, size_t len) * is needed to become ordered again. */ __asm__ __volatile__ ("sfence":::"memory"); #endif -#ifndef HAVE_SSE +#ifndef FASTMEMCPY_SSE /* enables to use FPU */ __asm__ __volatile__ (EMMS:::"memory"); #endif |