A lot of VE related improvements and code cleanup

git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@1916 b3059339-0415-0410-9bf9-f77b7e298cf2

2 files changed, 598 insertions, 282 deletions

diff --git a/drivers/radeon/radeon.h b/drivers/radeon/radeon.h
index efe1967db6..194a42cbdf 100644
--- a/drivers/radeon/radeon.h
+++ b/drivers/radeon/radeon.h
@@ -9,17 +9,49 @@
 #define PCI_DEVICE_ID_RADEON_QG		0x5147
 #define PCI_DEVICE_ID_RADEON_QY		0x5159
 #define PCI_DEVICE_ID_RADEON_QZ		0x515A
+#define PCI_DEVICE_ID_RADEON_LY		0x4C59
+#define PCI_DEVICE_ID_RADEON_LZ		0x4C5A
+#define PCI_DEVICE_ID_RADEON_LW		0x4C57
 
 #define RADEON_REGSIZE			0x4000
 
 
 #define MM_INDEX                               0x0000  
+/* MM_INDEX bit constants */
+#	define MM_APER                         0x80000000
 #define MM_DATA                                0x0004  
 #define BUS_CNTL                               0x0030  
+/* BUS_CNTL bit constants */
+#	define BUS_DBL_RESYNC                  0x00000001
+#	define BUS_MSTR_RESET                  0x00000002
+#	define BUS_FLUSH_BUF                   0x00000004
+#	define BUS_STOP_REQ_DIS                0x00000008
+#	define BUS_ROTATION_DIS                0x00000010
+#	define BUS_MASTER_DIS                  0x00000040
+#	define BUS_ROM_WRT_EN                  0x00000080
+#	define BUS_DIS_ROM                     0x00001000
+#	define BUS_PCI_READ_RETRY_EN           0x00002000
+#	define BUS_AGP_AD_STEPPING_EN          0x00004000
+#	define BUS_PCI_WRT_RETRY_EN            0x00008000
+#	define BUS_MSTR_RD_MULT                0x00100000
+#	define BUS_MSTR_RD_LINE                0x00200000
+#	define BUS_SUSPEND                     0x00400000
+#	define LAT_16X                         0x00800000
+#	define BUS_RD_DISCARD_EN               0x01000000
+#	define BUS_RD_ABORT_EN                 0x02000000
+#	define BUS_MSTR_WS                     0x04000000
+#	define BUS_PARKING_DIS                 0x08000000
+#	define BUS_MSTR_DISCONNECT_EN          0x10000000
+#	define BUS_WRT_BURST                   0x20000000
+#	define BUS_READ_BURST                  0x40000000
+#	define BUS_RDY_READ_DLY                0x80000000
 #define HI_STAT                                0x004C  
 #define BUS_CNTL1                              0x0034
+#	define BUS_WAIT_ON_LOCK_EN             (1 << 4)
 #define I2C_CNTL_1			       0x0094  
 #define CONFIG_CNTL                            0x00E0  
+/* CONFIG_CNTL bit constants */
+#	define CFG_VGA_RAM_EN                  0x00000100
 #define CONFIG_MEMSIZE                         0x00F8  
 #define CONFIG_APER_0_BASE                     0x0100  
 #define CONFIG_APER_1_BASE                     0x0104  
@@ -30,6 +62,14 @@
 #define PAD_CTLR_STRENGTH                      0x0168  
 #define PAD_CTLR_UPDATE                        0x016C
 #define AGP_CNTL                               0x0174
+#	define AGP_APER_SIZE_256MB             (0x00 << 0)
+#	define AGP_APER_SIZE_128MB             (0x20 << 0)
+#	define AGP_APER_SIZE_64MB              (0x30 << 0)
+#	define AGP_APER_SIZE_32MB              (0x38 << 0)
+#	define AGP_APER_SIZE_16MB              (0x3c << 0)
+#	define AGP_APER_SIZE_8MB               (0x3e << 0)
+#	define AGP_APER_SIZE_4MB               (0x3f << 0)
+#	define AGP_APER_SIZE_MASK              (0x3f << 0)
 #define BM_STATUS                              0x0160
 #define CAP0_TRIG_CNTL			       0x0950
 #define VIPH_CONTROL			       0x0C40
@@ -63,6 +103,10 @@
 #define PMI_DATA                               0x0F57  
 #define AGP_CAP_ID                             0x0F58  
 #define AGP_STATUS                             0x0F5C  
+#	define AGP_1X_MODE                     0x01
+#	define AGP_2X_MODE                     0x02
+#	define AGP_4X_MODE                     0x04
+#	define AGP_MODE_MASK                   0x07
 #define AGP_COMMAND                            0x0F60  
 #define AIC_CTRL                               0x01D0
 #define AIC_STAT                               0x01D4
@@ -72,8 +116,62 @@
 #define AIC_TLB_ADDR                           0x01E4  
 #define AIC_TLB_DATA                           0x01E8  
 #define DAC_CNTL                               0x0058  
+/* DAC_CNTL bit constants */   
+#	define DAC_8BIT_EN                     0x00000100
+#	define DAC_4BPP_PIX_ORDER              0x00000200
+#	define DAC_CRC_EN                      0x00080000
+#	define DAC_MASK_ALL		       (0xff << 24)
+#	define DAC_VGA_ADR_EN		       (1 << 13)
+#	define DAC_RANGE_CNTL		       (3 << 0)
+#	define DAC_BLANKING		       (1 << 2)
+#define DAC_CNTL2                              0x007c
+/* DAC_CNTL2 bit constants */   
+#	define DAC2_DAC_CLK_SEL                (1 <<  0)
+#	define DAC2_DAC2_CLK_SEL               (1 <<  1)
+#	define DAC2_PALETTE_ACC_CTL            (1 <<  5)
+#define TV_DAC_CNTL                            0x088c
+/* TV_DAC_CNTL bit constants */   
+#	define TV_DAC_STD_MASK                 0x0300
+#	define TV_DAC_RDACPD                   (1 <<  24)
+#	define TV_DAC_GDACPD                   (1 <<  25)
+#	define TV_DAC_BDACPD                   (1 <<  26)
 #define CRTC_GEN_CNTL                          0x0050  
+/* CRTC_GEN_CNTL bit constants */
+#	define CRTC_DBL_SCAN_EN                0x00000001
+#	define CRTC_INTERLACE_EN               (1 << 1)
+#	define CRTC_CSYNC_EN                   (1 << 4)
+#	define CRTC_CUR_EN                     0x00010000
+#	define CRTC_CUR_MODE_MASK              (7 << 17)
+#	define CRTC_ICON_EN                    (1 << 20)
+#	define CRTC_EXT_DISP_EN      	       (1 << 24)
+#	define CRTC_EN			       (1 << 25)
+#	define CRTC_DISP_REQ_EN_B              (1 << 26)
+#define CRTC2_GEN_CNTL                         0x03f8
+/* CRTC2_GEN_CNTL bit constants */
+#	define CRTC2_DBL_SCAN_EN               (1 <<  0)
+#	define CRTC2_INTERLACE_EN              (1 <<  1)
+#	define CRTC2_SYNC_TRISTAT              (1 <<  4)
+#	define CRTC2_HSYNC_TRISTAT             (1 <<  5)
+#	define CRTC2_VSYNC_TRISTAT             (1 <<  6)
+#	define CRTC2_CRT2_ON                   (1 <<  7)
+#	define CRTC2_ICON_EN                   (1 << 15)
+#	define CRTC2_CUR_EN                    (1 << 16)
+#	define CRTC2_CUR_MODE_MASK             (7 << 20)
+#	define CRTC2_DISP_DIS                  (1 << 23)
+#	define CRTC2_EN                        (1 << 25)
+#	define CRTC2_DISP_REQ_EN_B             (1 << 26)
+#	define CRTC2_HSYNC_DIS                 (1 << 28)
+#	define CRTC2_VSYNC_DIS                 (1 << 29)
 #define MEM_CNTL                               0x0140  
+/* MEM_CNTL bit constants */
+#	define MEM_CTLR_STATUS_IDLE            0x00000000
+#	define MEM_CTLR_STATUS_BUSY            0x00100000
+#	define MEM_SEQNCR_STATUS_IDLE          0x00000000
+#	define MEM_SEQNCR_STATUS_BUSY          0x00200000
+#	define MEM_ARBITER_STATUS_IDLE         0x00000000
+#	define MEM_ARBITER_STATUS_BUSY         0x00400000
+#	define MEM_REQ_UNLOCK                  0x00000000
+#	define MEM_REQ_LOCK                    0x00800000
 #define EXT_MEM_CNTL                           0x0144  
 #define MC_AGP_LOCATION                        0x014C  
 #define MEM_IO_CNTL_A0                         0x0178  
@@ -93,6 +191,10 @@
 #define HDP_DEBUG                              0x0138  
 #define SW_SEMAPHORE                           0x013C  
 #define SURFACE_CNTL                           0x0B00  
+/* SURFACE_CNTL bit constants */
+#	define SURF_TRANSLATION_DIS	       (1 << 8)
+#	define NONSURF_AP0_SWP_16BPP	       (1 << 20)
+#	define NONSURF_AP0_SWP_32BPP	       (2 << 20)
 #define SURFACE0_LOWER_BOUND                   0x0B04  
 #define SURFACE1_LOWER_BOUND                   0x0B14  
 #define SURFACE2_LOWER_BOUND                   0x0B24  
@@ -121,7 +223,23 @@
 #define SURFACE_ACCESS_CLR                     0x0BFC  
 #define GEN_INT_CNTL                           0x0040  
 #define GEN_INT_STATUS                         0x0044  
+#	define VSYNC_INT_AK                    (1 <<  2)
+#	define VSYNC_INT                       (1 <<  2)
 #define CRTC_EXT_CNTL                          0x0054
+/* CRTC_EXT_CNTL bit constants */
+#	define CRTC_VGA_XOVERSCAN              (1 <<  0)
+#	define VGA_ATI_LINEAR                  0x00000008
+#	define VGA_128KAP_PAGING               0x00000010
+#	define XCRT_CNT_EN		       (1 << 6)
+#	define CRTC_HSYNC_DIS		       (1 << 8)
+#	define CRTC_VSYNC_DIS		       (1 << 9)
+#	define CRTC_DISPLAY_DIS		       (1 << 10)
+#	define CRTC_SYNC_TRISTAT               (1 << 11)
+#	define CRTC_CRT_ON                     (1 << 15)
+#define CRTC_EXT_CNTL_DPMS_BYTE                0x0055
+#	define CRTC_HSYNC_DIS_BYTE             (1 <<  0)
+#	define CRTC_VSYNC_DIS_BYTE             (1 <<  1)
+#	define CRTC_DISPLAY_DIS_BYTE           (1 <<  2)
 #define RB3D_CNTL			       0x1C3C  
 #define WAIT_UNTIL                             0x1720  
 #define ISYNC_CNTL                             0x1724  
@@ -131,6 +249,15 @@
 #define RBBM_CNTL                              0x00EC  
 #define RBBM_CNTL_alt_1                        0x0E44  
 #define RBBM_SOFT_RESET                        0x00F0  
+/* RBBM_SOFT_RESET bit constants */
+#	define SOFT_RESET_CP          	       (1 <<  0)
+#	define SOFT_RESET_HI           	       (1 <<  1)
+#	define SOFT_RESET_SE           	       (1 <<  2)
+#	define SOFT_RESET_RE           	       (1 <<  3)
+#	define SOFT_RESET_PP           	       (1 <<  4)
+#	define SOFT_RESET_E2           	       (1 <<  5)
+#	define SOFT_RESET_RB           	       (1 <<  6)
+#	define SOFT_RESET_HDP          	       (1 <<  7)
 #define RBBM_SOFT_RESET_alt_1                  0x0E48  
 #define NQWAIT_UNTIL                           0x0E50  
 #define RBBM_DEBUG                             0x0E6C
@@ -139,6 +266,9 @@
 #define RBBM_CMDFIFO_DATAH                     0x0E78  
 #define RBBM_CMDFIFO_STAT                      0x0E7C  
 #define CRTC_STATUS                            0x005C  
+/* CRTC_STATUS bit constants */
+#	define CRTC_VBLANK                     0x00000001
+#	define CRTC_VBLANK_SAVE               (1 <<  1)
 #define GPIO_VGA_DDC                           0x0060  
 #define GPIO_DVI_DDC                           0x0064  
 #define GPIO_MONID                             0x0068  
@@ -146,17 +276,69 @@
 #define PALETTE_DATA                           0x00B4  
 #define PALETTE_30_DATA                        0x00B8  
 #define CRTC_H_TOTAL_DISP                      0x0200  
+#	define CRTC_H_TOTAL                    (0x03ff << 0)
+#	define CRTC_H_TOTAL_SHIFT              0
+#	define CRTC_H_DISP                     (0x01ff << 16)
+#	define CRTC_H_DISP_SHIFT               16
+#define CRTC2_H_TOTAL_DISP                     0x0300
+#	define CRTC2_H_TOTAL                   (0x03ff << 0)
+#	define CRTC2_H_TOTAL_SHIFT             0
+#	define CRTC2_H_DISP                    (0x01ff << 16)
+#	define CRTC2_H_DISP_SHIFT              16
 #define CRTC_H_SYNC_STRT_WID                   0x0204  
+#	define CRTC_H_SYNC_STRT_PIX            (0x07  <<  0)
+#	define CRTC_H_SYNC_STRT_CHAR           (0x3ff <<  3)
+#	define CRTC_H_SYNC_STRT_CHAR_SHIFT     3
+#	define CRTC_H_SYNC_WID                 (0x3f  << 16)
+#	define CRTC_H_SYNC_WID_SHIFT           16
+#	define CRTC_H_SYNC_POL                 (1     << 23)
+#define CRTC2_H_SYNC_STRT_WID                  0x0304
+#	define CRTC2_H_SYNC_STRT_PIX           (0x07  <<  0)
+#	define CRTC2_H_SYNC_STRT_CHAR          (0x3ff <<  3)
+#	define CRTC2_H_SYNC_STRT_CHAR_SHIFT    3
+#	define CRTC2_H_SYNC_WID                (0x3f  << 16)
+#	define CRTC2_H_SYNC_WID_SHIFT          16
+#	define CRTC2_H_SYNC_POL                (1     << 23)
 #define CRTC_V_TOTAL_DISP                      0x0208  
+#	define CRTC_V_TOTAL                    (0x07ff << 0)
+#	define CRTC_V_TOTAL_SHIFT              0
+#	define CRTC_V_DISP                     (0x07ff << 16)
+#	define CRTC_V_DISP_SHIFT               16
+#define CRTC2_V_TOTAL_DISP                     0x0308
+#	define CRTC2_V_TOTAL                   (0x07ff << 0)
+#	define CRTC2_V_TOTAL_SHIFT             0
+#	define CRTC2_V_DISP                    (0x07ff << 16)
+#	define CRTC2_V_DISP_SHIFT              16
 #define CRTC_V_SYNC_STRT_WID                   0x020C  
+#	define CRTC_V_SYNC_STRT                (0x7ff <<  0)
+#	define CRTC_V_SYNC_STRT_SHIFT          0
+#	define CRTC_V_SYNC_WID                 (0x1f  << 16)
+#	define CRTC_V_SYNC_WID_SHIFT           16
+#	define CRTC_V_SYNC_POL                 (1     << 23)
+#define CRTC2_V_SYNC_STRT_WID                  0x030C
+#	define CRTC2_V_SYNC_STRT               (0x7ff <<  0)
+#	define CRTC2_V_SYNC_STRT_SHIFT         0
+#	define CRTC2_V_SYNC_WID                (0x1f  << 16)
+#	define CRTC2_V_SYNC_WID_SHIFT          16
+#	define CRTC2_V_SYNC_POL                (1     << 23)
 #define CRTC_VLINE_CRNT_VLINE                  0x0210  
+#	define CRTC_CRNT_VLINE_MASK            (0x7ff << 16)
+#define CRTC2_VLINE_CRNT_VLINE                 0x0310
 #define CRTC_CRNT_FRAME                        0x0214
+#define CRTC2_CRNT_FRAME                       0x0314
 #define CRTC_GUI_TRIG_VLINE                    0x0218
+#define CRTC2_GUI_TRIG_VLINE                   0x0318
 #define CRTC_DEBUG                             0x021C
+#define CRTC2_DEBUG                            0x031C
 #define CRTC_OFFSET_RIGHT                      0x0220  
 #define CRTC_OFFSET                            0x0224  
+#define CRTC2_OFFSET                           0x0324
 #define CRTC_OFFSET_CNTL                       0x0228  
+#	define CRTC_TILE_EN                    (1 << 15)
+#define CRTC2_OFFSET_CNTL                      0x0328
+#	define CRTC2_TILE_EN                   (1 << 15)
 #define CRTC_PITCH                             0x022C  
+#define CRTC2_PITCH                            0x032C
 #define OVR_CLR                                0x0230  
 #define OVR_WID_LEFT_RIGHT                     0x0234  
 #define OVR_WID_TOP_BOTTOM                     0x0238  
@@ -166,22 +348,68 @@
 #define N_VIF_COUNT                            0x0248  
 #define SNAPSHOT_VIF_COUNT                     0x024C  
 #define FP_CRTC_H_TOTAL_DISP                   0x0250  
+#define FP_CRTC2_H_TOTAL_DISP                  0x0350
 #define FP_CRTC_V_TOTAL_DISP                   0x0254  
+#define FP_CRTC2_V_TOTAL_DISP                  0x0354
 #define CRT_CRTC_H_SYNC_STRT_WID               0x0258
 #define CRT_CRTC_V_SYNC_STRT_WID               0x025C
 #define CUR_OFFSET                             0x0260
 #define CUR_HORZ_VERT_POSN                     0x0264  
 #define CUR_HORZ_VERT_OFF                      0x0268  
+/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
+#	define CUR_LOCK                        0x80000000
 #define CUR_CLR0                               0x026C  
 #define CUR_CLR1                               0x0270  
+#define CUR2_OFFSET                            0x0360
+#define CUR2_HORZ_VERT_POSN                    0x0364
+#define CUR2_HORZ_VERT_OFF                     0x0368
+#	define CUR2_LOCK                       (1 << 31)
+#define CUR2_CLR0                              0x036c
+#define CUR2_CLR1                              0x0370
 #define FP_HORZ_VERT_ACTIVE                    0x0278  
 #define CRTC_MORE_CNTL                         0x027C  
 #define DAC_EXT_CNTL                           0x0280  
 #define FP_GEN_CNTL                            0x0284  
+/* FP_GEN_CNTL bit constants */
+#	define FP_FPON                         (1 <<  0)
+#	define FP_TMDS_EN                      (1 <<  2)
+#	define FP_EN_TMDS                      (1 <<  7)
+#	define FP_DETECT_SENSE                 (1 <<  8)
+#	define FP_SEL_CRTC2                    (1 << 13)
+#	define FP_CRTC_DONT_SHADOW_HPAR        (1 << 15)
+#	define FP_CRTC_DONT_SHADOW_VPAR        (1 << 16)
+#	define FP_CRTC_DONT_SHADOW_HEND        (1 << 17)
+#	define FP_CRTC_USE_SHADOW_VEND         (1 << 18)
+#	define FP_RMX_HVSYNC_CONTROL_EN        (1 << 20)
+#	define FP_DFP_SYNC_SEL                 (1 << 21)
+#	define FP_CRTC_LOCK_8DOT               (1 << 22)
+#	define FP_CRT_SYNC_SEL                 (1 << 23)
+#	define FP_USE_SHADOW_EN                (1 << 24)
+#	define FP_CRT_SYNC_ALT                 (1 << 26)
+#define FP2_GEN_CNTL                           0x0288
+/* FP2_GEN_CNTL bit constants */
+#	define FP2_FPON                        (1 <<  0)
+#	define FP2_TMDS_EN                     (1 <<  2)
+#	define FP2_EN_TMDS                     (1 <<  7)
+#	define FP2_DETECT_SENSE                (1 <<  8)
+#	define FP2_SEL_CRTC2                   (1 << 13)
+#	define FP2_FP_POL                      (1 << 16)
+#	define FP2_LP_POL                      (1 << 17)
+#	define FP2_SCK_POL                     (1 << 18)
+#	define FP2_LCD_CNTL_MASK               (7 << 19)
+#	define FP2_PAD_FLOP_EN                 (1 << 22)
+#	define FP2_CRC_EN                      (1 << 23)
+#	define FP2_CRC_READ_EN                 (1 << 24)
 #define FP_HORZ_STRETCH                        0x028C  
 #define FP_VERT_STRETCH                        0x0290  
 #define FP_H_SYNC_STRT_WID                     0x02C4  
+#define FP_H2_SYNC_STRT_WID                    0x03C4
 #define FP_V_SYNC_STRT_WID                     0x02C8  
+#define FP_V2_SYNC_STRT_WID                    0x03C8
+#define FP_HORZ_STRETCH                        0x028C
+#define FP_HORZ2_STRETCH                       0x038C
+#define FP_VERT_STRETCH                        0x0290
+#define FP_VERT2_STRETCH                       0x0390
 #define AUX_WINDOW_HORZ_CNTL                   0x02D8  
 #define AUX_WINDOW_VERT_CNTL                   0x02DC  
 #define DDA_CONFIG			       0x02e0
@@ -250,6 +478,7 @@
 #define SUBPIC_H_ACCUM_INIT                    0x0584  
 #define SUBPIC_V_ACCUM_INIT                    0x0588  
 #define DISP_MISC_CNTL                         0x0D00  
+#	define SOFT_RESET_GRPH_PP              (1 << 0)
 #define DAC_MACRO_CNTL                         0x0D04  
 #define DISP_PWR_MAN                           0x0D08  
 #define DISP_TEST_DEBUG_CNTL                   0x0D10  
@@ -270,6 +499,8 @@
 #define OV0_GAMMA_3C0_3FF                      0x0D54  
 #define DISP_MERGE_CNTL                        0x0D60  
 #define DISP_OUTPUT_CNTL                       0x0D64  
+#	define DISP_DAC_SOURCE_MASK            0x03
+#	define DISP_DAC_SOURCE_CRTC2           0x01
 #define DISP_LIN_TRANS_GRPH_A                  0x0D80  
 #define DISP_LIN_TRANS_GRPH_B                  0x0D84
 #define DISP_LIN_TRANS_GRPH_C                  0x0D88
@@ -294,6 +525,10 @@
 #define DAC_POS_SYNC_LEVEL                     0x0DD4  
 #define DAC_BLANK_LEVEL                        0x0DD8  
 #define CLOCK_CNTL_INDEX                       0x0008  
+/* CLOCK_CNTL_INDEX bit constants */
+#	define PLL_WR_EN                       0x00000080
+#	define RADEON_PLL_DIV_SEL              (3 << 8)
+#	define RADEON_PLL2_DIV_SEL_MASK        ~(3 << 8)
 #define CLOCK_CNTL_DATA                        0x000C  
 #define CP_RB_CNTL                             0x0704  
 #define CP_RB_BASE                             0x0700  
@@ -354,25 +589,169 @@
 #define SRC_SC_RIGHT                           0x1654  
 #define SRC_SC_BOTTOM                          0x165C  
 #define DP_CNTL                                0x16C0  
+/* DP_CNTL bit constants */
+#	define DST_X_RIGHT_TO_LEFT             0x00000000
+#	define DST_X_LEFT_TO_RIGHT             0x00000001
+#	define DST_Y_BOTTOM_TO_TOP             0x00000000
+#	define DST_Y_TOP_TO_BOTTOM             0x00000002
+#	define DST_X_MAJOR                     0x00000000
+#	define DST_Y_MAJOR                     0x00000004
+#	define DST_X_TILE                      0x00000008
+#	define DST_Y_TILE                      0x00000010
+#	define DST_LAST_PEL                    0x00000020
+#	define DST_TRAIL_X_RIGHT_TO_LEFT       0x00000000
+#	define DST_TRAIL_X_LEFT_TO_RIGHT       0x00000040
+#	define DST_TRAP_FILL_RIGHT_TO_LEFT     0x00000000
+#	define DST_TRAP_FILL_LEFT_TO_RIGHT     0x00000080
+#	define DST_BRES_SIGN                   0x00000100
+#	define DST_HOST_BIG_ENDIAN_EN          0x00000200
+#	define DST_POLYLINE_NONLAST            0x00008000
+#	define DST_RASTER_STALL                0x00010000
+#	define DST_POLY_EDGE                   0x00040000
 #define DP_CNTL_XDIR_YDIR_YMAJOR               0x16D0  
+/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */
+#	define DST_X_MAJOR_S                   0x00000000
+#	define DST_Y_MAJOR_S                   0x00000001
+#	define DST_Y_BOTTOM_TO_TOP_S           0x00000000
+#	define DST_Y_TOP_TO_BOTTOM_S           0x00008000
+#	define DST_X_RIGHT_TO_LEFT_S           0x00000000
+#	define DST_X_LEFT_TO_RIGHT_S           0x80000000
 #define DP_DATATYPE                            0x16C4  
+/* DP_DATATYPE bit constants */
+#	define DST_8BPP                        0x00000002
+#	define DST_15BPP                       0x00000003
+#	define DST_16BPP                       0x00000004
+#	define DST_24BPP                       0x00000005
+#	define DST_32BPP                       0x00000006
+#	define DST_8BPP_RGB332                 0x00000007
+#	define DST_8BPP_Y8                     0x00000008
+#	define DST_8BPP_RGB8                   0x00000009
+#	define DST_16BPP_VYUY422               0x0000000b
+#	define DST_16BPP_YVYU422               0x0000000c
+#	define DST_32BPP_AYUV444               0x0000000e
+#	define DST_16BPP_ARGB4444              0x0000000f
+#	define BRUSH_SOLIDCOLOR                0x00000d00
+#	define SRC_MONO                        0x00000000
+#	define SRC_MONO_LBKGD                  0x00010000
+#	define SRC_DSTCOLOR                    0x00030000
+#	define BYTE_ORDER_MSB_TO_LSB           0x00000000
+#	define BYTE_ORDER_LSB_TO_MSB           0x40000000
+#	define DP_CONVERSION_TEMP              0x80000000
+#	define HOST_BIG_ENDIAN_EN	      (1 << 29)
 #define DP_MIX                                 0x16C8  
+/* DP_MIX bit constants */
+#	define DP_SRC_RECT                     0x00000200
+#	define DP_SRC_HOST                     0x00000300
+#	define DP_SRC_HOST_BYTEALIGN           0x00000400
 #define DP_WRITE_MSK                           0x16CC  
 #define DP_XOP                                 0x17F8  
 #define CLR_CMP_CLR_SRC                        0x15C4
 #define CLR_CMP_CLR_DST                        0x15C8
 #define CLR_CMP_CNTL                           0x15C0
+/* CLR_CMP_CNTL bit constants */
+#	define COMPARE_SRC_FALSE               0x00000000
+#	define COMPARE_SRC_TRUE                0x00000001
+#	define COMPARE_SRC_NOT_EQUAL           0x00000004
+#	define COMPARE_SRC_EQUAL               0x00000005
+#	define COMPARE_SRC_EQUAL_FLIP          0x00000007
+#	define COMPARE_DST_FALSE               0x00000000
+#	define COMPARE_DST_TRUE                0x00000100
+#	define COMPARE_DST_NOT_EQUAL           0x00000400
+#	define COMPARE_DST_EQUAL               0x00000500
+#	define COMPARE_DESTINATION             0x00000000
+#	define COMPARE_SOURCE                  0x01000000
+#	define COMPARE_SRC_AND_DST             0x02000000
 #define CLR_CMP_MSK                            0x15CC  
 #define DSTCACHE_MODE                          0x1710  
 #define DSTCACHE_CTLSTAT                       0x1714  
+/* DSTCACHE_CTLSTAT bit constants */
+#	define RB2D_DC_FLUSH		       (3 << 0)
+#	define RB2D_DC_FLUSH_ALL	       0xf
+#	define RB2D_DC_BUSY		       (1 << 31)
 #define DEFAULT_PITCH_OFFSET                   0x16E0  
 #define DEFAULT_SC_BOTTOM_RIGHT                0x16E8  
+/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
+#	define DEFAULT_SC_RIGHT_MAX	       (0x1fff << 0)
+#	define DEFAULT_SC_BOTTOM_MAX	       (0x1fff << 16)
 #define DP_GUI_MASTER_CNTL                     0x146C  
+/* DP_GUI_MASTER_CNTL bit constants */
+#	define GMC_SRC_PITCH_OFFSET_DEFAULT    0x00000000
+#	define GMC_SRC_PITCH_OFFSET_LEAVE      0x00000001
+#	define GMC_DST_PITCH_OFFSET_DEFAULT    0x00000000
+#	define GMC_DST_PITCH_OFFSET_LEAVE      0x00000002
+#	define GMC_SRC_CLIP_DEFAULT            0x00000000
+#	define GMC_SRC_CLIP_LEAVE              0x00000004
+#	define GMC_DST_CLIP_DEFAULT            0x00000000
+#	define GMC_DST_CLIP_LEAVE              0x00000008
+#	define GMC_BRUSH_8x8MONO               0x00000000
+#	define GMC_BRUSH_8x8MONO_LBKGD         0x00000010
+#	define GMC_BRUSH_8x1MONO               0x00000020
+#	define GMC_BRUSH_8x1MONO_LBKGD         0x00000030
+#	define GMC_BRUSH_1x8MONO               0x00000040
+#	define GMC_BRUSH_1x8MONO_LBKGD         0x00000050
+#	define GMC_BRUSH_32x1MONO              0x00000060
+#	define GMC_BRUSH_32x1MONO_LBKGD        0x00000070
+#	define GMC_BRUSH_32x32MONO             0x00000080
+#	define GMC_BRUSH_32x32MONO_LBKGD       0x00000090
+#	define GMC_BRUSH_8x8COLOR              0x000000a0
+#	define GMC_BRUSH_8x1COLOR              0x000000b0
+#	define GMC_BRUSH_1x8COLOR              0x000000c0
+#	define GMC_BRUSH_SOLID_COLOR           0x000000d0
+#	define GMC_DST_8BPP                    0x00000200
+#	define GMC_DST_15BPP                   0x00000300
+#	define GMC_DST_16BPP                   0x00000400
+#	define GMC_DST_24BPP                   0x00000500
+#	define GMC_DST_32BPP                   0x00000600
+#	define GMC_DST_8BPP_RGB332             0x00000700
+#	define GMC_DST_8BPP_Y8                 0x00000800
+#	define GMC_DST_8BPP_RGB8               0x00000900
+#	define GMC_DST_16BPP_VYUY422           0x00000b00
+#	define GMC_DST_16BPP_YVYU422           0x00000c00
+#	define GMC_DST_32BPP_AYUV444           0x00000e00
+#	define GMC_DST_16BPP_ARGB4444          0x00000f00
+#	define GMC_SRC_MONO                    0x00000000
+#	define GMC_SRC_MONO_LBKGD              0x00001000
+#	define GMC_SRC_DSTCOLOR                0x00003000
+#	define GMC_BYTE_ORDER_MSB_TO_LSB       0x00000000
+#	define GMC_BYTE_ORDER_LSB_TO_MSB       0x00004000
+#	define GMC_DP_CONVERSION_TEMP_9300     0x00008000
+#	define GMC_DP_CONVERSION_TEMP_6500     0x00000000
+#	define GMC_DP_SRC_RECT                 0x02000000
+#	define GMC_DP_SRC_HOST                 0x03000000
+#	define GMC_DP_SRC_HOST_BYTEALIGN       0x04000000
+#	define GMC_3D_FCN_EN_CLR               0x00000000
+#	define GMC_3D_FCN_EN_SET               0x08000000
+#	define GMC_DST_CLR_CMP_FCN_LEAVE       0x00000000
+#	define GMC_DST_CLR_CMP_FCN_CLEAR       0x10000000
+#	define GMC_AUX_CLIP_LEAVE              0x00000000
+#	define GMC_AUX_CLIP_CLEAR              0x20000000
+#	define GMC_WRITE_MASK_LEAVE            0x00000000
+#	define GMC_WRITE_MASK_SET              0x40000000
+#	define GMC_CLR_CMP_CNTL_DIS            (1 << 28)
+#	define GMC_SRC_DATATYPE_COLOR	       (3 << 12)
+#	define ROP3_S                	       0x00cc0000
+#	define ROP3_SRCCOPY		       0x00cc0000
+#	define ROP3_P                	       0x00f00000
+#	define ROP3_PATCOPY		       0x00f00000
+#	define DP_SRC_SOURCE_MASK              (7    << 24)
+#	define GMC_BRUSH_NONE                  (15   <<  4)
+#	define DP_SRC_SOURCE_MEMORY	       (2    << 24)
+#	define GMC_BRUSH_SOLIDCOLOR	       0x000000d0
 #define SC_TOP_LEFT                            0x16EC  
 #define SC_BOTTOM_RIGHT                        0x16F0  
 #define SRC_SC_BOTTOM_RIGHT                    0x16F4  
 #define RB2D_DSTCACHE_CTLSTAT		       0x342C
 
+#define RADEON_BASE_CODE                    0x0f0b
+#define RADEON_BIOS_0_SCRATCH               0x0010
+#define RADEON_BIOS_1_SCRATCH               0x0014
+#define RADEON_BIOS_2_SCRATCH               0x0018
+#define RADEON_BIOS_3_SCRATCH               0x001c
+#define RADEON_BIOS_4_SCRATCH               0x0020
+#define RADEON_BIOS_5_SCRATCH               0x0024
+#define RADEON_BIOS_6_SCRATCH               0x0028
+#define RADEON_BIOS_7_SCRATCH               0x002c
+
 
 #define CLK_PIN_CNTL                               0x0001
 #define PPLL_CNTL                                  0x0002
@@ -389,267 +768,16 @@
 #define SCLK_CNTL                                  0x000d
 #define MPLL_CNTL                                  0x000e
 #define MCLK_CNTL                                  0x0012
+/* MCLK_CNTL bit constants */
+#	define FORCEON_MCLKA			   (1 << 16)
+#	define FORCEON_MCLKB         	   	   (1 << 17)
+#	define FORCEON_YCLKA         	      	   (1 << 18)
+#	define FORCEON_YCLKB         	   	   (1 << 19)
+#	define FORCEON_MC            	  	   (1 << 20)
+#	define FORCEON_AIC           	   	   (1 << 21)
 #define AGP_PLL_CNTL                               0x000b
 #define PLL_TEST_CNTL                              0x0013
 
-
-/* MCLK_CNTL bit constants */
-#define FORCEON_MCLKA				   (1 << 16)
-#define FORCEON_MCLKB         		   	   (1 << 17)
-#define FORCEON_YCLKA         	    	   	   (1 << 18)
-#define FORCEON_YCLKB         		   	   (1 << 19)
-#define FORCEON_MC            		   	   (1 << 20)
-#define FORCEON_AIC           		   	   (1 << 21)
-
-
-/* BUS_CNTL bit constants */
-#define BUS_DBL_RESYNC                             0x00000001
-#define BUS_MSTR_RESET                             0x00000002
-#define BUS_FLUSH_BUF                              0x00000004
-#define BUS_STOP_REQ_DIS                           0x00000008
-#define BUS_ROTATION_DIS                           0x00000010
-#define BUS_MASTER_DIS                             0x00000040
-#define BUS_ROM_WRT_EN                             0x00000080
-#define BUS_DIS_ROM                                0x00001000
-#define BUS_PCI_READ_RETRY_EN                      0x00002000
-#define BUS_AGP_AD_STEPPING_EN                     0x00004000
-#define BUS_PCI_WRT_RETRY_EN                       0x00008000
-#define BUS_MSTR_RD_MULT                           0x00100000
-#define BUS_MSTR_RD_LINE                           0x00200000
-#define BUS_SUSPEND                                0x00400000
-#define LAT_16X                                    0x00800000
-#define BUS_RD_DISCARD_EN                          0x01000000
-#define BUS_RD_ABORT_EN                            0x02000000
-#define BUS_MSTR_WS                                0x04000000
-#define BUS_PARKING_DIS                            0x08000000
-#define BUS_MSTR_DISCONNECT_EN                     0x10000000
-#define BUS_WRT_BURST                              0x20000000
-#define BUS_READ_BURST                             0x40000000
-#define BUS_RDY_READ_DLY                           0x80000000
-
-
-/* CLOCK_CNTL_INDEX bit constants */
-#define PLL_WR_EN                                  0x00000080
-
-/* CONFIG_CNTL bit constants */
-#define CFG_VGA_RAM_EN                             0x00000100
-
-/* CRTC_EXT_CNTL bit constants */
-#define VGA_ATI_LINEAR                             0x00000008
-#define VGA_128KAP_PAGING                          0x00000010
-#define	XCRT_CNT_EN				   (1 << 6)
-#define CRTC_HSYNC_DIS				   (1 << 8)
-#define CRTC_VSYNC_DIS				   (1 << 9)
-#define CRTC_DISPLAY_DIS			   (1 << 10)
-
-
-/* DSTCACHE_CTLSTAT bit constants */
-#define RB2D_DC_FLUSH				   (3 << 0)
-#define RB2D_DC_FLUSH_ALL			   0xf
-#define RB2D_DC_BUSY				   (1 << 31)
-
-
-/* CRTC_GEN_CNTL bit constants */
-#define CRTC_DBL_SCAN_EN                           0x00000001
-#define CRTC_CUR_EN                                0x00010000
-#define CRTC_EXT_DISP_EN      			   (1 << 24)
-#define CRTC_EN					   (1 << 25)
-
-/* CRTC_STATUS bit constants */
-#define CRTC_VBLANK                                0x00000001
-
-/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
-#define CUR_LOCK                                   0x80000000
-
-/* DAC_CNTL bit constants */   
-#define DAC_8BIT_EN                                0x00000100
-#define DAC_4BPP_PIX_ORDER                         0x00000200
-#define DAC_CRC_EN                                 0x00080000
-#define DAC_MASK_ALL				   (0xff << 24)
-#define DAC_VGA_ADR_EN				   (1 << 13)
-#define DAC_RANGE_CNTL				   (3 << 0)
-#define DAC_BLANKING				   (1 << 2)
-
-/* GEN_RESET_CNTL bit constants */
-#define SOFT_RESET_GUI                             0x00000001
-#define SOFT_RESET_VCLK                            0x00000100
-#define SOFT_RESET_PCLK                            0x00000200
-#define SOFT_RESET_ECP                             0x00000400
-#define SOFT_RESET_DISPENG_XCLK                    0x00000800
-
-/* MEM_CNTL bit constants */
-#define MEM_CTLR_STATUS_IDLE                       0x00000000
-#define MEM_CTLR_STATUS_BUSY                       0x00100000
-#define MEM_SEQNCR_STATUS_IDLE                     0x00000000
-#define MEM_SEQNCR_STATUS_BUSY                     0x00200000
-#define MEM_ARBITER_STATUS_IDLE                    0x00000000
-#define MEM_ARBITER_STATUS_BUSY                    0x00400000
-#define MEM_REQ_UNLOCK                             0x00000000
-#define MEM_REQ_LOCK                               0x00800000
-
-
-/* SURFACE_CNTL bit constants */
-#define SURF_TRANSLATION_DIS			   (1 << 8)
-#define NONSURF_AP0_SWP_16BPP			   (1 << 20)
-#define NONSURF_AP0_SWP_32BPP			   (2 << 20)
-
-
-/* RBBM_SOFT_RESET bit constants */
-#define SOFT_RESET_CP           		   (1 <<  0)
-#define SOFT_RESET_HI           		   (1 <<  1)
-#define SOFT_RESET_SE           		   (1 <<  2)
-#define SOFT_RESET_RE           		   (1 <<  3)
-#define SOFT_RESET_PP           		   (1 <<  4)
-#define SOFT_RESET_E2           		   (1 <<  5)
-#define SOFT_RESET_RB           		   (1 <<  6)
-#define SOFT_RESET_HDP          		   (1 <<  7)
-
-
-/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
-#define DEFAULT_SC_RIGHT_MAX			   (0x1fff << 0)
-#define DEFAULT_SC_BOTTOM_MAX			   (0x1fff << 16)
-
-/* MM_INDEX bit constants */
-#define MM_APER                                    0x80000000
-
-/* CLR_CMP_CNTL bit constants */
-#define COMPARE_SRC_FALSE                          0x00000000
-#define COMPARE_SRC_TRUE                           0x00000001
-#define COMPARE_SRC_NOT_EQUAL                      0x00000004
-#define COMPARE_SRC_EQUAL                          0x00000005
-#define COMPARE_SRC_EQUAL_FLIP                     0x00000007
-#define COMPARE_DST_FALSE                          0x00000000
-#define COMPARE_DST_TRUE                           0x00000100
-#define COMPARE_DST_NOT_EQUAL                      0x00000400
-#define COMPARE_DST_EQUAL                          0x00000500
-#define COMPARE_DESTINATION                        0x00000000
-#define COMPARE_SOURCE                             0x01000000
-#define COMPARE_SRC_AND_DST                        0x02000000
-
-
-/* DP_CNTL bit constants */
-#define DST_X_RIGHT_TO_LEFT                        0x00000000
-#define DST_X_LEFT_TO_RIGHT                        0x00000001
-#define DST_Y_BOTTOM_TO_TOP                        0x00000000
-#define DST_Y_TOP_TO_BOTTOM                        0x00000002
-#define DST_X_MAJOR                                0x00000000
-#define DST_Y_MAJOR                                0x00000004
-#define DST_X_TILE                                 0x00000008
-#define DST_Y_TILE                                 0x00000010
-#define DST_LAST_PEL                               0x00000020
-#define DST_TRAIL_X_RIGHT_TO_LEFT                  0x00000000
-#define DST_TRAIL_X_LEFT_TO_RIGHT                  0x00000040
-#define DST_TRAP_FILL_RIGHT_TO_LEFT                0x00000000
-#define DST_TRAP_FILL_LEFT_TO_RIGHT                0x00000080
-#define DST_BRES_SIGN                              0x00000100
-#define DST_HOST_BIG_ENDIAN_EN                     0x00000200
-#define DST_POLYLINE_NONLAST                       0x00008000
-#define DST_RASTER_STALL                           0x00010000
-#define DST_POLY_EDGE                              0x00040000
-
-
-/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
-#define DST_X_MAJOR_S                              0x00000000
-#define DST_Y_MAJOR_S                              0x00000001
-#define DST_Y_BOTTOM_TO_TOP_S                      0x00000000
-#define DST_Y_TOP_TO_BOTTOM_S                      0x00008000
-#define DST_X_RIGHT_TO_LEFT_S                      0x00000000
-#define DST_X_LEFT_TO_RIGHT_S                      0x80000000
-
-
-/* DP_DATATYPE bit constants */
-#define DST_8BPP                                   0x00000002
-#define DST_15BPP                                  0x00000003
-#define DST_16BPP                                  0x00000004
-#define DST_24BPP                                  0x00000005
-#define DST_32BPP                                  0x00000006
-#define DST_8BPP_RGB332                            0x00000007
-#define DST_8BPP_Y8                                0x00000008
-#define DST_8BPP_RGB8                              0x00000009
-#define DST_16BPP_VYUY422                          0x0000000b
-#define DST_16BPP_YVYU422                          0x0000000c
-#define DST_32BPP_AYUV444                          0x0000000e
-#define DST_16BPP_ARGB4444                         0x0000000f
-#define BRUSH_SOLIDCOLOR                           0x00000d00
-#define SRC_MONO                                   0x00000000
-#define SRC_MONO_LBKGD                             0x00010000
-#define SRC_DSTCOLOR                               0x00030000
-#define BYTE_ORDER_MSB_TO_LSB                      0x00000000
-#define BYTE_ORDER_LSB_TO_MSB                      0x40000000
-#define DP_CONVERSION_TEMP                         0x80000000
-#define HOST_BIG_ENDIAN_EN			   (1 << 29)
-
-
-/* DP_GUI_MASTER_CNTL bit constants */
-#define GMC_SRC_PITCH_OFFSET_DEFAULT               0x00000000
-#define GMC_SRC_PITCH_OFFSET_LEAVE                 0x00000001
-#define GMC_DST_PITCH_OFFSET_DEFAULT               0x00000000
-#define GMC_DST_PITCH_OFFSET_LEAVE                 0x00000002
-#define GMC_SRC_CLIP_DEFAULT                       0x00000000
-#define GMC_SRC_CLIP_LEAVE                         0x00000004
-#define GMC_DST_CLIP_DEFAULT                       0x00000000
-#define GMC_DST_CLIP_LEAVE                         0x00000008
-#define GMC_BRUSH_8x8MONO                          0x00000000
-#define GMC_BRUSH_8x8MONO_LBKGD                    0x00000010
-#define GMC_BRUSH_8x1MONO                          0x00000020
-#define GMC_BRUSH_8x1MONO_LBKGD                    0x00000030
-#define GMC_BRUSH_1x8MONO                          0x00000040
-#define GMC_BRUSH_1x8MONO_LBKGD                    0x00000050
-#define GMC_BRUSH_32x1MONO                         0x00000060
-#define GMC_BRUSH_32x1MONO_LBKGD                   0x00000070
-#define GMC_BRUSH_32x32MONO                        0x00000080
-#define GMC_BRUSH_32x32MONO_LBKGD                  0x00000090
-#define GMC_BRUSH_8x8COLOR                         0x000000a0
-#define GMC_BRUSH_8x1COLOR                         0x000000b0
-#define GMC_BRUSH_1x8COLOR                         0x000000c0
-#define GMC_BRUSH_SOLID_COLOR                       0x000000d0
-#define GMC_DST_8BPP                               0x00000200
-#define GMC_DST_15BPP                              0x00000300
-#define GMC_DST_16BPP                              0x00000400
-#define GMC_DST_24BPP                              0x00000500
-#define GMC_DST_32BPP                              0x00000600
-#define GMC_DST_8BPP_RGB332                        0x00000700