/*
Driver for S3 Savage Series
Copyright (C) 2004 by Reza Jelveh
Based on the X11 driver and nvidia vid
Thanks to Alex Deucher for Support
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Changes:
2004-11-09
Initial version
To Do:
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>
#include <math.h>
#include "vidix.h"
#include "vidixlib.h"
#include "fourcc.h"
#include "../libdha/libdha.h"
#include "../libdha/pci_ids.h"
#include "../libdha/pci_names.h"
#include "../config.h"
#include "savage_regs.h"
#define VF_STREAMS_ON 0x0001
#define BASE_PAD 0xf
#define FRAMEBUFFER_SIZE 1024*2000*4
/**************************************
S3 streams processor
**************************************/
#define EXT_MISC_CTRL2 0x67
/* New streams */
/* CR67[2] = 1 : enable stream 1 */
#define ENABLE_STREAM1 0x04
/* CR67[1] = 1 : enable stream 2 */
#define ENABLE_STREAM2 0x02
/* mask to clear CR67[2,1] */
#define NO_STREAMS 0xF9
/* CR67[3] = 1 : Mem-mapped regs */
#define USE_MM_FOR_PRI_STREAM 0x08
#define HDM_SHIFT 16
#define HDSCALE_4 (2 << HDM_SHIFT)
#define HDSCALE_8 (3 << HDM_SHIFT)
#define HDSCALE_16 (4 << HDM_SHIFT)
#define HDSCALE_32 (5 << HDM_SHIFT)
#define HDSCALE_64 (6 << HDM_SHIFT)
/* Old Streams */
#define ENABLE_STREAMS_OLD 0x0c
#define NO_STREAMS_OLD 0xf3
/* CR69[0] = 1 : Mem-mapped regs */
#define USE_MM_FOR_PRI_STREAM_OLD 0x01
void SavageStreamsOn(void);
/*
* There are two different streams engines used in the Savage line.
* The old engine is in the 3D, 4, Pro, and Twister.
* The new engine is in the 2000, MX, IX, and Super.
*/
/* streams registers for old engine */
#define PSTREAM_CONTROL_REG 0x8180
#define COL_CHROMA_KEY_CONTROL_REG 0x8184
#define SSTREAM_CONTROL_REG 0x8190
#define CHROMA_KEY_UPPER_BOUND_REG 0x8194
#define SSTREAM_STRETCH_REG 0x8198
#define COLOR_ADJUSTMENT_REG 0x819C
#define BLEND_CONTROL_REG 0x81A0
#define PSTREAM_FBADDR0_REG 0x81C0
#define PSTREAM_FBADDR1_REG 0x81C4
#define PSTREAM_STRIDE_REG 0x81C8
#define DOUBLE_BUFFER_REG 0x81CC
#define SSTREAM_FBADDR0_REG 0x81D0
#define SSTREAM_FBADDR1_REG 0x81D4
#define SSTREAM_STRIDE_REG 0x81D8
#define SSTREAM_VSCALE_REG 0x81E0
#define SSTREAM_VINITIAL_REG 0x81E4
#define SSTREAM_LINES_REG 0x81E8
#define STREAMS_FIFO_REG 0x81EC
#define PSTREAM_WINDOW_START_REG 0x81F0
#define PSTREAM_WINDOW_SIZE_REG 0x81F4
#define SSTREAM_WINDOW_START_REG 0x81F8
#define SSTREAM_WINDOW_SIZE_REG 0x81FC
#define FIFO_CONTROL 0x8200
#define PSTREAM_FBSIZE_REG 0x8300
#define SSTREAM_FBSIZE_REG 0x8304
#define SSTREAM_FBADDR2_REG 0x8308
#define OS_XY(x,y) (((x+1)<<16)|(y+1))
#define OS_WH(x,y) (((x-1)<<16)|(y))
#define PCI_COMMAND_MEM 0x2
#define MAX_FRAMES 3
/**
* @brief Information on PCI device.
*/
pciinfo_t pci_info;
/**
* @brief Unichrome driver colorkey settings.
*/
static vidix_grkey_t savage_grkey;
static int frames[VID_PLAY_MAXFRAMES];
uint8_t *vio;
uint8_t mclk_save[3];
#define outb(reg,val) OUTPORT8(reg,val)
#define inb(reg) INPORT8(reg)
#define outw(reg,val) OUTPORT16(reg,val)
#define inw(reg) INPORT16(reg)
#define outl(reg,val) OUTPORT32(reg,val)
#define inl(reg) INPORT32(reg)
/*
* PCI-Memory IO access macros.
*/
#define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val))
#define VID_RD08(p,i) (((uint8_t *)(p))[(i)])
#define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val))
#define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4])
#ifndef USE_RMW_CYCLES
/*
* Can be used to inhibit READ-MODIFY-WRITE cycles. On by default.
*/
#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")
#undef VID_WR08
#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
#undef VID_RD08
#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
#undef VID_WR16
#define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); })
#undef VID_RD16
#define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; })
#undef VID_WR32
#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); })
#undef VID_RD32
#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
#endif /* USE_RMW_CYCLES */
#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val))
#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
/* from x driver */
#define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr)
#define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr)
#define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr)
#define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val)
#define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val)
#define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val)
#define INREG(addr) VID_RD32(info->control_base, addr)
#define OUTREG(addr,val) VID_WR32(info->control_base, addr, val)
#define INREG8(addr) VID_RD08(info->control_base, addr)
#define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val)
#define INREG16(addr) VID_RD16(info->control_base, addr)
#define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val)
#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1))
void debugout(unsigned int addr, unsigned int val);
struct savage_chip {
volatile uint32_t *PMC; /* general control */
volatile uint32_t *PME; /* multimedia port */
volatile uint32_t *PFB; /* framebuffer control */
volatile uint32_t *PVIDEO; /* overlay control */
volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */
volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */
volatile uint32_t *PRAMIN; /* instance memory */
volatile uint32_t *PRAMHT; /* hash table */
volatile uint32_t *PRAMFC; /* fifo context table */
volatile uint32_t *PRAMRO; /* fifo runout table */
volatile uint32_t *PFIFO; /* fifo control region */
volatile uint32_t *FIFO; /* fifo channels (USER) */
volatile uint32_t *PGRAPH; /* graphics engine */
int arch; /* compatible NV_ARCH_XX define */
unsigned long fbsize; /* framebuffer size */
void (* lock) (struct savage_chip *, int);
};
typedef struct savage_chip savage_chip;
struct savage_info {
unsigned int use_colorkey;
unsigned int colorkey; /* saved xv colorkey*/
unsigned int vidixcolorkey; /*currently used colorkey*/
unsigned int depth;
unsigned int bpp;
unsigned int videoFlags;
unsigned int format;
unsigned int pitch;
unsigned int blendBase;
unsigned int lastKnownPitch;
unsigned int displayWidth, displayHeight;
unsigned int brightness,hue,saturation,contrast;
unsigned int src_w,src_h;
unsigned int drw_w,drw_h; /*scaled width && height*/
unsigned int wx,wy; /*window x && y*/
unsigned int screen_x; /*screen width*/
unsigned int screen_y; /*screen height*/
unsigned long buffer_size; /* size of the image buffer */
struct savage_chip chip; /* NV architecture structure */
void* video_base; /* virtual address of control region */
void* control_base; /* virtual address of fb region */
unsigned long picture_base; /* direct pointer to video picture */
unsigned long picture_offset; /* offset of video picture in frame bu
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