From 6f9cd1674c399bf88ba78e6428e5b6c06ee03eae Mon Sep 17 00:00:00 2001 From: faust3 Date: Tue, 14 Sep 2004 20:43:39 +0000 Subject: workaround for Xorg-6.8 not saving the surface registers on bigendian architectures, patch by Luca Barbato git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@13336 b3059339-0415-0410-9bf9-f77b7e298cf2 --- vidix/drivers/radeon_vid.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'vidix') diff --git a/vidix/drivers/radeon_vid.c b/vidix/drivers/radeon_vid.c index db9b77fa7a..88dab54f85 100644 --- a/vidix/drivers/radeon_vid.c +++ b/vidix/drivers/radeon_vid.c @@ -1316,6 +1316,37 @@ static void radeon_vid_stop_video( void ) static void radeon_vid_display_video( void ) { int bes_flags; +#ifdef WORDS_BIGENDIAN +#if defined(RAGE128) + /* code from gatos */ + { + SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); + OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & + ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); + +// printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, +// INREG(CONFIG_CNTL)); + } +#else + /*code from radeon_video.c*/ + { + SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); +/* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | + RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); +*/ + OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP + | RADEON_NONSURF_AP0_SWP_16BPP)); + +/* + OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); +*/ + } +#endif +#endif + + + radeon_fifo_wait(2); OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); radeon_engine_idle(); -- cgit v1.2.3