From f20d1b16a895f5949851aacd70f24da046164670 Mon Sep 17 00:00:00 2001 From: diego Date: Sat, 17 Mar 2007 21:27:42 +0000 Subject: Move files from radeon/ subdirectory here. git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@22709 b3059339-0415-0410-9bf9-f77b7e298cf2 --- drivers/Makefile | 9 +- drivers/README | 46 - drivers/README.Ati | 121 +++ drivers/README.Matrox | 46 + drivers/generic_math.h | 258 ++++++ drivers/hacking.ati | 313 +++++++ drivers/radeon.h | 2046 +++++++++++++++++++++++++++++++++++++++++ drivers/radeon/README | 121 --- drivers/radeon/generic_math.h | 258 ------ drivers/radeon/hacking | 313 ------- drivers/radeon/radeon.h | 2046 ----------------------------------------- drivers/radeon/radeon_vid.c | 1544 ------------------------------- drivers/radeon/radeon_vid.h | 117 --- drivers/radeon_vid.c | 1544 +++++++++++++++++++++++++++++++ drivers/radeon_vid.h | 117 +++ 15 files changed, 4449 insertions(+), 4450 deletions(-) delete mode 100644 drivers/README create mode 100644 drivers/README.Ati create mode 100644 drivers/README.Matrox create mode 100644 drivers/generic_math.h create mode 100644 drivers/hacking.ati create mode 100644 drivers/radeon.h delete mode 100644 drivers/radeon/README delete mode 100644 drivers/radeon/generic_math.h delete mode 100644 drivers/radeon/hacking delete mode 100644 drivers/radeon/radeon.h delete mode 100644 drivers/radeon/radeon_vid.c delete mode 100644 drivers/radeon/radeon_vid.h create mode 100644 drivers/radeon_vid.c create mode 100644 drivers/radeon_vid.h (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index b9bac2a61e..c298c9b4c4 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -4,16 +4,16 @@ MDIR = /lib/modules/$(VERSION)/misc CFLAGS = -O2 -D__KERNEL__ -DMODULE -I$(KERNEL_INCLUDES) -Wall -include $(KERNEL_INCLUDES)/linux/modversions.h -OBJS = mga_vid.o tdfx_vid.o radeon/radeon_vid.o radeon/rage128_vid.o +OBJS = mga_vid.o tdfx_vid.o radeon_vid.o rage128_vid.o all: $(OBJS) mga_vid_test tdfx_vid_test mga_vid.o: mga_vid.c mga_vid.h tdfx_vid.o: tdfx_vid.c 3dfx.h -radeon/radeon_vid.o: radeon/radeon_vid.c radeon/radeon.h radeon/radeon_vid.h -radeon/rage128_vid.o: radeon/radeon_vid.c radeon/radeon.h radeon/radeon_vid.h +radeon_vid.o: radeon_vid.c radeon.h radeon_vid.h +rage128_vid.o: radeon_vid.c radeon.h radeon_vid.h $(CC) $(CFLAGS) -DRAGE128 -c $< -o $@ -radeon/radeon_vid.o radeon/rage128_vid.o: +radeon_vid.o rage128_vid.o: CFLAGS += -fomit-frame-pointer -fno-strict-aliasing -fno-common -ffast-math %_test: %_test.c @@ -32,7 +32,6 @@ dep depend: clean: rm -f *.o *~ mga_vid_test tdfx_vid_test - rm -f radeon/*.o radeon/*~ distclean: clean diff --git a/drivers/README b/drivers/README deleted file mode 100644 index ae641ab452..0000000000 --- a/drivers/README +++ /dev/null @@ -1,46 +0,0 @@ -The code in this directory is the old mga_vid driver for Linux kernels -prior to 2.6. It does _not_ compile for version 2.6.x. - -For Linux kernel 2.6.x please get the newest version of the 2.6 port from -http://attila.kinali.ch/mga/ - - -mga_vid - MGA G200/G400 YUV Overlay kernel module - - Author: - Aaron Holtzman , Oct 1999 - - Contributions by: - Fredrik Vraalsen - Alan Cox - - WARNING ----- WARNING - -This code messes with your video card and your X server. It will probably -lock up your box, format your hard drive, and cause your brand new G400 -MAX to spout 6 inch flames. You have been warned. - - WARNING ----- WARNING - -What does this code do? - - mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550 - video scaler/overlay unit to perform YUV->RGB colorspace conversion - and arbitrary video scaling. - - mga_vid is also a monster hack. - -How does mga_vid work? - - This kernel module sets up the BES (backend scaler) with appropriate - values based on parameters supplied via ioctl. It also maps a chunk of - video memory into userspace via mmap. This memory is stolen from X - (which may decide to write to it later). The application can then write - image data directly to the framebuffer (if it knows the right padding, - etc). - - -How do I know if mga_vid works on my system? - - There is a test application called mga_vid_test. This test code should - draw some nice 256x256 images for you if all is working well. diff --git a/drivers/README.Ati b/drivers/README.Ati new file mode 100644 index 0000000000..640107f56c --- /dev/null +++ b/drivers/README.Ati @@ -0,0 +1,121 @@ + framebuffer driver for ATI Radeon chipset video boards + ====================================================== + +These files are replacement for linux-2.4.x-ac.y drivers. +To use this driver you should have at least linux-2.4.5-ac.1 +then simply replace linux/drivers/video/radeon* with files +from this directory. +Note: since linux-2.4.10 this driver was moved from -ac to +Linus distribution. + +Alternative way: +~~~~~~~~~~~~~~~~ +Simply type two commands in this directory: +make +make install + +Anyway you should have 'framebuffer support' compiled into linux-kernel +and at least '8bpp packed pixel support' compiled and installed as module. +(But if you plan to use this module with MPlayer you also should have +16bpp, 24bpp and 32bpp pixel support compiled as modules). + + + Radeon video overlay + ==================== + +It was designed for MPlayer and currently can be used only by MPlayer. +It's RGB-YUV BES for Radeon cards (althrough there is experimental +support for Rage128 / Rage128pro chips). + +rage128_vid is contained within radeon_vid.c. As for a Rage128 framebuffer - +use the one from your Linux distribution. + +Installation: +~~~~~~~~~~~~~ + +Simply type two commands in this directory: +make +make install + +Using with MPlayer: +~~~~~~~~~~~~~~~~~~~ + +Currently there is only one way to use ATI's drivers: +mplayer -vo vesa:lvo:/dev/radeon_vid - filename +or +mplayer -vo vesa:lvo:/dev/rage128_vid - filename + +For YV12 formats you can use also: +mplayer -vo mga:/dev/radeon_vid - filename + +but in this case you should load at least radeonfb driver from +this package. + +Configuring: +~~~~~~~~~~~~ + +You can tune some parameters with the following trick: +echo "parameter=value" > /dev/radeon_vid +Example (disables adaptive deinterlacing): +echo "deinterlace=off" > /dev/radeon_vid + +To know more about these parameters - try reading the /dev/radeon_vid file ;) +For example: +cat /dev/radeon_vid + +List of parameters: +~~~~~~~~~~~~~~~~~~~ +If you have Rage128 chip: +brightness=decval (-64:+63) changes brightness +saturation=decval (0:+31) changes saturation 0 == grayscale mode +else - if you have Radeon: +brightness=decval (-1000:+1000) -1000 == black screen +saturation=decval (-1000:+1000) -1000 == grayscaled mode +contrast=decval (-1000:+1000) -1000 == black screen +hue=decval (-1000:+1000) -1000 == +1000 (full circle) + all other values are within this range +Note: 0 is the default value for every parameter on Radeons. +WARNING: This driver violates the rule: "no float in the kernel". +So if you have problems then don't use color correction. + +double_buff=on/off enables/disables double buffering +deinterlace=on/off enables/disables adaptive deinterlacing +deinterlace_pattern=hexval defines deinterlacing pattern + +Driver parameters: +~~~~~~~~~~~~~~~~~~ + +You can use some additional parameters during module loading: +Example: +modprobe radeon_vid swap_fourcc=1 + +List of driver parameters: +~~~~~~~~~~~~~~~~~~~~~~~~~~ +mtrr=1/0 Configures MTRR (if available), default = 1. +swap_fourcc=1/0 Performs byte swapping of passed fourcc. + (It's required for compatibility with -vo mga.) + +To know more about driver parameters execute: +modinfo radeon_vid +or +modinfo rage128_vid + +Note: +~~~~~ +For command line of MPlayer: +You can pass only options with can be recognized by vo_vesa driver. +(Indeed radeon_vid and rage128_vid are stupid things and can only create +video overlay. Mode switching and other adjustments are performed by the +vo_vesa driver. This mean that they use the VESA BIOS as graphics server.) + +Conclusion: +~~~~~~~~~~~ +This stuff (radeon(rage128)_vid) currently doesn't support any standards. + +Full example: +~~~~~~~~~~~~~ +modprobe radeon_vid mtrr=1 +echo "deinterlace_pattern=F0055555" > /dev/radeon_vid +mplayer -vo vesa:lvo:/dev/radeon_vid -fs -zoom -bpp 32 filename + +Enjoy! diff --git a/drivers/README.Matrox b/drivers/README.Matrox new file mode 100644 index 0000000000..ae641ab452 --- /dev/null +++ b/drivers/README.Matrox @@ -0,0 +1,46 @@ +The code in this directory is the old mga_vid driver for Linux kernels +prior to 2.6. It does _not_ compile for version 2.6.x. + +For Linux kernel 2.6.x please get the newest version of the 2.6 port from +http://attila.kinali.ch/mga/ + + +mga_vid - MGA G200/G400 YUV Overlay kernel module + + Author: + Aaron Holtzman , Oct 1999 + + Contributions by: + Fredrik Vraalsen + Alan Cox + + WARNING ----- WARNING + +This code messes with your video card and your X server. It will probably +lock up your box, format your hard drive, and cause your brand new G400 +MAX to spout 6 inch flames. You have been warned. + + WARNING ----- WARNING + +What does this code do? + + mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550 + video scaler/overlay unit to perform YUV->RGB colorspace conversion + and arbitrary video scaling. + + mga_vid is also a monster hack. + +How does mga_vid work? + + This kernel module sets up the BES (backend scaler) with appropriate + values based on parameters supplied via ioctl. It also maps a chunk of + video memory into userspace via mmap. This memory is stolen from X + (which may decide to write to it later). The application can then write + image data directly to the framebuffer (if it knows the right padding, + etc). + + +How do I know if mga_vid works on my system? + + There is a test application called mga_vid_test. This test code should + draw some nice 256x256 images for you if all is working well. diff --git a/drivers/generic_math.h b/drivers/generic_math.h new file mode 100644 index 0000000000..459cf2a276 --- /dev/null +++ b/drivers/generic_math.h @@ -0,0 +1,258 @@ +/* + generic implementation of sin(x) and cos(x) functions. + Specially for Linux. + Licence: GPL + Copyright (C) 2002 Nick Kurshev +*/ + +#ifndef GENERIC_MATH_H +#define GENERIC_MATH_H + +typedef struct _gen_sincos +{ + double x; + double sinx; + double cosx; +}gen_sincos_t; + +static gen_sincos_t g_sincos[201] = { +{ -3.141600e+00, 7.346410e-06, -1.000000e-00 }, +{ -3.110184e+00, -3.140349e-02, -9.995068e-01 }, +{ -3.078768e+00, -6.278333e-02, -9.980272e-01 }, +{ -3.047352e+00, -9.410122e-02, -9.955626e-01 }, +{ -3.015936e+00, -1.253262e-01, -9.921156e-01 }, +{ -2.984520e+00, -1.564276e-01, -9.876894e-01 }, +{ -2.953104e+00, -1.873745e-01, -9.822885e-01 }, +{ -2.921688e+00, -2.181366e-01, -9.759183e-01 }, +{ -2.890272e+00, -2.486833e-01, -9.685848e-01 }, +{ -2.858856e+00, -2.789847e-01, -9.602956e-01 }, +{ -2.827440e+00, -3.090107e-01, -9.510586e-01 }, +{ -2.796024e+00, -3.387318e-01, -9.408830e-01 }, +{ -2.764608e+00, -3.681185e-01, -9.297789e-01 }, +{ -2.733192e+00, -3.971420e-01, -9.177572e-01 }, +{ -2.701776e+00, -4.257736e-01, -9.048297e-01 }, +{ -2.670360e+00, -4.539849e-01, -8.910094e-01 }, +{ -2.638944e+00, -4.817483e-01, -8.763097e-01 }, +{ -2.607528e+00, -5.090362e-01, -8.607451e-01 }, +{ -2.576112e+00, -5.358217e-01, -8.443312e-01 }, +{ -2.544696e+00, -5.620785e-01, -8.270839e-01 }, +{ -2.513280e+00, -5.877805e-01, -8.090204e-01 }, +{ -2.481864e+00, -6.129025e-01, -7.901586e-01 }, +{ -2.450448e+00, -6.374196e-01, -7.705169e-01 }, +{ -2.419032e+00, -6.613076e-01, -7.501148e-01 }, +{ -2.387616e+00, -6.845430e-01, -7.289724e-01 }, +{ -2.356200e+00, -7.071029e-01, -7.071107e-01 }, +{ -2.324784e+00, -7.289649e-01, -6.845511e-01 }, +{ -2.293368e+00, -7.501075e-01, -6.613159e-01 }, +{ -2.261952e+00, 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9.602935e-01 }, +{ 3.141600e-01, 3.090177e-01, 9.510563e-01 }, +{ 3.455760e-01, 3.387387e-01, 9.408805e-01 }, +{ 3.769920e-01, 3.681254e-01, 9.297762e-01 }, +{ 4.084080e-01, 3.971488e-01, 9.177542e-01 }, +{ 4.398240e-01, 4.257802e-01, 9.048266e-01 }, +{ 4.712400e-01, 4.539915e-01, 8.910060e-01 }, +{ 5.026560e-01, 4.817547e-01, 8.763061e-01 }, +{ 5.340720e-01, 5.090425e-01, 8.607414e-01 }, +{ 5.654880e-01, 5.358279e-01, 8.443272e-01 }, +{ 5.969040e-01, 5.620845e-01, 8.270798e-01 }, +{ 6.283200e-01, 5.877864e-01, 8.090161e-01 }, +{ 6.597360e-01, 6.129083e-01, 7.901541e-01 }, +{ 6.911520e-01, 6.374252e-01, 7.705122e-01 }, +{ 7.225680e-01, 6.613131e-01, 7.501100e-01 }, +{ 7.539840e-01, 6.845484e-01, 7.289674e-01 }, +{ 7.854000e-01, 7.071081e-01, 7.071055e-01 }, +{ 8.168160e-01, 7.289699e-01, 6.845457e-01 }, +{ 8.482320e-01, 7.501124e-01, 6.613104e-01 }, +{ 8.796480e-01, 7.705146e-01, 6.374224e-01 }, +{ 9.110640e-01, 7.901563e-01, 6.129054e-01 }, +{ 9.424800e-01, 8.090183e-01, 5.877835e-01 }, +{ 9.738960e-01, 8.270819e-01, 5.620815e-01 }, +{ 1.005312e+00, 8.443292e-01, 5.358248e-01 }, +{ 1.036728e+00, 8.607433e-01, 5.090393e-01 }, +{ 1.068144e+00, 8.763079e-01, 4.817515e-01 }, +{ 1.099560e+00, 8.910077e-01, 4.539882e-01 }, +{ 1.130976e+00, 9.048282e-01, 4.257769e-01 }, +{ 1.162392e+00, 9.177557e-01, 3.971454e-01 }, +{ 1.193808e+00, 9.297775e-01, 3.681220e-01 }, +{ 1.225224e+00, 9.408817e-01, 3.387352e-01 }, +{ 1.256640e+00, 9.510574e-01, 3.090142e-01 }, +{ 1.288056e+00, 9.602945e-01, 2.789882e-01 }, +{ 1.319472e+00, 9.685839e-01, 2.486869e-01 }, +{ 1.350888e+00, 9.759175e-01, 2.181402e-01 }, +{ 1.382304e+00, 9.822879e-01, 1.873781e-01 }, +{ 1.413720e+00, 9.876889e-01, 1.564312e-01 }, +{ 1.445136e+00, 9.921151e-01, 1.253299e-01 }, +{ 1.476552e+00, 9.955623e-01, 9.410488e-02 }, +{ 1.507968e+00, 9.980269e-01, 6.278700e-02 }, +{ 1.539384e+00, 9.995067e-01, 3.140716e-02 }, +{ 1.570800e+00, 1.000000e-00, -3.673205e-06 }, +{ 1.602216e+00, 9.995064e-01, -3.141450e-02 }, +{ 1.633632e+00, 9.980265e-01, -6.279433e-02 }, +{ 1.665048e+00, 9.955616e-01, -9.411219e-02 }, +{ 1.696464e+00, 9.921142e-01, -1.253372e-01 }, +{ 1.727880e+00, 9.876877e-01, -1.564385e-01 }, +{ 1.759296e+00, 9.822865e-01, -1.873854e-01 }, +{ 1.790712e+00, 9.759158e-01, -2.181473e-01 }, +{ 1.822128e+00, 9.685821e-01, -2.486940e-01 }, +{ 1.853544e+00, 9.602925e-01, -2.789953e-01 }, +{ 1.884960e+00, 9.510552e-01, -3.090212e-01 }, +{ 1.916376e+00, 9.408793e-01, -3.387421e-01 }, +{ 1.947792e+00, 9.297748e-01, -3.681288e-01 }, +{ 1.979208e+00, 9.177528e-01, -3.971521e-01 }, +{ 2.010624e+00, 9.048251e-01, -4.257835e-01 }, +{ 2.042040e+00, 8.910044e-01, -4.539948e-01 }, +{ 2.073456e+00, 8.763043e-01, -4.817579e-01 }, +{ 2.104872e+00, 8.607395e-01, -5.090457e-01 }, +{ 2.136288e+00, 8.443252e-01, -5.358310e-01 }, +{ 2.167704e+00, 8.270777e-01, -5.620876e-01 }, +{ 2.199120e+00, 8.090140e-01, -5.877894e-01 }, +{ 2.230536e+00, 7.901518e-01, -6.129112e-01 }, +{ 2.261952e+00, 7.705099e-01, -6.374281e-01 }, +{ 2.293368e+00, 7.501075e-01, -6.613159e-01 }, +{ 2.324784e+00, 7.289649e-01, -6.845511e-01 }, +{ 2.356200e+00, 7.071029e-01, -7.071107e-01 }, +{ 2.387616e+00, 6.845430e-01, -7.289724e-01 }, +{ 2.419032e+00, 6.613076e-01, -7.501148e-01 }, +{ 2.450448e+00, 6.374196e-01, -7.705169e-01 }, +{ 2.481864e+00, 6.129025e-01, -7.901586e-01 }, +{ 2.513280e+00, 5.877805e-01, -8.090204e-01 }, +{ 2.544696e+00, 5.620785e-01, -8.270839e-01 }, +{ 2.576112e+00, 5.358217e-01, -8.443312e-01 }, +{ 2.607528e+00, 5.090362e-01, -8.607451e-01 }, +{ 2.638944e+00, 4.817483e-01, -8.763097e-01 }, +{ 2.670360e+00, 4.539849e-01, -8.910094e-01 }, +{ 2.701776e+00, 4.257736e-01, -9.048297e-01 }, +{ 2.733192e+00, 3.971420e-01, -9.177572e-01 }, +{ 2.764608e+00, 3.681185e-01, -9.297789e-01 }, +{ 2.796024e+00, 3.387318e-01, -9.408830e-01 }, +{ 2.827440e+00, 3.090107e-01, -9.510586e-01 }, +{ 2.858856e+00, 2.789847e-01, -9.602956e-01 }, +{ 2.890272e+00, 2.486833e-01, -9.685848e-01 }, +{ 2.921688e+00, 2.181366e-01, -9.759183e-01 }, +{ 2.953104e+00, 1.873745e-01, -9.822885e-01 }, +{ 2.984520e+00, 1.564276e-01, -9.876894e-01 }, +{ 3.015936e+00, 1.253262e-01, -9.921156e-01 }, +{ 3.047352e+00, 9.410122e-02, -9.955626e-01 }, +{ 3.078768e+00, 6.278333e-02, -9.980272e-01 }, +{ 3.110184e+00, 3.140349e-02, -9.995068e-01 }, +{ 3.141600e+00, -7.346410e-06, -1.000000e-00 } +}; + +# define M_PI 3.14159265358979323846 /* pi */ + +static double inline gen_sin(double x) +{ + int i; + if(x < 0) while(x < -M_PI) x+= M_PI; + else while(x > M_PI) x-= M_PI; + for(i=0;i=g_sincos[i].x && x <= g_sincos[i+1].x) + { + return (g_sincos[i+1].sinx-g_sincos[i].sinx)*(x-g_sincos[i].x)/(g_sincos[i+1].x-g_sincos[i].x)+g_sincos[i].sinx; + } + } + return x<0?1:-1; +} +#undef sin +#define sin(x) gen_sin(x) + +static double inline gen_cos(double x) +{ + int i; + if(x < 0) while(x < -M_PI) x+= M_PI; + else while(x > M_PI) x-= M_PI; + for(i=0;i=g_sincos[i].x && x <= g_sincos[i+1].x) + { + return (g_sincos[i+1].cosx-g_sincos[i].cosx)*(x-g_sincos[i].x)/(g_sincos[i+1].x-g_sincos[i].x)+g_sincos[i].cosx; + } + } + return x<0?1:-1; +} +#undef cos +#define cos(x) gen_cos(x) + +#endif \ No newline at end of file diff --git a/drivers/hacking.ati b/drivers/hacking.ati new file mode 100644 index 0000000000..345c183608 --- /dev/null +++ b/drivers/hacking.ati @@ -0,0 +1,313 @@ + ATI chips hacking + ================= + Dedicated to ATI's hackers. + +Preface +~~~~~~~ +This document will compare ATI chips only from point of DAC and video overlay. +There are lots of difference from 3D point, dual-head support, tv-out support +and many other things but it's already perfectly different story. +This document doesn't include information about ATI AIW (All In Wonder) chips. + +What are units on modern ATI chips: +DAC - (Digital to Analog Convertor) controls CRTC, LCD, DFP monitor's output + Consists from: + PLL - (Programable line length) registers + CRTC - CRT controller + LCD/DFP scaler + surface control +DAC2 - controls CRTC, LCD, DFP monitor's output on second head +TVDAC - controls Composite Video and Super Video output ports + Consists from: + TV_PLL + TV scaler & sync unit + TV format convertor (PAL/NTSC) +TVCAP - controls Video-In port +MPP - Miscellaneous peripheral port. (includes macrovision's filter - copy + protection mechanism) +OV - Video overlay (YUV BES) (include subpictures, gamma correction and + adaptive deinterlacing) +CAP0 - Video capturing +CAP1 - Video capturing (second unit) +RT - Rage theatre: video encoding and mixing +MUX - video muxer +MEM - PCI/AGP bus mastering +2D - GUI engine +3D - 3D-OpenGL engine (There are lots of stuff) +I2C - I2C Bus control + +This document is mainly related only with OV unit ;) +Video decoding diagram: + +RAM memory: [ App ] Copies YUV image to overlay memory + | <-- (It's possible to program DMA here) +overlay memory:[ OV ] performs scaling and YUVtoRGB convertion + /\ +RGB memory: / \ + / [ macrovision ] performs copy protection filtering + / \ (unneeded but presented by default thing;) + [ CRTC/LCD/DFP DAC ] [ TV DAC ] convert RGB memory to CRTC and NTSC/PAL signals + | | + [CRTC/LCD/DFP Monitor] [TV-screen] + +History +~~~~~~~ + What is history of ATI's chips? I can be wrong but below is my vision +of this question: + +0. I don't know any earlied chips :( +1. Mach8 +2. Mach16 +3. Mach32 + +4. Mach64. + It's first chip which has support from side of open + source drivers. Set of mach64 chips is: + mach64GX (ATI888GX00) + mach64CX (ATI888CX00) + mach64CT (ATI264CT) + mach64ET (ATI264ET) + mach64VTA3 (ATI264VT) + mach64VTA4 (ATI264VT) + mach64VTB (ATI264VTB) + mach64VT4 (ATI264VT4) + +5. 3D rage chips. + It seems that these chips have fully compatible by GPU with Mach64 + which is extended by 3D possibilities. Set of 3D rage chips is: + 3D RAGE (GT) + 3D RAGE II+ (GTB) + 3D RAGE IIC (PCI) + 3D RAGE IIC (AGP) + 3D RAGE LT + 3D RAGE LT-G + 3D RAGE PRO (BGA, AGP) + 3D RAGE PRO (BGA, AGP, 1x only) + 3D RAGE PRO (BGA, PCI) + 3D RAGE PRO (PQFP, PCI) + 3D RAGE PRO (PQFP, PCI, limited 3D) + 3D RAGE (XL) + 3D RAGE LT PRO (AGP) + 3D RAGE LT PRO (PCI) + 3D RAGE Mobility (PCI) + 3D RAGE Mobility (AGP) + +6. Rage128 chips. + These chips have perfectly new GPU which supports memory mapped IO + space for accelerating port access (It's main cause of incompatibility + with mach64). Set of Rage128 chips is: + Rage128 GL RE + Rage128 GL RF + Rage128 GL RG + Rage128 GL RH + Rage128 GL RI + Rage128 VR RK + Rage128 VR RL + Rage128 VR RM + Rage128 VR RN + Rage128 VR RO + Rage128 Mobility M3 LE + Rage128 Mobility M3 LF +7. Rage128Pro chips. + These chips are successors of Rage128 ones. + Rage128Pro GL PA + Rage128Pro GL PB + Rage128Pro GL PC + Rage128Pro GL PD + Rage128Pro GL PE + Rage128Pro GL PF + Rage128Pro VR PG + Rage128Pro VR PH + Rage128Pro VR PI + Rage128Pro VR PJ + Rage128Pro VR PK + Rage128Pro VR PL + Rage128Pro VR PM + Rage128Pro VR PN + Rage128Pro VR PO + Rage128Pro VR PP + Rage128Pro VR PQ + Rage128Pro VR PR + Rage128Pro VR TR + Rage128Pro VR PS + Rage128Pro VR PT + Rage128Pro VR PU + Rage128Pro VR PV + Rage128Pro VR PW + Rage128Pro VR PX + Rage128Pro Ultra U1 + Rage128Pro Ultra U2 + Rage128Pro Ultra U3 + +8. Radeon chips. + Indeed they could be named Rage256 Pro. (With minor changes is fully + compatible with Rage128 chips). + Radeon QD + Radeon QE + Radeon QF + Radeon QG + Radeon VE QY + Radeon VE QZ + Radeon M6 LY + Radeon M6 LZ + Radeon M7 LW +9. Radeon2 chips. + Indeed they could be named Rage512 Pro. + Radeon2 8500 QL + Radeon2 7500 QW + +10. Radeon3 and newest are cooming soon, but I hope that they will be fully + compatible with Radeon1 chips. + +In Radeon famility there were introduced also FX chips: Radeon FX and +Radeon2 8700 FX. Probably they have the same possibility as other Radeon +but currently it's unknown for me. + +What about video overlay and DAC? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Currently it's known that there is only difference between +Mach64 and Rage128 compatible chips: +- They have different logic of io ports programming! +- They are incompatible by port numbers! +But: +- They use the same program logic from register's name point. +(Indeed exists slight difference even between Radeon and Rage128 +chips. AFAIK only Radeon has OV0_SLICE_CNTL register which currently +is not used by driver. But I know only its name ;). Also there +is difference in slight adjust of BES position but it's configured +by #ifdef blocks). + +Please compare: + +(The piece of Back-End Scaler programming) + + Sample for Mach64 compatible chips: + *********************************** + +#define SPARSE_IO_BASE 0x03fcu +#define SPARSE_IO_SELECT 0xfc00u + +#define BLOCK_IO_BASE 0xff00u +#define BLOCK_IO_SELECT 0x00fcu + +#define MM_IO_SELECT 0x03fcu +#define BLOCK_SELECT 0x0400u +#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT) + +#define IO_BYTE_SELECT 0x0003u + +#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT) +#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT) + +#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \ + (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \ + SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT)) +#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0) +#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect) + +... + +#define OVERLAY_Y_X_START BlockIOTag(0x100u) +#define OVERLAY_Y_X_END BlockIOTag(0x101u) + +... + +#define OUTREG(_Register, _Value) \ + MMIO_OUT32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \ + (_Register) & MM_IO_SELECT, _Value) + +... + +OUTREG(OVERLAY_Y_X_START,((drw_x)<<16)|(drw_y)|(1<<31)); +OUTREG(OVERLAY_Y_X_END,((drw_x+drw_w)<<16)|(drw_y+drw_h)); + + + Sample for Rage128 compatible chips: + ************************************ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 + +... + +#define INREG(addr) readl((rage_mmio_base)+addr) +#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr) + +... + +rage_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RAGE_REGSIZE); + +... + +#ifdef RADEON +#define X_ADJUST 8 +#else /* rage128 */ +#define X_ADJUST 0 +#endif + +OUTREG(OV0_Y_X_START,(drw_x+X_ADJUST)|(drw_y<<16)); +OUTREG(OV0_Y_X_END,(drw_x+drw_w+X_ADJUST)|(drw_y+drw_h)<<16)); + +Thus - these chips have almost the same logic from register's name point. +(except the fact that they have swapped 16-bit halfs). +Yes - programming of Rage128 is much simpler of Mach64. + + +What about other ATI's chips? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +I suggest you have latest copy of GATOS-CVS: +http://www.linuxvideo.org +GATOS was designed and introduced as General ATI TV and Overlay Sowfware. +You will be able to find out there a lots of useful hacking utilities +(at location gatos-ati/gatos): +gfxdump - Program for dumping graphics chips registers on Linux and Windows 9X. + (it's more useful for Win9x to hack their values). +xatitv - For working with tv-in (currently is under hard development) +atitvout- For working with tv-out +and lot of other stuff. +BUT: After studing of Gatos and X11 stuffs I've found that they are bad +optimized for movie playback. +Please compare: + radeon_vid - configures video overlay only once and provides DGA to it. + (doesn't require to be MMX optimized) + gatos and X11 - configures video overlay at every slice of frame, then + performs unoptimized copying of source stuff to video memory + often with using CopyMungedData (it's C-analog of YV12_to_YUY2) + since there are lacks in yv12 support. + (is not MMX optimized that's gladly accepted, but probably + will be never optimized due portability). + +hardware IDCT support diagram: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + | +[ Video parser ] <---------- [ Transport demuxing ] --> [ Audio ] + | | | +[ Variable length decoder] |D | + | |V | +[ Inverse quantization ] |D | + | | | +-------|---[ video card ]---------+ |s | + | | |u | +[ Run level decode & de-zigzag ] | |b | + | | |p | +[ IDCT ] | |i | + | | |c | +[ Motion compensation ] | |t | + | | |u | +[ Advanced deinterlacing ] | |r | + | | |e | +[ Filtered X-Y scaling ] [SUBPIC]-|-----+s [ OSD ] + | | | | | +[ 4-bit alpha blending ] <---+ | +-------+ + | | +[ YUV to RGB conversion ] | +-------|--------------------------+ +TV-screen or CRT-display + + +Conslusion: +~~~~~~~~~~~ + +That's all folk! diff --git a/drivers/radeon.h b/drivers/radeon.h new file mode 100644 index 0000000000..764e491c00 --- /dev/null +++ b/drivers/radeon.h @@ -0,0 +1,2046 @@ +/* + * radeon.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * This collection of definition was written by Nick Kurshev + * It's based on radeonfb, X11, GATOS sources + * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) +*/ + +#ifndef _RADEON_H +#define _RADEON_H + + +/* radeon PCI ids */ +#define PCI_DEVICE_ID_RADEON_QD 0x5144 +#define PCI_DEVICE_ID_RADEON_QE 0x5145 +#define PCI_DEVICE_ID_RADEON_QF 0x5146 +#define PCI_DEVICE_ID_RADEON_QG 0x5147 +#define PCI_DEVICE_ID_RADEON_QY 0x5159 +#define PCI_DEVICE_ID_RADEON_QZ 0x515A +#define PCI_DEVICE_ID_RADEON_LY 0x4C59 +#define PCI_DEVICE_ID_RADEON_LZ 0x4C5A +#define PCI_DEVICE_ID_RADEON_LW 0x4C57 +#define PCI_DEVICE_ID_R200_QL 0x514C +#define PCI_DEVICE_ID_RV200_QW 0x5157 +#define PCI_DEVICE_ID_R200_BB 0x4242 + +#define RADEON_REGSIZE 0x4000 + + +#define MM_INDEX 0x0000 +/* MM_INDEX bit constants */ +# define MM_APER 0x80000000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +/* BUS_CNTL bit constants */ +# define BUS_DBL_RESYNC 0x00000001 +# define BUS_MSTR_RESET 0x00000002 +# define BUS_FLUSH_BUF 0x00000004 +# define BUS_STOP_REQ_DIS 0x00000008 +# define BUS_ROTATION_DIS 0x00000010 +# define BUS_MASTER_DIS 0x00000040 +# define BUS_ROM_WRT_EN 0x00000080 +# define BUS_DIS_ROM 0x00001000 +# define BUS_PCI_READ_RETRY_EN 0x00002000 +# define BUS_AGP_AD_STEPPING_EN 0x00004000 +# define BUS_PCI_WRT_RETRY_EN 0x00008000 +# define BUS_MSTR_RD_MULT 0x00100000 +# define BUS_MSTR_RD_LINE 0x00200000 +# define BUS_SUSPEND 0x00400000 +# define LAT_16X 0x00800000 +# define BUS_RD_DISCARD_EN 0x01000000 +# define BUS_RD_ABORT_EN 0x02000000 +# define BUS_MSTR_WS 0x04000000 +# define BUS_PARKING_DIS 0x08000000 +# define BUS_MSTR_DISCONNECT_EN 0x10000000 +# define BUS_WRT_BURST 0x20000000 +# define BUS_READ_BURST 0x40000000 +# define BUS_RDY_READ_DLY 0x80000000 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +# define BUS_WAIT_ON_LOCK_EN (1 << 4) +#define I2C_CNTL_0 0x0090 +# define I2C_DONE (1<<0) +# define I2C_NACK (1<<1) +# define I2C_HALT (1<<2) +# define I2C_SOFT_RST (1<<5) +# define I2C_DRIVE_EN (1<<6) +# define I2C_DRIVE_SEL (1<<7) +# define I2C_START (1<<8) +# define I2C_STOP (1<<9) +# define I2C_RECEIVE (1<<10) +# define I2C_ABORT (1<<11) +# define I2C_GO (1<<12) +# define I2C_SEL (1<<16) +# define I2C_EN (1<<17) +#define I2C_CNTL_1 0x0094 +#define I2C_DATA 0x0098 +#define CONFIG_CNTL 0x00E0 +/* CONFIG_CNTL bit constants */ +# define CFG_VGA_RAM_EN 0x00000100 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define AGP_CNTL 0x0174 +# define AGP_APER_SIZE_256MB (0x00 << 0) +# define AGP_APER_SIZE_128MB (0x20 << 0) +# define AGP_APER_SIZE_64MB (0x30 << 0) +# define AGP_APER_SIZE_32MB (0x38 << 0) +# define AGP_APER_SIZE_16MB (0x3c << 0) +# define AGP_APER_SIZE_8MB (0x3e << 0) +# define AGP_APER_SIZE_4MB (0x3f << 0) +# define AGP_APER_SIZE_MASK (0x3f << 0) +#define AMCGPIO_A_REG 0x01a0 +#define AMCGPIO_EN_REG 0x01a8 +#define AMCGPIO_MASK 0x0194 +#define AMCGPIO_Y_REG 0x01a4 +#define BM_STATUS 0x0160 +#define MPP_TB_CONFIG 0x01c0 /* ? */ +#define MPP_GP_CONFIG 0x01c8 /* ? */ +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +# define AGP_1X_MODE 0x01 +# define AGP_2X_MODE 0x02 +# define AGP_4X_MODE 0x04 +# define AGP_MODE_MASK 0x07 +#define AGP_COMMAND 0x0F60 + +/* Video muxer unit */ +#define VIDEOMUX_CNTL 0x0190 +#define VIPPAD_MASK 0x0198 +#define VIPPAD1_A 0x01AC +#define VIPPAD1_EN 0x01B0 +#define VIPPAD1_Y 0x01B4 + +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +/* DAC_CNTL bit constants */ +# define DAC_8BIT_EN 0x00000100 +# define DAC_4BPP_PIX_ORDER 0x00000200 +# define DAC_CRC_EN 0x00080000 +# define DAC_MASK_ALL (0xff << 24) +# define DAC_VGA_ADR_EN (1 << 13) +# define DAC_RANGE_CNTL (3 << 0) +# define DAC_BLANKING (1 << 2) +#define DAC_CNTL2 0x007c +/* DAC_CNTL2 bit constants */ +# define DAC2_DAC_CLK_SEL (1 << 0) +# define DAC2_DAC2_CLK_SEL (1 << 1) +# define DAC2_PALETTE_ACC_CTL (1 << 5) +#define TV_DAC_CNTL 0x088c +/* TV_DAC_CNTL bit constants */ +# define TV_DAC_STD_MASK 0x0300 +# define TV_DAC_RDACPD (1 << 24) +# define TV_DAC_GDACPD (1 << 25) +# define TV_DAC_BDACPD (1 << 26) +#define CRTC_GEN_CNTL 0x0050 +/* CRTC_GEN_CNTL bit constants */ +# define CRTC_DBL_SCAN_EN 0x00000001 +# define CRTC_INTERLACE_EN (1 << 1) +# define CRTC_CSYNC_EN (1 << 4) +# define CRTC_CUR_EN 0x00010000 +# define CRTC_CUR_MODE_MASK (7 << 17) +# define CRTC_ICON_EN (1 << 20) +# define CRTC_EXT_DISP_EN (1 << 24) +# define CRTC_EN (1 << 25) +# define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC2_GEN_CNTL 0x03f8 +/* CRTC2_GEN_CNTL bit constants */ +# define CRTC2_DBL_SCAN_EN (1 << 0) +# define CRTC2_INTERLACE_EN (1 << 1) +# define CRTC2_SYNC_TRISTAT (1 << 4) +# define CRTC2_HSYNC_TRISTAT (1 << 5) +# define CRTC2_VSYNC_TRISTAT (1 << 6) +# define CRTC2_CRT2_ON (1 << 7) +# define CRTC2_ICON_EN (1 << 15) +# define CRTC2_CUR_EN (1 << 16) +# define CRTC2_CUR_MODE_MASK (7 << 20) +# define CRTC2_DISP_DIS (1 << 23) +# define CRTC2_EN (1 << 25) +# define CRTC2_DISP_REQ_EN_B (1 << 26) +# define CRTC2_HSYNC_DIS (1 << 28) +# define CRTC2_VSYNC_DIS (1 << 29) +#define MEM_CNTL 0x0140 +/* MEM_CNTL bit constants */ +# define MEM_CTLR_STATUS_IDLE 0x00000000 +# define MEM_CTLR_STATUS_BUSY 0x00100000 +# define MEM_SEQNCR_STATUS_IDLE 0x00000000 +# define MEM_SEQNCR_STATUS_BUSY 0x00200000 +# define MEM_ARBITER_STATUS_IDLE 0x00000000 +# define MEM_ARBITER_STATUS_BUSY 0x00400000 +# define MEM_REQ_UNLOCK 0x00000000 +# define MEM_REQ_LOCK 0x00800000 +#define EXT_MEM_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_FB_LOCATION 0x0148 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define SURFACE_CNTL 0x0B00 +/* SURFACE_CNTL bit constants */ +# define SURF_TRANSLATION_DIS (1 << 8) +# define NONSURF_AP0_SWP_16BPP (1 << 20) +# define NONSURF_AP0_SWP_32BPP (2 << 20) +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +# define VSYNC_INT_AK (1 << 2) +# define VSYNC_INT (1 << 2) +#define CRTC_EXT_CNTL 0x0054 +/* CRTC_EXT_CNTL bit constants */ +# define CRTC_VGA_XOVERSCAN (1 << 0) +# define VGA_ATI_LINEAR 0x00000008 +# define VGA_128KAP_PAGING 0x00000010 +# define XCRT_CNT_EN (1 << 6) +# define CRTC_HSYNC_DIS (1 << 8) +# define CRTC_VSYNC_DIS (1 << 9) +# define CRTC_DISPLAY_DIS (1 << 10) +# define CRTC_SYNC_TRISTAT (1 << 11) +# define CRTC_CRT_ON (1 << 15) +#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define CRTC_HSYNC_DIS_BYTE (1 << 0) +# define CRTC_VSYNC_DIS_BYTE (1 << 1) +# define CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +# define RBBM_FIFOCNT_MASK 0x007f +# define RBBM_ACTIVE (1 << 31) +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +/* RBBM_SOFT_RESET bit constants */ +# define SOFT_RESET_CP (1 << 0) +# define SOFT_RESET_HI (1 << 1) +# define SOFT_RESET_SE (1 << 2) +# define SOFT_RESET_RE (1 << 3) +# define SOFT_RESET_PP (1 << 4) +# define SOFT_RESET_E2 (1 << 5) +# define SOFT_RESET_RB (1 << 6) +# define SOFT_RESET_HDP (1 << 7) +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +/* CRTC_STATUS bit constants */ +# define CRTC_VBLANK 0x00000001 +# define CRTC_VBLANK_SAVE ( 1 << 1) +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +# define CRTC_H_TOTAL (0x03ff << 0) +# define CRTC_H_TOTAL_SHIFT 0 +# define CRTC_H_DISP (0x01ff << 16) +# define CRTC_H_DISP_SHIFT 16 +#define CRTC2_H_TOTAL_DISP 0x0300 +# define CRTC2_H_TOTAL (0x03ff << 0) +# define CRTC2_H_TOTAL_SHIFT 0 +# define CRTC2_H_DISP (0x01ff << 16) +# define CRTC2_H_DISP_SHIFT 16 +#define CRTC_H_SYNC_STRT_WID 0x0204 +# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC_H_SYNC_WID (0x3f << 16) +# define CRTC_H_SYNC_WID_SHIFT 16 +# define CRTC_H_SYNC_POL (1 << 23) +#define CRTC2_H_SYNC_STRT_WID 0x0304 +# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC2_H_SYNC_WID (0x3f << 16) +# define CRTC2_H_SYNC_WID_SHIFT 16 +# define CRTC2_H_SYNC_POL (1 << 23) +#define CRTC_V_TOTAL_DISP 0x0208 +# define CRTC_V_TOTAL (0x07ff << 0) +# define CRTC_V_TOTAL_SHIFT 0 +# define CRTC_V_DISP (0x07ff << 16) +# define CRTC_V_DISP_SHIFT 16 +#define CRTC2_V_TOTAL_DISP 0x0308 +# define CRTC2_V_TOTAL (0x07ff << 0) +# define CRTC2_V_TOTAL_SHIFT 0 +# define CRTC2_V_DISP (0x07ff << 16) +# define CRTC2_V_DISP_SHIFT 16 +#define CRTC_V_SYNC_STRT_WID 0x020C +# define CRTC_V_SYNC_STRT (0x7ff << 0) +# define CRTC_V_SYNC_STRT_SHIFT 0 +# define CRTC_V_SYNC_WID (0x1f << 16) +# define CRTC_V_SYNC_WID_SHIFT 16 +# define CRTC_V_SYNC_POL (1 << 23) +#define CRTC2_V_SYNC_STRT_WID 0x030C +# define CRTC2_V_SYNC_STRT (0x7ff << 0) +# define CRTC2_V_SYNC_STRT_SHIFT 0 +# define CRTC2_V_SYNC_WID (0x1f << 16) +# define CRTC2_V_SYNC_WID_SHIFT 16 +# define CRTC2_V_SYNC_POL (1 << 23) +#define CRTC_VLINE_CRNT_VLINE 0x0210 +# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC_DEBUG 0x021C +#define CRTC2_DEBUG 0x031C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC2_OFFSET 0x0324 +#define CRTC_OFFSET_CNTL 0x0228 +# define CRTC_TILE_EN (1 << 15) +#define CRTC2_OFFSET_CNTL 0x0328 +# define CRTC2_TILE_EN (1 << 15) +#define CRTC_PITCH 0x022C +#define CRTC2_PITCH 0x032C +#define TMDS_CRC 0x02a0 +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC2_H_TOTAL_DISP 0x0350 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define FP_CRTC2_V_TOTAL_DISP 0x0354 +# define FP_CRTC_H_TOTAL_MASK 0x000003ff +# define FP_CRTC_H_DISP_MASK 0x01ff0000 +# define FP_CRTC_V_TOTAL_MASK 0x00000fff +# define FP_CRTC_V_DISP_MASK 0x0fff0000 +# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define FP_H_SYNC_WID_MASK 0x003f0000 +# define FP_V_SYNC_STRT_MASK 0x00000fff +# define FP_V_SYNC_WID_MASK 0x001f0000 +# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_H_DISP_SHIFT 0x00000010 +# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_V_DISP_SHIFT 0x00000010 +# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define FP_H_SYNC_WID_SHIFT 0x00000010 +# define FP_V_SYNC_STRT_SHIFT 0x00000000 +# define FP_V_SYNC_WID_SHIFT 0x00000010 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +# define CUR_LOCK 0x80000000 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define CUR2_OFFSET 0x0360 +#define CUR2_HORZ_VERT_POSN 0x0364 +#define CUR2_HORZ_VERT_OFF 0x0368 +# define CUR2_LOCK (1 << 31) +#define CUR2_CLR0 0x036c +#define CUR2_CLR1 0x0370 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +/* FP_GEN_CNTL bit constants */ +# define FP_FPON (1 << 0) +# define FP_TMDS_EN (1 << 2) +# define FP_EN_TMDS (1 << 7) +# define FP_DETECT_SENSE (1 << 8) +# define FP_SEL_CRTC2 (1 << 13) +# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define FP_DFP_SYNC_SEL (1 << 21) +# define FP_CRTC_LOCK_8DOT (1 << 22) +# define FP_CRT_SYNC_SEL (1 << 23) +# define FP_USE_SHADOW_EN (1 << 24) +# define FP_CRT_SYNC_ALT (1 << 26) +#define FP2_GEN_CNTL 0x0288 +/* FP2_GEN_CNTL bit constants */ +# define FP2_FPON (1 << 0) +# define FP2_TMDS_EN (1 << 2) +# define FP2_EN_TMDS (1 << 7) +# define FP2_DETECT_SENSE (1 << 8) +# define FP2_SEL_CRTC2 (1 << 13) +# define FP2_FP_POL (1 << 16) +# define FP2_LP_POL (1 << 17) +# define FP2_SCK_POL (1 << 18) +# define FP2_LCD_CNTL_MASK (7 << 19) +# define FP2_PAD_FLOP_EN (1 << 22) +# define FP2_CRC_EN (1 << 23) +# define FP2_CRC_READ_EN (1 << 24) +#define FP_HORZ_STRETCH 0x028C +#define FP_HORZ2_STRETCH 0x038C +# define HORZ_STRETCH_RATIO_MASK 0xffff +# define HORZ_STRETCH_RATIO_MAX 4096 +# define HORZ_PANEL_SIZE (0x1ff << 16) +# define HORZ_PANEL_SHIFT 16 +# define HORZ_STRETCH_PIXREP (0 << 25) +# define HORZ_STRETCH_BLEND (1 << 26) +# define HORZ_STRETCH_ENABLE (1 << 25) +# define HORZ_AUTO_RATIO (1 << 27) +# define HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define HORZ_AUTO_RATIO_INC (1 << 31) +#define FP_VERT_STRETCH 0x0290 +#define FP_VERT2_STRETCH 0x0390 +# define VERT_PANEL_SIZE (0xfff << 12) +# define VERT_PANEL_SHIFT 12 +# define VERT_STRETCH_RATIO_MASK 0xfff +# define VERT_STRETCH_RATIO_SHIFT 0 +# define VERT_STRETCH_RATIO_MAX 4096 +# define VERT_STRETCH_ENABLE (1 << 25) +# define VERT_STRETCH_LINEREP (0 << 26) +# define VERT_STRETCH_BLEND (1 << 26) +# define VERT_AUTO_RATIO_EN (1 << 27) +# define VERT_STRETCH_RESERVED 0xf1000000 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_H2_SYNC_STRT_WID 0x03C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define FP_V2_SYNC_STRT_WID 0x03C8 +#define LVDS_GEN_CNTL 0x02d0 +# define LVDS_ON (1 << 0) +# define LVDS_DISPLAY_DIS (1 << 1) +# define LVDS_PANEL_TYPE (1 << 2) +# define LVDS_PANEL_FORMAT (1 << 3) +# define LVDS_EN (1 << 7) +# define LVDS_DIGON (1 << 18) +# define LVDS_BLON (1 << 19) +# define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_PLL_CNTL 0x02d4 +# define HSYNC_DELAY_SHIFT 28 +# define HSYNC_DELAY_MASK (0xf << 28) +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 + +#define GRPH_BUFFER_CNTL 0x02F0 +#define VGA_BUFFER_CNTL 0x02F4 + +/* first overlay unit (there is only one) */ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define EXCL_HORZ_START_MASK 0x000000ff +# define EXCL_HORZ_END_MASK 0x0000ff00 +# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define EXCL_VERT_START_MASK 0x000003ff +# define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +# define REG_LD_CTL_LOCK 0x00000001L +# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +# define SCALER_PIX_EXPAND 0x00000001L +# define SCALER_Y2R_TEMP 0x00000002L +#ifdef RAGE128 +# define SCALER_HORZ_PICK_NEAREST 0x00000003L +# define SCALER_VERT_PICK_NEAREST 0x00000004L +#else +# define SCALER_HORZ_PICK_NEAREST 0x00000004L +# define SCALER_VERT_PICK_NEAREST 0x00000008L +#endif +# define SCALER_SIGNED_UV 0x00000010L +# define SCALER_GAMMA_SEL_MASK 0x00000060L +# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define SCALER_GAMMA_SEL_G22 0x00000020L +# define SCALER_GAMMA_SEL_G18 0x00000040L +# define SCALER_GAMMA_SEL_G14 0x00000060L +# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define SCALER_SURFAC_FORMAT 0x00000f00L +# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ +# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ +# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ +# define SCALER_SOURCE_15BPP 0x00000300L +# define SCALER_SOURCE_16BPP 0x00000400L +# define SCALER_SOURCE_24BPP 0x00000500L +# define SCALER_SOURCE_32BPP 0x00000600L +# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ +# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ +# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ +# define SCALER_SOURCE_YUV12 0x00000A00L +# define SCALER_SOURCE_VYUY422 0x00000B00L +# define SCALER_SOURCE_YVYU422 0x00000C00L +# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ +# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ +# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ +# define SCALER_ADAPTIVE_DEINT 0x00001000L +# define R200_SCALER_TEMPORAL_DEINT 0x00002000L +# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ +# define SCALER_SMART_SWITCH 0x00008000L +#ifdef RAGE128 +# define SCALER_BURST_PER_PLANE 0x00ff0000L +#else +# define SCALER_BURST_PER_PLANE 0x007f0000L +#endif +# define SCALER_DOUBLE_BUFFER 0x01000000L +# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ +# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ +# define SCALER_DIS_LIMIT 0x08000000L +# define SCALER_PRG_LOAD_START 0x10000000L +# define SCALER_INT_EMU 0x20000000L +# define SCALER_ENABLE 0x40000000L +# define SCALER_SOFT_RESET 0x80000000L +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P23_V_ACCUM_INIT 0x042C +# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define P23_ACTIVE_LINES_M1 0x07ff0000L +#ifndef RAGE128 +#define OV0_BASE_ADDR 0x043C +#endif +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define VIF_BUF0_PITCH_SEL 0x00000001L +# define VIF_BUF0_TILE_ADRS 0x00000002L +# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define VIF_BUF1_PITCH_SEL 0x00000001L +# define VIF_BUF1_TILE_ADRS 0x00000002L +# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define VIF_BUF2_PITCH_SEL 0x00000001L +# define VIF_BUF2_TILE_ADRS 0x00000002L +# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +# define VIF_BUF3_PITCH_SEL 0x00000001L +# define VIF_BUF3_TILE_ADRS 0x00000002L +# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +# define VIF_BUF4_PITCH_SEL 0x00000001L +# define VIF_BUF4_TILE_ADRS 0x00000002L +# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +# define VIF_BUF5_PITCH_SEL 0x00000001L +# define VIF_BUF5_TILE_ADRS 0x00000002L +# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +# define FILTER_PROGRAMMABLE_COEF 0x00000000 +# define FILTER_HARDCODED_COEF 0x0000000F +# define FILTER_COEF_MASK 0x0000000F +/* other values allow us use hardcoded coefs for Y and + programmable for UV that's nosense. */ +/* + Top quality 4x4-tap filtered vertical and horizontal scaler. + It allows up to 64:1 upscaling and downscaling without + performance or quality degradation. +*/ +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 + +#define OV0_FLAG_CNTL 0x04DC +#ifdef RAGE128 +#define OV0_COLOUR_CNTL 0x04E0 +# define COLOUR_CNTL_BRIGHTNESS 0x0000007F +# define COLOUR_CNTL_SATURATION 0x001F1F00 +#else +/* NB: radeons have no COLOUR_CNTL register */ +#define OV0_SLICE_CNTL 0x04E0 +# define SLICE_CNTL_DISABLE 0x40000000 +#endif +/* Video and graphics keys allow alpha blending, color correction + and many other video effects */ +#define OV0_VID_KEY_CLR 0x04E4 +#define OV0_VID_KEY_MSK 0x04E8 +#define OV0_GRAPHICS_KEY_CLR 0x04EC +#define OV0_GRAPHICS_KEY_MSK 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +# define VIDEO_KEY_FN_MASK 0x00000007L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000004L +# define VIDEO_KEY_FN_NE 0x00000005L +# define GRAPHIC_KEY_FN_MASK 0x00000070L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000040L +# define GRAPHIC_KEY_FN_NE 0x00000050L +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +#define OV0_TEST 0x04F8 +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +/* These registers exist on R200 only */ +#define OV0_GAMMA_80_BF 0x0E00 +#define OV0_GAMMA_C0_FF 0x0E04 +#define OV0_GAMMA_100_13F 0x0E08 +#define OV0_GAMMA_140_17F 0x0E0C +#define OV0_GAMMA_180_1BF 0x0E10 +#define OV0_GAMMA_1C0_1FF 0x0E14 +#define OV0_GAMMA_200_23F 0x0E18 +#define OV0_GAMMA_240_27F 0x0E1C +#define OV0_GAMMA_280_2BF 0x0E20 +#define OV0_GAMMA_2C0_2FF 0x0E24 +#define OV0_GAMMA_300_33F 0x0E28 +#define OV0_GAMMA_340_37F 0x0E2C +/* End of R200 specific definitions */ +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 + +/* + IDCT ENGINE: + It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag + and IDCT into an IDCT engine to complement the motion compensation engine. +*/ +#define IDCT_RUNS 0x1F80 +#define IDCT_LEVELS 0x1F84 +#define IDCT_AUTH_CONTROL 0x1F88 +#define IDCT_AUTH 0x1F8C +#define IDCT_CONTROL 0x1FBC + +#define SE_MC_SRC2_CNTL 0x19D4 +#define SE_MC_SRC1_CNTL 0x19D8 +#define SE_MC_DST_CNTL 0x19DC +#define SE_MC_CNTL_START 0x19E0 +#ifndef RAGE128 +#define SE_MC_BUF_BASE 0x19E4 +#define PP_MC_CONTEXT 0x19E8 +#define PP_MISC 0x1C14 +#endif +/* + SUBPICTURE UNIT: + Decompressing, scaling and alpha blending the compressed bitmap on the fly. + Provide optimal DVD subpicture qualtity. +*/ +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 + +#define CP_RB_BASE 0x0700 +#define CP_RB_CNTL 0x0704 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define CP_CSQ_CNTL 0x0740 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DMA_GUI_TABLE_ADDR 0x0780 +#define DMA_GUI_SRC_ADDR 0x0784 +#define DMA_GUI_DST_ADDR 0x0788 +#define DMA_GUI_COMMAND 0x078C +#define DMA_GUI_STATUS 0x0790 +#define DMA_GUI_ACT_DSCRPTR 0x0794 +#define DMA_VID_TABLE_ADDR 0x07A0 +#define DMA_VID_SRC_ADDR 0x07A4 +#define DMA_VID_DST_ADDR 0x07A8 +#define DMA_VID_COMMAND 0x07AC +#define DMA_VID_STATUS 0x07B0 +#define DMA_VID_ACT_DSCRPTR 0x07B4 +#define CP_ME_CNTL 0x07D0 +#define CP_ME_RAM_ADDR 0x07D4 +#define CP_ME_RAM_RADDR 0x07D8 +#define CP_ME_RAM_DATAH 0x07DC +#define CP_ME_RAM_DATAL 0x07E0 +#define CP_CSQ_ADDR 0x07F0 +#define CP_CSQ_DATA 0x07F4 +#define CP_CSQ_STAT 0x07F8 + +#define DISP_MISC_CNTL 0x0D00 +# define SOFT_RESET_GRPH_PP (1 << 0) +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C + +/* first capture unit */ + +#define VID_BUFFER_CONTROL 0x0900 +#define CAP_INT_CNTL 0x0908 +#define CAP_INT_STATUS 0x090C +#define FCP_CNTL 0x0910 +#define CAP0_BUF0_OFFSET 0x0920 +#define CAP0_BUF1_OFFSET 0x0924 +#define CAP0_BUF0_EVEN_OFFSET 0x0928 +#define CAP0_BUF1_EVEN_OFFSET 0x092C +#define CAP0_BUF_PITCH 0x0930 +#define CAP0_V_WINDOW 0x0934 +#define CAP0_H_WINDOW 0x0938 +#define CAP0_VBI0_OFFSET 0x093C +#define CAP0_VBI1_OFFSET 0x0940 +#define CAP0_VBI_V_WINDOW 0x0944 +#define CAP0_VBI_H_WINDOW 0x0948 +#define CAP0_PORT_MODE_CNTL 0x094C +#define CAP0_TRIG_CNTL 0x0950 +#define CAP0_DEBUG 0x0954 +#define CAP0_CONFIG 0x0958 +# define CAP0_CONFIG_CONTINUOS 0x00000001 +# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define CAP0_CONFIG_START_BUF_GET 0x00000004 +# define CAP0_CONFIG_START_BUF_SET 0x00000008 +# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define CAP0_CONFIG_MIRROR_EN 0x00000200 +# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define CAP0_CONFIG_VBI_EN 0x00002000 +# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define CAP0_ANC_ODD_OFFSET 0x095C +#define CAP0_ANC_EVEN_OFFSET 0x0960 +#define CAP0_ANC_H_WINDOW 0x0964 +#define CAP0_VIDEO_SYNC_TEST 0x0968 +#define CAP0_ONESHOT_BUF_OFFSET 0x096C +#define CAP0_BUF_STATUS 0x0970 +#ifdef RAGE128 +#define CAP0_DWNSC_XRATIO 0x0978 +#define CAP0_XSHARPNESS 0x097C +#else +/* #define CAP0_DWNSC_XRATIO 0x0978 */ +/* #define CAP0_XSHARPNESS 0x097C */ +#endif +#define CAP0_VBI2_OFFSET 0x0980 +#define CAP0_VBI3_OFFSET 0x0984 +#define CAP0_ANC2_OFFSET 0x0988 +#define CAP0_ANC3_OFFSET 0x098C + +/* second capture unit */ + +#define CAP1_BUF0_OFFSET 0x0990 +#define CAP1_BUF1_OFFSET 0x0994 +#define CAP1_BUF0_EVEN_OFFSET 0x0998 +#define CAP1_BUF1_EVEN_OFFSET 0x099C + +#define CAP1_BUF_PITCH 0x09A0 +#define CAP1_V_WINDOW 0x09A4 +#define CAP1_H_WINDOW 0x09A8 +#define CAP1_VBI_ODD_OFFSET 0x09AC +#define CAP1_VBI_EVEN_OFFSET 0x09B0 +#define CAP1_VBI_V_WINDOW 0x09B4 +#define CAP1_VBI_H_WINDOW 0x09B8 +#define CAP1_PORT_MODE_CNTL 0x09BC +#define CAP1_TRIG_CNTL 0x09C0 +#define CAP1_DEBUG 0x09C4 +#define CAP1_CONFIG 0x09C8 +#define CAP1_ANC_ODD_OFFSET 0x09CC +#define CAP1_ANC_EVEN_OFFSET 0x09D0 +#define CAP1_ANC_H_WINDOW 0x09D4 +#define CAP1_VIDEO_SYNC_TEST 0x09D8 +#define CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define CAP1_BUF_STATUS 0x09E0 +#define CAP1_DWNSC_XRATIO 0x09E8 +#define CAP1_XSHARPNESS 0x09EC + +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL