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authornickols_k <nickols_k@b3059339-0415-0410-9bf9-f77b7e298cf2>2001-06-13 16:12:14 +0000
committernickols_k <nickols_k@b3059339-0415-0410-9bf9-f77b7e298cf2>2001-06-13 16:12:14 +0000
commit50f47cfd500e666eff9db8b5f6e6b0839539c021 (patch)
treeff77d763b7bbd77dc02ed198f6ff615ae6ef3a43 /libvo
parent6bef8b7c5c13e6607e5d8f732dea411cc062bed6 (diff)
downloadmpv-50f47cfd500e666eff9db8b5f6e6b0839539c021.tar.bz2
mpv-50f47cfd500e666eff9db8b5f6e6b0839539c021.tar.xz
Issues about P3 performance and SSE2 support.
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@1124 b3059339-0415-0410-9bf9-f77b7e298cf2
Diffstat (limited to 'libvo')
-rw-r--r--libvo/aclib.c11
-rw-r--r--libvo/aclib_template.c11
2 files changed, 18 insertions, 4 deletions
diff --git a/libvo/aclib.c b/libvo/aclib.c
index 85bab6e040..2366a28d51 100644
--- a/libvo/aclib.c
+++ b/libvo/aclib.c
@@ -8,8 +8,15 @@
#include <stddef.h>
-/* Enable this code, if SSE version works (faster) for you! */
-#if 1
+#ifndef HAVE_SSE2
+/*
+ P3 processor has only one SSE decoder so can execute only 1 sse insn per
+ cpu clock, but it has 3 mmx decoders (include load/store unit)
+ and executes 3 mmx insns per cpu clock.
+ P4 processor has some chances, but after reading:
+ http://www.emulators.com/pentium4.htm
+ I have doubts. Anyway SSE2 version of this code can be written better.
+*/
#undef HAVE_SSE
#endif
diff --git a/libvo/aclib_template.c b/libvo/aclib_template.c
index 85bab6e040..2366a28d51 100644
--- a/libvo/aclib_template.c
+++ b/libvo/aclib_template.c
@@ -8,8 +8,15 @@
#include <stddef.h>
-/* Enable this code, if SSE version works (faster) for you! */
-#if 1
+#ifndef HAVE_SSE2
+/*
+ P3 processor has only one SSE decoder so can execute only 1 sse insn per
+ cpu clock, but it has 3 mmx decoders (include load/store unit)
+ and executes 3 mmx insns per cpu clock.
+ P4 processor has some chances, but after reading:
+ http://www.emulators.com/pentium4.htm
+ I have doubts. Anyway SSE2 version of this code can be written better.
+*/
#undef HAVE_SSE
#endif