- added capture registers

- tuned some values for Rage128 and radeon
- tabs (sorry for inconveniece)


git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3382 b3059339-0415-0410-9bf9-f77b7e298cf2

1 files changed, 1767 insertions, 1661 deletions

diff --git a/drivers/radeon/radeon.h b/drivers/radeon/radeon.h
index 03f01ad700..c3405717f7 100644
--- a/drivers/radeon/radeon.h
+++ b/drivers/radeon/radeon.h
@@ -1,1826 +1,1932 @@
-#ifndef _RADEON_H
-#define _RADEON_H
+/*
+ * radeon.h
+ * This	software has been released under the terms of the GNU Public
+ * license. See	http://www.gnu.org/copyleft/gpl.html for details.
+ *
+ * This	collection of definition was written by	Nick Kurshev
+ * It's	based on radeonfb, X11,	GATOS sources
+ * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts)
+*/
+
+#ifndef	_RADEON_H
+#define	_RADEON_H
 
 
 /* radeon PCI ids */
-#define PCI_DEVICE_ID_RADEON_QD		0x5144
-#define PCI_DEVICE_ID_RADEON_QE		0x5145
-#define PCI_DEVICE_ID_RADEON_QF		0x5146
-#define PCI_DEVICE_ID_RADEON_QG		0x5147
-#define PCI_DEVICE_ID_RADEON_QY		0x5159
-#define PCI_DEVICE_ID_RADEON_QZ		0x515A
-#define PCI_DEVICE_ID_RADEON_LY		0x4C59
-#define PCI_DEVICE_ID_RADEON_LZ		0x4C5A
-#define PCI_DEVICE_ID_RADEON_LW		0x4C57
-#define PCI_DEVICE_ID_R200_QL		0x514C
-#define PCI_DEVICE_ID_RV200_QW		0x5157
-
-#define RADEON_REGSIZE			0x4000
-
-
-#define MM_INDEX                        0x0000  
-/* MM_INDEX bit constants */
-#	define MM_APER                         0x80000000
-#define MM_DATA                                0x0004  
-#define BUS_CNTL                               0x0030  
-/* BUS_CNTL bit constants */
-#	define BUS_DBL_RESYNC                  0x00000001
-#	define BUS_MSTR_RESET                  0x00000002
-#	define BUS_FLUSH_BUF                   0x00000004
-#	define BUS_STOP_REQ_DIS                0x00000008
-#	define BUS_ROTATION_DIS                0x00000010
-#	define BUS_MASTER_DIS                  0x00000040
-#	define BUS_ROM_WRT_EN                  0x00000080
-#	define BUS_DIS_ROM                     0x00001000
-#	define BUS_PCI_READ_RETRY_EN           0x00002000
-#	define BUS_AGP_AD_STEPPING_EN          0x00004000
-#	define BUS_PCI_WRT_RETRY_EN            0x00008000
-#	define BUS_MSTR_RD_MULT                0x00100000
-#	define BUS_MSTR_RD_LINE                0x00200000
-#	define BUS_SUSPEND                     0x00400000
-#	define LAT_16X                         0x00800000
-#	define BUS_RD_DISCARD_EN               0x01000000
-#	define BUS_RD_ABORT_EN                 0x02000000
-#	define BUS_MSTR_WS                     0x04000000
-#	define BUS_PARKING_DIS                 0x08000000
-#	define BUS_MSTR_DISCONNECT_EN          0x10000000
-#	define BUS_WRT_BURST                   0x20000000
-#	define BUS_READ_BURST                  0x40000000
-#	define BUS_RDY_READ_DLY                0x80000000
-#define HI_STAT                                0x004C  
-#define BUS_CNTL1                              0x0034
-#	define BUS_WAIT_ON_LOCK_EN             (1 << 4)
-#define I2C_CNTL_0			       0x0090
-#	define I2C_DONE			       (1<<0)
-#	define I2C_NACK			       (1<<1)
-#	define I2C_HALT			       (1<<2)
-#	define I2C_SOFT_RST		       (1<<5)
-#	define I2C_DRIVE_EN		       (1<<6)
-#	define I2C_DRIVE_SEL		       (1<<7)
-#	define I2C_START		       (1<<8)
-#	define I2C_STOP			       (1<<9)
-#	define I2C_RECEIVE		       (1<<10)
-#	define I2C_ABORT		       (1<<11)
-#	define I2C_GO			       (1<<12)
-#	define I2C_SEL			       (1<<16)
-#	define I2C_EN			       (1<<17)
-#define I2C_CNTL_1			       0x0094 
-#define I2C_DATA			       0x0098
-#define CONFIG_CNTL                            0x00E0  
+#define	PCI_DEVICE_ID_RADEON_QD		0x5144
+#define	PCI_DEVICE_ID_RADEON_QE		0x5145
+#define	PCI_DEVICE_ID_RADEON_QF		0x5146
+#define	PCI_DEVICE_ID_RADEON_QG		0x5147
+#define	PCI_DEVICE_ID_RADEON_QY		0x5159
+#define	PCI_DEVICE_ID_RADEON_QZ		0x515A
+#define	PCI_DEVICE_ID_RADEON_LY		0x4C59
+#define	PCI_DEVICE_ID_RADEON_LZ		0x4C5A
+#define	PCI_DEVICE_ID_RADEON_LW		0x4C57
+#define	PCI_DEVICE_ID_R200_QL		0x514C
+#define	PCI_DEVICE_ID_RV200_QW		0x5157
+
+#define	RADEON_REGSIZE			0x4000
+
+
+#define	MM_INDEX			0x0000
+/* MM_INDEX bit	constants */
+#	define MM_APER				0x80000000
+#define	MM_DATA					0x0004
+#define	BUS_CNTL				0x0030
+/* BUS_CNTL bit	constants */
+#	define BUS_DBL_RESYNC			0x00000001
+#	define BUS_MSTR_RESET			0x00000002
+#	define BUS_FLUSH_BUF			0x00000004
+#	define BUS_STOP_REQ_DIS			0x00000008
+#	define BUS_ROTATION_DIS			0x00000010
+#	define BUS_MASTER_DIS			0x00000040
+#	define BUS_ROM_WRT_EN			0x00000080
+#	define BUS_DIS_ROM			0x00001000
+#	define BUS_PCI_READ_RETRY_EN		0x00002000
+#	define BUS_AGP_AD_STEPPING_EN		0x00004000
+#	define BUS_PCI_WRT_RETRY_EN		0x00008000
+#	define BUS_MSTR_RD_MULT			0x00100000
+#	define BUS_MSTR_RD_LINE			0x00200000
+#	define BUS_SUSPEND			0x00400000
+#	define LAT_16X				0x00800000
+#	define BUS_RD_DISCARD_EN		0x01000000
+#	define BUS_RD_ABORT_EN			0x02000000
+#	define BUS_MSTR_WS			0x04000000
+#	define BUS_PARKING_DIS			0x08000000
+#	define BUS_MSTR_DISCONNECT_EN		0x10000000
+#	define BUS_WRT_BURST			0x20000000
+#	define BUS_READ_BURST			0x40000000
+#	define BUS_RDY_READ_DLY			0x80000000
+#define	HI_STAT					0x004C
+#define	BUS_CNTL1				0x0034
+#	define BUS_WAIT_ON_LOCK_EN		(1 << 4)
+#define	I2C_CNTL_0				0x0090
+#	define I2C_DONE				(1<<0)
+#	define I2C_NACK				(1<<1)
+#	define I2C_HALT				(1<<2)
+#	define I2C_SOFT_RST			(1<<5)
+#	define I2C_DRIVE_EN			(1<<6)
+#	define I2C_DRIVE_SEL			(1<<7)
+#	define I2C_START			(1<<8)
+#	define I2C_STOP				(1<<9)
+#	define I2C_RECEIVE			(1<<10)
+#	define I2C_ABORT			(1<<11)
+#	define I2C_GO				(1<<12)
+#	define I2C_SEL				(1<<16)
+#	define I2C_EN				(1<<17)
+#define	I2C_CNTL_1				0x0094
+#define	I2C_DATA				0x0098
+#define	CONFIG_CNTL				0x00E0
 /* CONFIG_CNTL bit constants */
-#	define CFG_VGA_RAM_EN                  0x00000100
-#define CONFIG_MEMSIZE                         0x00F8  
-#define CONFIG_APER_0_BASE                     0x0100  
-#define CONFIG_APER_1_BASE                     0x0104  
-#define CONFIG_APER_SIZE                       0x0108  
-#define CONFIG_REG_1_BASE                      0x010C  
-#define CONFIG_REG_APER_SIZE                   0x0110  
-#define PAD_AGPINPUT_DELAY                     0x0164  
-#define PAD_CTLR_STRENGTH                      0x0168  
-#define PAD_CTLR_UPDATE                        0x016C
-#define AGP_CNTL                               0x0174
-#	define AGP_APER_SIZE_256MB             (0x00 << 0)
-#	define AGP_APER_SIZE_128MB             (0x20 << 0)
-#	define AGP_APER_SIZE_64MB              (0x30 << 0)
-#	define AGP_APER_SIZE_32MB              (0x38 << 0)
-#	define AGP_APER_SIZE_16MB              (0x3c << 0)
-#	define AGP_APER_SIZE_8MB               (0x3e << 0)
-#	define AGP_APER_SIZE_4MB               (0x3f << 0)
-#	define AGP_APER_SIZE_MASK              (0x3f << 0)
-#define AMCGPIO_A_REG                          0x01a0
-#define AMCGPIO_EN_REG                         0x01a8
-#define AMCGPIO_MASK                           0x0194
-#define AMCGPIO_Y_REG                          0x01a4
-#define BM_STATUS                              0x0160
-#define MPP_TB_CONFIG                          0x01c0 /* ? */
-#define MPP_GP_CONFIG                          0x01c8 /* ? */
-#define CAP0_TRIG_CNTL			       0x0950
-#define CAP1_TRIG_CNTL                         0x09c0 /* ? */
-#define VENDOR_ID                              0x0F00  
-#define DEVICE_ID                              0x0F02  
-#define COMMAND                                0x0F04  
-#define STATUS                                 0x0F06  
-#define REVISION_ID                            0x0F08  
-#define REGPROG_INF                            0x0F09  
-#define SUB_CLASS                              0x0F0A  
-#define BASE_CODE                              0x0F0B  
-#define CACHE_LINE                             0x0F0C  
-#define LATENCY                                0x0F0D  
-#define HEADER                                 0x0F0E  
-#define BIST                                   0x0F0F  
-#define REG_MEM_BASE                           0x0F10  
-#define REG_IO_BASE                            0x0F14  
-#define REG_REG_BASE                           0x0F18
-#define ADAPTER_ID                             0x0F2C
-#define BIOS_ROM                               0x0F30
-#define CAPABILITIES_PTR                       0x0F34  
-#define INTERRUPT_LINE                         0x0F3C  
-#define INTERRUPT_PIN                          0x0F3D  
-#define MIN_GRANT                              0x0F3E  
-#define MAX_LATENCY                            0x0F3F  
-#define ADAPTER_ID_W                           0x0F4C  
-#define PMI_CAP_ID                             0x0F50  
-#define PMI_NXT_CAP_PTR                        0x0F51  
-#define PMI_PMC_REG                            0x0F52  
-#define PM_STATUS                              0x0F54  
-#define PMI_DATA                               0x0F57  
-#define AGP_CAP_ID                             0x0F58  
-#define AGP_STATUS                             0x0F5C  
-#	define AGP_1X_MODE                     0x01
-#	define AGP_2X_MODE                     0x02
-#	define AGP_4X_MODE                     0x04
-#	define AGP_MODE_MASK                   0x07
-#define AGP_COMMAND                            0x0F60  
-#define AIC_CTRL                               0x01D0
-#define AIC_STAT                               0x01D4
-#define AIC_PT_BASE                            0x01D8
-#define AIC_LO_ADDR                            0x01DC  
-#define AIC_HI_ADDR                            0x01E0  
-#define AIC_TLB_ADDR                           0x01E4  
-#define AIC_TLB_DATA                           0x01E8  
-#define DAC_CNTL                               0x0058  
-/* DAC_CNTL bit constants */   
-#	define DAC_8BIT_EN                     0x00000100
-#	define DAC_4BPP_PIX_ORDER              0x00000200
-#	define DAC_CRC_EN                      0x00080000
-#	define DAC_MASK_ALL		       (0xff << 24)
-#	define DAC_VGA_ADR_EN		       (1 << 13)
-#	define DAC_RANGE_CNTL		       (3 << 0)
-#	define DAC_BLANKING		       (1 << 2)
-#define DAC_CNTL2                              0x007c
-/* DAC_CNTL2 bit constants */   
-#	define DAC2_DAC_CLK_SEL                (1 <<  0)
-#	define DAC2_DAC2_CLK_SEL               (1 <<  1)
-#	define DAC2_PALETTE_ACC_CTL            (1 <<  5)
-#define TV_DAC_CNTL                            0x088c
-/* TV_DAC_CNTL bit constants */   
-#	define TV_DAC_STD_MASK                 0x0300
-#	define TV_DAC_RDACPD                   (1 <<  24)
-#	define TV_DAC_GDACPD                   (1 <<  25)
-#	define TV_DAC_BDACPD                   (1 <<  26)
-#define CRTC_GEN_CNTL                          0x0050  
+#	define CFG_VGA_RAM_EN			0x00000100
+#define	CONFIG_MEMSIZE				0x00F8
+#define	CONFIG_APER_0_BASE			0x0100
+#define	CONFIG_APER_1_BASE			0x0104
+#define	CONFIG_APER_SIZE			0x0108
+#define	CONFIG_REG_1_BASE			0x010C
+#define	CONFIG_REG_APER_SIZE			0x0110
+#define	PAD_AGPINPUT_DELAY			0x0164
+#define	PAD_CTLR_STRENGTH			0x0168
+#define	PAD_CTLR_UPDATE				0x016C
+#define	AGP_CNTL				0x0174
+#	define AGP_APER_SIZE_256MB		(0x00 << 0)
+#	define AGP_APER_SIZE_128MB		(0x20 << 0)
+#	define AGP_APER_SIZE_64MB		(0x30 << 0)
+#	define AGP_APER_SIZE_32MB		(0x38 << 0)
+#	define AGP_APER_SIZE_16MB		(0x3c << 0)
+#	define AGP_APER_SIZE_8MB		(0x3e << 0)
+#	define AGP_APER_SIZE_4MB		(0x3f << 0)
+#	define AGP_APER_SIZE_MASK		(0x3f << 0)
+#define	AMCGPIO_A_REG				0x01a0
+#define	AMCGPIO_EN_REG				0x01a8
+#define	AMCGPIO_MASK				0x0194
+#define	AMCGPIO_Y_REG				0x01a4
+#define	BM_STATUS				0x0160
+#define	MPP_TB_CONFIG				0x01c0 /* ? */
+#define	MPP_GP_CONFIG				0x01c8 /* ? */
+#define	VENDOR_ID				0x0F00
+#define	DEVICE_ID				0x0F02
+#define	COMMAND					0x0F04
+#define	STATUS					0x0F06
+#define	REVISION_ID				0x0F08
+#define	REGPROG_INF				0x0F09
+#define	SUB_CLASS				0x0F0A
+#define	CACHE_LINE				0x0F0C
+#define	LATENCY					0x0F0D
+#define	HEADER					0x0F0E
+#define	BIST					0x0F0F
+#define	REG_MEM_BASE				0x0F10
+#define	REG_IO_BASE				0x0F14
+#define	REG_REG_BASE				0x0F18
+#define	ADAPTER_ID				0x0F2C
+#define	BIOS_ROM				0x0F30
+#define	CAPABILITIES_PTR			0x0F34
+#define	INTERRUPT_LINE				0x0F3C
+#define	INTERRUPT_PIN				0x0F3D
+#define	MIN_GRANT				0x0F3E
+#define	MAX_LATENCY				0x0F3F
+#define	ADAPTER_ID_W				0x0F4C
+#define	PMI_CAP_ID				0x0F50
+#define	PMI_NXT_CAP_PTR				0x0F51
+#define	PMI_PMC_REG				0x0F52
+#define	PM_STATUS				0x0F54
+#define	PMI_DATA				0x0F57
+#define	AGP_CAP_ID				0x0F58
+#define	AGP_STATUS				0x0F5C
+#	define AGP_1X_MODE			0x01
+#	define AGP_2X_MODE			0x02
+#	define AGP_4X_MODE			0x04
+#	define AGP_MODE_MASK			0x07
+#define	AGP_COMMAND				0x0F60
+#define	AIC_CTRL				0x01D0
+#define	AIC_STAT				0x01D4
+#define	AIC_PT_BASE				0x01D8
+#define	AIC_LO_ADDR				0x01DC
+#define	AIC_HI_ADDR				0x01E0
+#define	AIC_TLB_ADDR				0x01E4
+#define	AIC_TLB_DATA				0x01E8
+#define	DAC_CNTL				0x0058
+/* DAC_CNTL bit	constants */
+#	define DAC_8BIT_EN			0x00000100
+#	define DAC_4BPP_PIX_ORDER		0x00000200
+#	define DAC_CRC_EN			0x00080000
+#	define DAC_MASK_ALL			(0xff << 24)
+#	define DAC_VGA_ADR_EN			(1 << 13)
+#	define DAC_RANGE_CNTL			(3 << 0)
+#	define DAC_BLANKING			(1 << 2)
+#define	DAC_CNTL2				0x007c
+/* DAC_CNTL2 bit constants */
+#	define DAC2_DAC_CLK_SEL			(1 <<  0)
+#	define DAC2_DAC2_CLK_SEL		(1 <<  1)
+#	define DAC2_PALETTE_ACC_CTL		(1 <<  5)
+#define	TV_DAC_CNTL				0x088c
+/* TV_DAC_CNTL bit constants */
+#	define TV_DAC_STD_MASK			0x0300
+#	define TV_DAC_RDACPD			(1 <<  24)
+#	define TV_DAC_GDACPD			(1 <<  25)
+#	define TV_DAC_BDACPD			(1 <<  26)
+#define	CRTC_GEN_CNTL				0x0050
 /* CRTC_GEN_CNTL bit constants */
-#	define CRTC_DBL_SCAN_EN                0x00000001
-#	define CRTC_INTERLACE_EN               (1 << 1)
-#	define CRTC_CSYNC_EN                   (1 << 4)
-#	define CRTC_CUR_EN                     0x00010000
-#	define CRTC_CUR_MODE_MASK              (7 << 17)
-#	define CRTC_ICON_EN                    (1 << 20)
-#	define CRTC_EXT_DISP_EN      	       (1 << 24)
-#	define CRTC_EN			       (1 << 25)
-#	define CRTC_DISP_REQ_EN_B              (1 << 26)
-#define CRTC2_GEN_CNTL                         0x03f8
-/* CRTC2_GEN_CNTL bit constants */
-#	define CRTC2_DBL_SCAN_EN               (1 <<  0)
-#	define CRTC2_INTERLACE_EN              (1 <<  1)
-#	define CRTC2_SYNC_TRISTAT              (1 <<  4)
-#	define CRTC2_HSYNC_TRISTAT             (1 <<  5)
-#	define CRTC2_VSYNC_TRISTAT             (1 <<  6)
-#	define CRTC2_CRT2_ON                   (1 <<  7)
-#	define CRTC2_ICON_EN                   (1 << 15)
-#	define CRTC2_CUR_EN                    (1 << 16)
-#	define CRTC2_CUR_MODE_MASK             (7 << 20)
-#	define CRTC2_DISP_DIS                  (1 << 23)
-#	define CRTC2_EN                        (1 << 25)
-#	define CRTC2_DISP_REQ_EN_B             (1 << 26)
-#	define CRTC2_HSYNC_DIS                 (1 << 28)
-#	define CRTC2_VSYNC_DIS                 (1 << 29)
-#define MEM_CNTL                               0x0140  
-/* MEM_CNTL bit constants */
-#	define MEM_CTLR_STATUS_IDLE            0x00000000
-#	define MEM_CTLR_STATUS_BUSY            0x00100000
-#	define MEM_SEQNCR_STATUS_IDLE          0x00000000
-#	define MEM_SEQNCR_STATUS_BUSY          0x00200000
-#	define MEM_ARBITER_STATUS_IDLE         0x00000000
-#	define MEM_ARBITER_STATUS_BUSY         0x00400000
-#	define MEM_REQ_UNLOCK                  0x00000000
-#	define MEM_REQ_LOCK                    0x00800000
-#define EXT_MEM_CNTL                           0x0144  
-#define MC_AGP_LOCATION                        0x014C  
-#define MEM_IO_CNTL_A0                         0x0178  
-#define MEM_INIT_LATENCY_TIMER                 0x0154  
-#define MEM_SDRAM_MODE_REG                     0x0158  
-#define AGP_BASE                               0x0170  
-#define MEM_IO_CNTL_A1                         0x017C  
-#define MEM_IO_CNTL_B0                         0x0180
-#define MEM_IO_CNTL_B1                         0x0184
-#define MC_DEBUG                               0x0188
-#define MC_STATUS                              0x0150  
-#define MEM_IO_OE_CNTL                         0x018C  
-#define MC_FB_LOCATION                         0x0148  
-#define HOST_PATH_CNTL                         0x0130  
-#define MEM_VGA_WP_SEL                         0x0038  
-#define MEM_VGA_RP_SEL                         0x003C  
-#define HDP_DEBUG                              0x0138  
-#define SW_SEMAPHORE                           0x013C  
-#define SURFACE_CNTL                           0x0B00  
-/* SURFACE_CNTL bit constants */
-#	define SURF_TRANSLATION_DIS	       (1 << 8)
-#	define NONSURF_AP0_SWP_16BPP	       (1 << 20)
-#	define NONSURF_AP0_SWP_32BPP	       (2 << 20)
-#define SURFACE0_LOWER_BOUND                   0x0B04  
-#define SURFACE1_LOWER_BOUND                   0x0B14  
-#define SURFACE2_LOWER_BOUND                   0x0B24  
-#define SURFACE3_LOWER_BOUND                   0x0B34  
-#define SURFACE4_LOWER_BOUND                   0x0B44  
-#define SURFACE5_LOWER_BOUND                   0x0B54
-#define SURFACE6_LOWER_BOUND                   0x0B64
-#define SURFACE7_LOWER_BOUND                   0x0B74
-#define SURFACE0_UPPER_BOUND                   0x0B08  
-#define SURFACE1_UPPER_BOUND                   0x0B18  
-#define SURFACE2_UPPER_BOUND                   0x0B28  
-#define SURFACE3_UPPER_BOUND                   0x0B38  
-#define SURFACE4_UPPER_BOUND                   0x0B48  
-#define SURFACE5_UPPER_BOUND                   0x0B58  
-#define SURFACE6_UPPER_BOUND                   0x0B68  
-#define SURFACE7_UPPER_BOUND                   0x0B78  
-#define SURFACE0_INFO                          0x0B0C  
-#define SURFACE1_INFO                          0x0B1C  
-#define SURFACE2_INFO                          0x0B2C  
-#define SURFACE3_INFO                          0x0B3C  
-#define SURFACE4_INFO                          0x0B4C  
-#define SURFACE5_INFO                          0x0B5C  
-#define SURFACE6_INFO                          0x0B6C
-#define SURFACE7_INFO                          0x0B7C
-#define SURFACE_ACCESS_FLAGS                   0x0BF8
-#define SURFACE_ACCESS_CLR                     0x0BFC  
-#define GEN_INT_CNTL                           0x0040  
-#define GEN_INT_STATUS                         0x0044  
-#	define VSYNC_INT_AK                    (1 <<  2)
-#	define VSYNC_INT                       (1 <<  2)
-#define CRTC_EXT_CNTL                          0x0054
+#	define CRTC_DBL_SCAN_EN			0x00000001
+#	define CRTC_INTERLACE_EN		(1 << 1)
+#	define CRTC_CSYNC_EN			(1 << 4)
+#	define CRTC_CUR_EN			0x00010000
+#	define CRTC_CUR_MODE_MASK		(7 << 17)
+#	define CRTC_ICON_EN			(1 << 20)
+#	define CRTC_EXT_DISP_EN			(1 << 24)
+#	define CRTC_EN				(1 << 25)
+#	define CRTC_DISP_REQ_EN_B		(1 << 26)
+#define	CRTC2_GEN_CNTL				0x03f8
+/* CRTC2_GEN_CNTL bit constants	*/
+#	define CRTC2_DBL_SCAN_EN		(1 <<  0)
+#	define CRTC2_INTERLACE_EN		(1 <<  1)
+#	define CRTC2_SYNC_TRISTAT		(1 <<  4)
+#	define CRTC2_HSYNC_TRISTAT		(1 <<  5)
+#	define CRTC2_VSYNC_TRISTAT		(1 <<  6)
+#	define CRTC2_CRT2_ON			(1 <<  7)
+#	define CRTC2_ICON_EN			(1 << 15)
+#	define CRTC2_CUR_EN			(1 << 16)
+#	define CRTC2_CUR_MODE_MASK		(7 << 20)
+#	define CRTC2_DISP_DIS			(1 << 23)
+#	define CRTC2_EN				(1 << 25)
+#	define CRTC2_DISP_REQ_EN_B		(1 << 26)
+#	define CRTC2_HSYNC_DIS			(1 << 28)
+#	define CRTC2_VSYNC_DIS			(1 << 29)
+#define	MEM_CNTL				0x0140
+/* MEM_CNTL bit	constants */
+#	define MEM_CTLR_STATUS_IDLE		0x00000000
+#	define MEM_CTLR_STATUS_BUSY		0x00100000
+#	define MEM_SEQNCR_STATUS_IDLE		0x00000000
+#	define MEM_SEQNCR_STATUS_BUSY		0x00200000
+#	define MEM_ARBITER_STATUS_IDLE		0x00000000
+#	define MEM_ARBITER_STATUS_BUSY		0x00400000
+#	define MEM_REQ_UNLOCK			0x00000000
+#	define MEM_REQ_LOCK			0x00800000
+#define	EXT_MEM_CNTL				0x0144
+#define	MC_AGP_LOCATION				0x014C
+#define	MEM_IO_CNTL_A0				0x0178
+#define	MEM_INIT_LATENCY_TIMER			0x0154
+#define	MEM_SDRAM_MODE_REG			0x0158
+#define	AGP_BASE				0x0170
+#define	MEM_IO_CNTL_A1				0x017C
+#define	MEM_IO_CNTL_B0				0x0180
+#define	MEM_IO_CNTL_B1				0x0184
+#define	MC_DEBUG				0x0188
+#define	MC_STATUS				0x0150
+#define	MEM_IO_OE_CNTL				0x018C
+#define	MC_FB_LOCATION				0x0148
+#define	HOST_PATH_CNTL				0x0130
+#define	MEM_VGA_WP_SEL				0x0038
+#define	MEM_VGA_RP_SEL				0x003C
+#define	HDP_DEBUG				0x0138
+#define	SW_SEMAPHORE				0x013C
+#define	SURFACE_CNTL				0x0B00
+/* SURFACE_CNTL	bit constants */
+#	define SURF_TRANSLATION_DIS		(1 << 8)
+#	define NONSURF_AP0_SWP_16BPP		(1 << 20)
+#	define NONSURF_AP0_SWP_32BPP		(2 << 20)
+#define	SURFACE0_LOWER_BOUND			0x0B04
+#define	SURFACE1_LOWER_BOUND			0x0B14
+#define	SURFACE2_LOWER_BOUND			0x0B24
+#define	SURFACE3_LOWER_BOUND			0x0B34
+#define	SURFACE4_LOWER_BOUND			0x0B44
+#define	SURFACE5_LOWER_BOUND			0x0B54
+#define	SURFACE6_LOWER_BOUND			0x0B64
+#define	SURFACE7_LOWER_BOUND			0x0B74
+#define	SURFACE0_UPPER_BOUND			0x0B08
+#define	SURFACE1_UPPER_BOUND			0x0B18
+#define	SURFACE2_UPPER_BOUND			0x0B28
+#define	SURFACE3_UPPER_BOUND			0x0B38
+#define	SURFACE4_UPPER_BOUND			0x0B48
+#define	SURFACE5_UPPER_BOUND			0x0B58
+#define	SURFACE6_UPPER_BOUND			0x0B68
+#define	SURFACE7_UPPER_BOUND			0x0B78
+#define	SURFACE0_INFO				0x0B0C
+#define	SURFACE1_INFO				0x0B1C
+#define	SURFACE2_INFO				0x0B2C
+#define	SURFACE3_INFO				0x0B3C
+#define	SURFACE4_INFO				0x0B4C
+#define	SURFACE5_INFO				0x0B5C
+#define	SURFACE6_INFO				0x0B6C
+#define	SURFACE7_INFO				0x0B7C
+#define	SURFACE_ACCESS_FLAGS			0x0BF8
+#define	SURFACE_ACCESS_CLR			0x0BFC
+#define	GEN_INT_CNTL				0x0040
+#define	GEN_INT_STATUS				0x0044
+#	define VSYNC_INT_AK			(1 <<  2)
+#	define VSYNC_INT			(1 <<  2)
+#define	CRTC_EXT_CNTL				0x0054
 /* CRTC_EXT_CNTL bit constants */
-#	define CRTC_VGA_XOVERSCAN              (1 <<  0)
-#	define VGA_ATI_LINEAR                  0x00000008
-#	define VGA_128KAP_PAGING               0x00000010
-#	define XCRT_CNT_EN		       (1 << 6)
-#	define CRTC_HSYNC_DIS		       (1 << 8)
-#	define CRTC_VSYNC_DIS		       (1 << 9)
-#	define CRTC_DISPLAY_DIS		       (1 << 10)
-#	define CRTC_SYNC_TRISTAT               (1 << 11)
-#	define CRTC_CRT_ON                     (1 << 15)
-#define CRTC_EXT_CNTL_DPMS_BYTE                0x0055
-#	define CRTC_HSYNC_DIS_BYTE             (1 <<  0)
-#	define CRTC_VSYNC_DIS_BYTE             (1 <<  1)
-#	define CRTC_DISPLAY_DIS_BYTE           (1 <<  2)
-#define RB3D_CNTL			       0x1C3C  
-#define WAIT_UNTIL                             0x1720  
-#define ISYNC_CNTL                             0x1724  
-#define RBBM_GUICNTL                           0x172C  
-#define RBBM_STATUS                            0x0E40  
-#	define RBBM_FIFOCNT_MASK               0x007f
-#	define RBBM_ACTIVE                     (1 << 31)
-#define RBBM_STATUS_alt_1                      0x1740  
-#define RBBM_CNTL                              0x00EC  
-#define RBBM_CNTL_alt_1                        0x0E44  
-#define RBBM_SOFT_RESET                        0x00F0  
+#	define CRTC_VGA_XOVERSCAN		(1 <<  0)
+#	define VGA_ATI_LINEAR			0x00000008
+#	define VGA_128KAP_PAGING		0x00000010
+#	define XCRT_CNT_EN			(1 << 6)
+#	define CRTC_HSYNC_DIS			(1 << 8)
+#	define CRTC_VSYNC_DIS			(1 << 9)
+#	define CRTC_DISPLAY_DIS			(1 << 10)
+#	define CRTC_SYNC_TRISTAT		(1 << 11)
+#	define CRTC_CRT_ON			(1 << 15)
+#define	CRTC_EXT_CNTL_DPMS_BYTE			0x0055
+#	define CRTC_HSYNC_DIS_BYTE		(1 <<  0)
+#	define CRTC_VSYNC_DIS_BYTE		(1 <<  1)
+#	define CRTC_DISPLAY_DIS_BYTE		(1 <<  2)
+#define	RB3D_CNTL				0x1C3C
+#define	WAIT_UNTIL				0x1720
+#define	ISYNC_CNTL				0x1724
+#define	RBBM_GUICNTL				0x172C
+#define	RBBM_STATUS				0x0E40
+#	define RBBM_FIFOCNT_MASK		0x007f
+#	define RBBM_ACTIVE			(1 << 31)
+#define	RBBM_STATUS_alt_1			0x1740
+#define	RBBM_CNTL				0x00EC
+#define	RBBM_CNTL_alt_1				0x0E44
+#define	RBBM_SOFT_RESET				0x00F0
 /* RBBM_SOFT_RESET bit constants */
-#	define SOFT_RESET_CP          	       (1 <<  0)
-#	define SOFT_RESET_HI           	       (1 <<  1)
-#	define SOFT_RESET_SE           	       (1 <<  2)
-#	define SOFT_RESET_RE           	       (1 <<  3)
-#	define SOFT_RESET_PP           	       (1 <<  4)
-#	define SOFT_RESET_E2           	       (1 <<  5)
-#	define SOFT_RESET_RB           	       (1 <<  6)
-#	define SOFT_RESET_HDP          	       (1 <<  7)
-#define RBBM_SOFT_RESET_alt_1                  0x0E48  
-#define NQWAIT_UNTIL                           0x0E50  
-#define RBBM_DEBUG                             0x0E6C
-#define RBBM_CMDFIFO_ADDR                      0x0E70
-#define RBBM_CMDFIFO_DATAL                     0x0E74
-#define RBBM_CMDFIFO_DATAH                     0x0E78  
-#define RBBM_CMDFIFO_STAT                      0x0E7C  
-#define CRTC_STATUS                            0x005C  
+#	define SOFT_RESET_CP			(1 <<  0)
+#	define SOFT_RESET_HI			(1 <<  1)
+#	define SOFT_RESET_SE			(1 <<  2)
+#	define SOFT_RESET_RE			(1 <<  3)
+#	define SOFT_RESET_PP			(1 <<  4)
+#	define SOFT_RESET_E2			(1 <<  5)
+#	define SOFT_RESET_RB			(1 <<  6)
+#	define SOFT_RESET_HDP			(1 <<  7)
+#define	RBBM_SOFT_RESET_alt_1			0x0E48
+#define	NQWAIT_UNTIL				0x0E50
+#define	RBBM_DEBUG				0x0E6C
+#define	RBBM_CMDFIFO_ADDR			0x0E70
+#define	RBBM_CMDFIFO_DATAL			0x0E74
+#define	RBBM_CMDFIFO_DATAH			0x0E78
+#define	RBBM_CMDFIFO_STAT			0x0E7C
+#define	CRTC_STATUS				0x005C
 /* CRTC_STATUS bit constants */
-#	define CRTC_VBLANK                     0x00000001
-#	define CRTC_VBLANK_SAVE               (1 <<  1)
-#define GPIO_VGA_DDC                           0x0060  
-#define GPIO_DVI_DDC                           0x0064  
-#define GPIO_MONID                             0x0068  
-#define PALETTE_INDEX                          0x00B0  
-#define PALETTE_DATA                           0x00B4  
-#define PALETTE_30_DATA                        0x00B8  
-#define CRTC_H_TOTAL_DISP                      0x0200  
-#	define CRTC_H_TOTAL                    (0x03ff << 0)
-#	define CRTC_H_TOTAL_SHIFT              0
-#	define CRTC_H_DISP                     (0x01ff << 16)
-#	define CRTC_H_DISP_SHIFT               16
-#define CRTC2_H_TOTAL_DISP                     0x0300
-#	define CRTC2_H_TOTAL                   (0x03ff << 0)
-#	define CRTC2_H_TOTAL_SHIFT             0
-#	define CRTC2_H_DISP                    (0x01ff << 16)
-#	define CRTC2_H_DISP_SHIFT              16
-#define CRTC_H_SYNC_STRT_WID                   0x0204  
-#	define CRTC_H_SYNC_STRT_PIX            (0x07  <<  0)
-#	define CRTC_H_SYNC_STRT_CHAR           (0x3ff <<  3)
-#	define CRTC_H_SYNC_STRT_CHAR_SHIFT     3
-#	define CRTC_H_SYNC_WID                 (0x3f  << 16)
-#	define CRTC_H_SYNC_WID_SHIFT           16
-#	define CRTC_H_SYNC_POL                 (1     << 23)
-#define CRTC2_H_SYNC_STRT_WID                  0x0304
-#	define CRTC2_H_SYNC_STRT_PIX           (0x07  <<  0)
-#	define CRTC2_H_SYNC_STRT_CHAR          (0x3ff <<  3)
-#	define CRTC2_H_SYNC_STRT_CHAR_SHIFT    3
-#	define CRTC2_H_SYNC_WID                (0x3f  << 16)
-#	define CRTC2_H_SYNC_WID_SHIFT          16
-#	define CRTC2_H_SYNC_POL                (1     << 23)
-#define CRTC_V_TOTAL_DISP                      0x0208  
-#	define CRTC_V_TOTAL                    (0x07ff << 0)
-#	define CRTC_V_TOTAL_SHIFT              0
-#	define CRTC_V_DISP                     (0x07ff << 16)
-#	define CRTC_V_DISP_SHIFT               16
-#define CRTC2_V_TOTAL_DISP                     0x0308
-#	define CRTC2_V_TOTAL                   (0x07ff << 0)
-#	define CRTC2_V_TOTAL_SHIFT             0
-#	define CRTC2_V_DISP                    (0x07ff << 16)
-#	define CRTC2_V_DISP_SHIFT              16
-#define CRTC_V_SYNC_STRT_WID                   0x020C  
-#	define CRTC_V_SYNC_STRT                (0x7ff <<  0)
-#	define CRTC_V_SYNC_STRT_SHIFT          0
-#	define CRTC_V_SYNC_WID                 (0x1f  << 16)
-#	define CRTC_V_SYNC_WID_SHIFT           16
-#	define CRTC_V_SYNC_POL                 (1     << 23)
-#define CRTC2_V_SYNC_STRT_WID                  0x030C
-#	define CRTC2_V_SYNC_STRT               (0x7ff <<  0)
-#	define CRTC2_V_SYNC_STRT_SHIFT         0
-#	define CRTC2_V_SYNC_WID                (0x1f  << 16)
-#	define CRTC2_V_SYNC_WID_SHIFT          16
-#	define CRTC2_V_SYNC_POL                (1     << 23)
-#define CRTC_VLINE_CRNT_VLINE                  0x0210  
-#	define CRTC_CRNT_VLINE_MASK            (0x7ff << 16)
-#define CRTC2_VLINE_CRNT_VLINE                 0x0310
-#define CRTC_CRNT_FRAME                        0x0214
-#define CRTC2_CRNT_FRAME                       0x0314
-#define CRTC_GUI_TRIG_VLINE                    0x0218
-#define CRTC2_GUI_TRIG_VLINE                   0x0318
-#define CRTC_DEBUG                             0x021C
-#define CRTC2_DEBUG                            0x031C
-#define CRTC_OFFSET_RIGHT                      0x0220  
-#define CRTC_OFFSET                            0x0224  
-#define CRTC2_OFFSET                           0x0324
-#define CRTC_OFFSET_CNTL                       0x0228  
-#	define CRTC_TILE_EN                    (1 << 15)
-#define CRTC2_OFFSET_CNTL                      0x0328
-#	define CRTC2_TILE_EN                   (1 << 15)
-#define CRTC_PITCH                             0x022C  
-#define CRTC2_PITCH                            0x032C
-#define TMDS_CRC                               0x02a0
-#define OVR_CLR                                0x0230  
-#define OVR_WID_LEFT_RIGHT                     0x0234  
-#define OVR_WID_TOP_BOTTOM                     0x0238  
-#define DISPLAY_BASE_ADDR                      0x023C  
-#define SNAPSHOT_VH_COUNTS                     0x0240  
-#define SNAPSHOT_F_COUNT                       0x0244  
-#define N_VIF_COUNT                            0x0248  
-#define SNAPSHOT_VIF_COUNT                     0x024C  
-#define FP_CRTC_H_TOTAL_DISP                   0x0250  
-#define FP_CRTC2_H_TOTAL_DISP                  0x0350
-#define FP_CRTC_V_TOTAL_DISP                   0x0254  
-#define FP_CRTC2_V_TOTAL_DISP                  0x0354
-#	define FP_CRTC_H_TOTAL_MASK            0x000003ff
-#	define FP_CRTC_H_DISP_MASK             0x01ff0000
-#	define FP_CRTC_V_TOTAL_MASK            0x00000fff
-#	define FP_CRTC_V_DISP_MASK             0x0fff0000
-#	define FP_H_SYNC_STRT_CHAR_MASK        0x00001ff8
-#	define FP_H_SYNC_WID_MASK              0x003f0000
-#	define FP_V_SYNC_STRT_MASK             0x00000fff
-#	define FP_V_SYNC_WID_MASK              0x001f0000
-#	define FP_CRTC_H_TOTAL_SHIFT           0x00000000
-#	define FP_CRTC_H_DISP_SHIFT            0x00000010
-#	define FP_CRTC_V_TOTAL_SHIFT           0x00000000
-#	define FP_CRTC_V_DISP_SHIFT            0x00000010
-#	define FP_H_SYNC_STRT_CHAR_SHIFT       0x00000003
-#	define FP_H_SYNC_WID_SHIFT             0x00000010
-#	define FP_V_SYNC_STRT_SHIFT            0x00000000
-#	define FP_V_SYNC_WID_SHIFT             0x00000010
-#define CRT_CRTC_H_SYNC_STRT_WID               0x0258
-#define CRT_CRTC_V_SYNC_STRT_WID               0x025C
-#define CUR_OFFSET                             0x0260
-#define CUR_HORZ_VERT_POSN                     0x0264  
-#define CUR_HORZ_VERT_OFF                      0x0268  
+#	define CRTC_VBLANK			0x00000001
+#	define CRTC_VBLANK_SAVE			( 1 <<	1)
+#define	GPIO_VGA_DDC				0x0060
+#define	GPIO_DVI_DDC				0x0064
+#define	GPIO_MONID				0x0068
+#define	PALETTE_INDEX				0x00B0
+#define	PALETTE_DATA				0x00B4
+#define	PALETTE_30_DATA				0x00B8
+#define	CRTC_H_TOTAL_DISP			0x0200
+#	define CRTC_H_TOTAL			(0x03ff	<< 0)
+#	define CRTC_H_TOTAL_SHIFT		0
+#	define CRTC_H_DISP			(0x01ff	<< 16)
+#	define CRTC_H_DISP_SHIFT		16
+#define	CRTC2_H_TOTAL_DISP			0x0300
+#	define CRTC2_H_TOTAL			(0x03ff	<< 0)
+#	define CRTC2_H_TOTAL_SHIFT		0
+#	define CRTC2_H_DISP			(0x01ff	<< 16)
+#	define CRTC2_H_DISP_SHIFT		16
+#define	CRTC_H_SYNC_STRT_WID			0x0204
+#	define CRTC_H_SYNC_STRT_PIX		(0x07  <<  0)
+#	define CRTC_H_SYNC_STRT_CHAR		(0x3ff <<  3)
+#	define CRTC_H_SYNC_STRT_CHAR_SHIFT	3
+#	define CRTC_H_SYNC_WID			(0x3f  << 16)
+#	define CRTC_H_SYNC_WID_SHIFT		16
+#	define CRTC_H_SYNC_POL			(1     << 23)
+#define	CRTC2_H_SYNC_STRT_WID			0x0304
+#	define CRTC2_H_SYNC_STRT_PIX		(0x07  <<  0)
+#	define CRTC2_H_SYNC_STRT_CHAR		(0x3ff <<  3)
+#	define CRTC2_H_SYNC_STRT_CHAR_SHIFT	3
+#	define CRTC2_H_SYNC_WID			(0x3f  << 16)
+#	define CRTC2_H_SYNC_WID_SHIFT		16
+#	define CRTC2_H_SYNC_POL			(1     << 23)
+#define	CRTC_V_TOTAL_DISP			0x0208
+#	define CRTC_V_TOTAL			(0x07ff	<< 0)
+#	define CRTC_V_TOTAL_SHIFT		0
+#	define CRTC_V_DISP			(0x07ff	<< 16)
+#	define CRTC_V_DISP_SHIFT		16
+#define	CRTC2_V_TOTAL_DISP			0x0308
+#	define CRTC2_V_TOTAL			(0x07ff	<< 0)
+#	define CRTC2_V_TOTAL_SHIFT		0
+#	define CRTC2_V_DISP			(0x07ff	<< 16)
+#	define CRTC2_V_DISP_SHIFT		16
+#define	CRTC_V_SYNC_STRT_WID			0x020C
+#	define CRTC_V_SYNC_STRT			(0x7ff <<  0)
+#	define CRTC_V_SYNC_STRT_SHIFT		0
+#	define CRTC_V_SYNC_WID			(0x1f  << 16)
+#	define CRTC_V_SYNC_WID_SHIFT		16
+#	define CRTC_V_SYNC_POL			(1     << 23)
+#define	CRTC2_V_SYNC_STRT_WID			0x030C
+#	define CRTC2_V_SYNC_STRT		(0x7ff <<  0)
+#	define CRTC2_V_SYNC_STRT_SHIFT		0
+#	define CRTC2_V_SYNC_WID			(0x1f  << 16)
+#	define CRTC2_V_SYNC_WID_SHIFT		16
+#	define CRTC2_V_SYNC_POL			(1     << 23)
+#define	CRTC_VLINE_CRNT_VLINE			0x0210
+#	define CRTC_CRNT_VLINE_MASK		(0x7ff << 16)
+#define	CRTC2_VLINE_CRNT_VLINE			0x0310
+#define	CRTC_CRNT_FRAME				0x0214
+#define	CRTC2_CRNT_FRAME			0x0314
+#define	CRTC_GUI_TRIG_VLINE			0x0218
+#define	CRTC2_GUI_TRIG_VLINE			0x0318
+#define	CRTC_DEBUG				0x021C
+#define	CRTC2_DEBUG				0x031C
+#define	CRTC_OFFSET_RIGHT			0x0220
+#define	CRTC_OFFSET				0x0224
+#define	CRTC2_OFFSET				0x0324
+#define	CRTC_OFFSET_CNTL			0x0228
+#	define CRTC_TILE_EN			(1 << 15)
+#define	CRTC2_OFFSET_CNTL			0x0328
+#	define CRTC2_TILE_EN			(1 << 15)
+#define	CRTC_PITCH				0x022C
+#define	CRTC2_PITCH				0x032C
+#define	TMDS_CRC				0x02a0
+#define	OVR_CLR					0x0230
+#define	OVR_WID_LEFT_RIGHT			0x0234
+#define	OVR_WID_TOP_BOTTOM			0x0238
+#define	DISPLAY_BASE_ADDR			0x023C
+#define	SNAPSHOT_VH_COUNTS			0x0240
+#define	SNAPSHOT_F_COUNT			0x0244
+#define	N_VIF_COUNT				0x0248
+#define	SNAPSHOT_VIF_COUNT			0x024C
+#define	FP_CRTC_H_TOTAL_DISP			0x0250
+#define	FP_CRTC2_H_TOTAL_DISP			0x0350
+#define	FP_CRTC_V_TOTAL_DISP			0x0254
+#define	FP_CRTC2_V_TOTAL_DISP			0x0354
+#	define FP_CRTC_H_TOTAL_MASK		0x000003ff
+#	define FP_CRTC_H_DISP_MASK		0x01ff0000
+#	define FP_CRTC_V_TOTAL_MASK		0x00000fff
+#	define FP_CRTC_V_DISP_MASK		0x0fff0000
+#	define FP_H_SYNC_STRT_CHAR_MASK		0x00001ff8
+#	define FP_H_SYNC_WID_MASK		0x003f0000
+#	define FP_V_SYNC_STRT_MASK		0x00000fff
+#	define FP_V_SYNC_WID_MASK		0x001f0000
+#	define FP_CRTC_H_TOTAL_SHIFT		0x00000000
+#	define FP_CRTC_H_DISP_SHIFT		0x00000010
+#	define FP_CRTC_V_TOTAL_SHIFT		0x00000000
+#	define FP_CRTC_V_DISP_SHIFT		0x00000010
+#	define FP_H_SYNC_STRT_CHAR_SHIFT	0x00000003
+#	define FP_H_SYNC_WID_SHIFT		0x00000010
+#	define FP_V_SYNC_STRT_SHIFT		0x00000000
+#	define FP_V_SYNC_WID_SHIFT		0x00000010
+#define	CRT_CRTC_H_SYNC_STRT_WID		0x0258
+#define	CRT_CRTC_V_SYNC_STRT_WID		0x025C
+#define	CUR_OFFSET				0x0260
+#define	CUR_HORZ_VERT_POSN			0x0264
+#define	CUR_HORZ_VERT_OFF			0x0268
 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
-#	define CUR_LOCK                        0x80000000
-#define CUR_CLR0                               0x026C  
-#define CUR_CLR1                               0x0270  
-#define CUR2_OFFSET                            0x0360
-#define CUR2_HORZ_VERT_POSN                    0x0364
-#define CUR2_HORZ_VERT_OFF                     0x0368
-#	define CUR2_LOCK                       (1 << 31)
-#define CUR2_CLR0                              0x036c
-#define CUR2_CLR1                              0x0370
-#define FP_HORZ_VERT_ACTIVE                    0x0278  
-#define CRTC_MORE_CNTL                         0x027C  
-#define DAC_EXT_CNTL                           0x0280  
-#define FP_GEN_CNTL                            0x0284  
+#	define CUR_LOCK				0x80000000
+#define	CUR_CLR0				0x026C
+#define	CUR_CLR1				0x0270
+#define	CUR2_OFFSET				0x0360
+#define	CUR2_HORZ_VERT_POSN			0x0364
+#define	CUR2_HORZ_VERT_OFF			0x0368
+#	define CUR2_LOCK			(1 << 31)
+#define	CUR2_CLR0				0x036c
+#define	CUR2_CLR1				0x0370
+#define	FP_HORZ_VERT_ACTIVE			0x0278
+#define	CRTC_MORE_CNTL				0x027C
+#define	DAC_EXT_CNTL				0x0280
+#define	FP_GEN_CNTL				0x0284
 /* FP_GEN_CNTL bit constants */
-#	define FP_FPON                         (1 <<  0)
-#	define FP_TMDS_EN                      (1 <<  2)
-#	define FP_EN_TMDS                      (1 <<  7)
-#	define FP_DETECT_SENSE                 (1 <<  8)
-#	define FP_SEL_CRTC2                    (1 << 13)
-#	define FP_CRTC_DONT_SHADOW_HPAR        (1 << 15)
-#	define FP_CRTC_DONT_SHADOW_VPAR        (1 << 16)
-#	define FP_CRTC_DONT_SHADOW_HEND        (1 << 17)
-#	define FP_CRTC_USE_SHADOW_VEND         (1 << 18)
-#	define FP_RMX_HVSYNC_CONTROL_EN        (1 << 20)
-#	define FP_DFP_SYNC_SEL                 (1 << 21)
-#	define FP_CRTC_LOCK_8DOT               (1 << 22)
-#	define FP_CRT_SYNC_SEL                 (1 << 23)
-#	define FP_USE_SHADOW_EN                (1 << 24)
-#	define FP_CRT_SYNC_ALT                 (1 << 26)
-#define FP2_GEN_CNTL                           0x0288
-/* FP2_GEN_CNTL bit constants */
-#	define FP2_FPON