diff options
author | diego <diego@b3059339-0415-0410-9bf9-f77b7e298cf2> | 2007-03-17 21:01:37 +0000 |
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committer | diego <diego@b3059339-0415-0410-9bf9-f77b7e298cf2> | 2007-03-17 21:01:37 +0000 |
commit | 8f191b6d4402119d03065bd8ca7acc2518b96173 (patch) | |
tree | df83c760e409d3b629cc9a95cae580ec0775ca4a | |
parent | aa03d96676d8fdfaabf8e197810f381fd2dd9692 (diff) | |
download | mpv-8f191b6d4402119d03065bd8ca7acc2518b96173.tar.bz2 mpv-8f191b6d4402119d03065bd8ca7acc2518b96173.tar.xz |
Remove radeonfb, the version in the Linux kernel is much better.
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@22707 b3059339-0415-0410-9bf9-f77b7e298cf2
-rw-r--r-- | drivers/Makefile | 5 | ||||
-rw-r--r-- | drivers/radeon/radeonfb.c | 3175 |
2 files changed, 2 insertions, 3178 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index d74cd28f2a..b9bac2a61e 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -4,17 +4,16 @@ MDIR = /lib/modules/$(VERSION)/misc CFLAGS = -O2 -D__KERNEL__ -DMODULE -I$(KERNEL_INCLUDES) -Wall -include $(KERNEL_INCLUDES)/linux/modversions.h -OBJS = mga_vid.o tdfx_vid.o radeon/radeonfb.o radeon/radeon_vid.o radeon/rage128_vid.o +OBJS = mga_vid.o tdfx_vid.o radeon/radeon_vid.o radeon/rage128_vid.o all: $(OBJS) mga_vid_test tdfx_vid_test mga_vid.o: mga_vid.c mga_vid.h tdfx_vid.o: tdfx_vid.c 3dfx.h -radeon/radeonfb.o: radeon/radeonfb.c radeon/radeon.h radeon/radeon_vid.o: radeon/radeon_vid.c radeon/radeon.h radeon/radeon_vid.h radeon/rage128_vid.o: radeon/radeon_vid.c radeon/radeon.h radeon/radeon_vid.h $(CC) $(CFLAGS) -DRAGE128 -c $< -o $@ -radeon/radeonfb.o radeon/radeon_vid.o radeon/rage128_vid.o: +radeon/radeon_vid.o radeon/rage128_vid.o: CFLAGS += -fomit-frame-pointer -fno-strict-aliasing -fno-common -ffast-math %_test: %_test.c diff --git a/drivers/radeon/radeonfb.c b/drivers/radeon/radeonfb.c deleted file mode 100644 index 240070add9..0000000000 --- a/drivers/radeon/radeonfb.c +++ /dev/null @@ -1,3175 +0,0 @@ -/* - * drivers/video/radeonfb.c - * framebuffer driver for ATI Radeon chipset video boards - * - * Copyright 2000 Ani Joshi <ajoshi@unixbox.com> - * - * - * ChangeLog: - * 2000-08-03 initial version 0.0.1 - * 2000-09-10 more bug fixes, public release 0.0.5 - * 2001-02-19 mode bug fixes, 0.0.7 - * 2001-07-05 fixed scrolling issues, engine initialization, - * and minor mode tweaking, 0.0.9 - * - * 2001-09-07 Radeon VE support - * 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru> - * (limitations: on dualhead Radeons (VE, M6, M7) - * driver works only on second head (DVI port). - * TVout is not supported too. M6 & M7 chips - * currently are not supported. Driver has a lot - * of other bugs. Probably they can be solved by - * importing XFree86 code, which has ATI's support)., - * 0.0.11 - * 2001-09-13 merge Ani Joshi radeonfb-0.1.0: - * console switching fixes, blanking fixes, - * 0.1.0-ve.0 - * 2001-09-18 Radeon VE, M6 support (by Nick Kurshev <nickols_k@mail.ru>), - * Fixed bug of rom bios detection on VE (by NK), - * Minor code cleanup (by NK), - * Enable CRT port on VE (by NK), - * Disable SURFACE_CNTL because mplayer doesn't work - * propertly (by NK) - * 0.1.0-ve.1 - * 2001-09-25 MTRR support (by NK) - * 0.1.0-ve.2 - * 2001-12-17 sync with 0.1.1: - * PanelYRes - module parameter - * - rage theatre (please see gatos.sf.net) - * - buggy tvout detection (need radeon_i2c) - * + better powerpc support - * + better radeon2 pll computing - * * Note: my stuff still work better for me than official - * linux driver :( - * Special thanks to ATI DevRel team for their hardware donations. - * - * LIMITATIONS: on dualhead Radeons (VE, M6, M7) driver doesn't work in - * dual monitor configuration. TVout is not supported too. - * Probably these problems can be solved by importing XFree86 code, which - * has ATI's support. - * - * Mini-HOWTO: This driver doesn't accept any options. It only switches your - * video card to graphics mode. Standard way to change video modes and other - * video attributes is using 'fbset' utility. - * Sample: - * - * #!/bin/sh - * fbset -fb /dev/fb0 -xres 640 -yres 480 -depth 32 -vxres 640 -vyres 480 -left 70 -right 50 -upper 70 -lower 70 -laced false -pixclock 39767 - * -*/ - -#define RADEON_VERSION "0.1.1-ve" - -#include <linux/config.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/tty.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/console.h> -#include <linux/selection.h> -#include <linux/ioport.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/unistd.h> - -#include <asm/io.h> - -#include <video/fbcon.h> -#include <video/fbcon-cfb8.h> -#include <video/fbcon-cfb16.h> -#include <video/fbcon-cfb24.h> -#include <video/fbcon-cfb32.h> - -#ifdef CONFIG_MTRR -#include <asm/mtrr.h> -#endif -#if defined(__powerpc__) -#include <asm/prom.h> -#endif - -#include "radeon.h" - - -#define DEBUG 0 - -#if DEBUG -#define RTRACE printk -#else -#define RTRACE(...) ((void)0) -#endif - -MODULE_AUTHOR("Ani Joshi. (Radeon VE extensions by Nick Kurshev)"); -MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset. Ver: "RADEON_VERSION); -#ifdef MODULE_LICENSE -MODULE_LICENSE("GPL"); -#endif -#ifdef CONFIG_MTRR -MODULE_PARM(nomtrr, "i"); -MODULE_PARM_DESC(nomtrr, "Don't touch MTRR (touch=0(default))"); -#endif -MODULE_PARM(yres_panel, "i"); -MODULE_PARM_DESC(yres_panel, "Force DFP height"); - - -enum radeon_chips { - RADEON_QD, - RADEON_QE, - RADEON_QF, - RADEON_QG, - RADEON_QY, - RADEON_QZ, - RADEON_LY, - RADEON_LZ, - RADEON_LW, - R200_QL, - R200_BB, - RV200_QW -}; - -enum radeon_montype -{ - MT_NONE, - MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */ - MT_LCD, /* Liquid Crystal Display */ - MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */ - MT_CTV, /* Composite TV out (not in VE) */ - MT_STV /* S-Video TV out (probably in VE only) */ -}; - -static struct pci_device_id radeonfb_pci_table[] __devinitdata = { - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_R200_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, R200_QL}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_R200_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, R200_BB}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RV200_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RV200_QW}, - { 0, } -}; -MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); - - -typedef struct { - u16 reg; - u32 val; -} reg_val; - - -#define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0])) - -typedef struct { - u8 clock_chip_type; - u8 struct_size; - u8 accelerator_entry; - u8 VGA_entry; - u16 VGA_table_offset; - u16 POST_table_offset; - u16 XCLK; - u16 MCLK; - u8 num_PLL_blocks; - u8 size_PLL_blocks; - u16 PCLK_ref_freq; - u16 PCLK_ref_divider; - u32 PCLK_min_freq; - u32 PCLK_max_freq; - u16 MCLK_ref_freq; - u16 MCLK_ref_divider; - u32 MCLK_min_freq; - u32 MCLK_max_freq; - u16 XCLK_ref_freq; - u16 XCLK_ref_divider; - u32 XCLK_min_freq; - u32 XCLK_max_freq; -} __attribute__ ((packed)) PLL_BLOCK; - - -struct pll_info { - int ppll_max; - int ppll_min; - int xclk; - int ref_div; - int ref_clk; -}; - - -struct ram_info { - int ml; - int mb; - int trcd; - int trp; - int twr; - int cl; - int tr2w; - int loop_latency; - int rloop; -}; - - -struct radeon_regs { - /* Common registers */ - u32 ovr_clr; - u32 ovr_wid_left_right; - u32 ovr_wid_top_bottom; - u32 ov0_scale_cntl; - u32 mpp_tb_config; - u32 mpp_gp_config; - u32 subpic_cntl; - u32 i2c_cntl_1; - u32 gen_int_cntl; - u32 cap0_trig_cntl; - u32 cap1_trig_cntl; - u32 bus_cntl; - /* Other registers to save for VT switches */ - u32 dp_datatype; - u32 rbbm_soft_reset; - u32 clock_cntl_index; - u32 amcgpio_en_reg; - u32 amcgpio_mask; - /* CRTC registers */ - u32 crtc_gen_cntl; - u32 crtc_ext_cntl; - u32 dac_cntl; - u32 crtc_h_total_disp; - u32 crtc_h_sync_strt_wid; - u32 crtc_v_total_disp; - u32 crtc_v_sync_strt_wid; - u32 crtc_offset; - u32 crtc_offset_cntl; - u32 crtc_pitch; - /* CRTC2 registers */ - u32 crtc2_gen_cntl; - u32 dac2_cntl; - u32 disp_output_cntl; - u32 crtc2_h_total_disp; - u32 crtc2_h_sync_strt_wid; - u32 crtc2_v_total_disp; - u32 crtc2_v_sync_strt_wid; - u32 crtc2_offset; - u32 crtc2_offset_cntl; - u32 crtc2_pitch; - /* Flat panel registers */ - u32 fp_crtc_h_total_disp; - u32 fp_crtc_v_total_disp; - u32 fp_gen_cntl; - u32 fp_h_sync_strt_wid; - u32 fp_horz_stretch; - u32 fp_panel_cntl; - u32 fp_v_sync_strt_wid; - u32 fp_vert_stretch; - u32 lvds_gen_cntl; - u32 lvds_pll_cntl; - u32 tmds_crc; - /* DDA registers */ - u32 dda_config; - u32 dda_on_off; - - /* Computed values for PLL */ - u32 dot_clock_freq; - u32 pll_output_freq; - int feedback_div; - int post_div; - /* PLL registers */ - u32 ppll_ref_div; - u32 ppll_div_3; - u32 htotal_cntl; - /* Computed values for PLL2 */ - u32 dot_clock_freq_2; - u32 pll_output_freq_2; - int feedback_div_2; - int post_div_2; - /* PLL2 registers */ - u32 p2pll_ref_div; - u32 p2pll_div_0; - u32 htotal_cntl2; - /* Pallet */ - int palette_valid; - u32 palette[256]; - u32 palette2[256]; - - u32 flags; - u32 pix_clock; - int xres, yres; - int bpp; -#if defined(__BIG_ENDIAN) - u32 surface_cntl; -#endif -}; - - -struct radeonfb_info { - struct fb_info info; - - struct radeon_regs state; - struct radeon_regs init_state; - - char name[17]; - char ram_type[12]; - - int hasCRTC2; - int crtDispType; - int dviDispType; - int isM7; - int isM6; - int isR200; - /* Computed values for FPs */ - int PanelXRes; - int PanelYRes; - int HOverPlus; - int HSyncWidth; - int HBlank; - int VOverPlus; - int VSyncWidth; - int VBlank; - int PanelPwrDly; - - u32 mmio_base_phys; - u32 fb_base_phys; - - u32 mmio_base; - u32 fb_base; - - u32 MemCntl; - u32 BusCntl; - - struct pci_dev *pdev; - - struct display disp; - int currcon; - struct display *currcon_display; - - struct { u8 red, green, blue, pad; } palette[256]; - - int chipset; - int video_ram; - u8 rev; - int pitch, bpp, depth; - int xres, yres, pixclock; - - u32 dp_gui_master_cntl; - - struct pll_info pll; - int pll_output_freq, post_div, fb_div; - - struct ram_info ram; - -#ifdef CONFIG_MTRR - struct { int vram; int vram_valid; } mtrr; -#endif -#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32) - union { -#if defined(FBCON_HAS_CFB16) - u_int16_t cfb16[16]; -#endif -#if defined(FBCON_HAS_CFB24) - u_int32_t cfb24[16]; -#endif -#if defined(FBCON_HAS_CFB32) - u_int32_t cfb32[16]; -#endif - } con_cmap; -#endif -}; - -#define SINGLE_MONITOR(rinfo) (rinfo->crtDispType == MT_NONE || rinfo->dviDispType == MT_NONE) -/*#define DUAL_MONITOR(rinfo) (rinfo->crtDispType != MT_NONE && rinfo->dviDispType != MT_NONE)*/ -/* Disable DUAL monitor support for now */ -#define DUAL_MONITOR(rinfo) (0) -#define PRIMARY_MONITOR(rinfo) (rinfo->dviDispType != MT_NONE &&\ - rinfo->dviDispType != MT_STV &&\ - rinfo->dviDispType != MT_CTV ?\ - rinfo->dviDispType : rinfo->crtDispType) - -static struct fb_var_screeninfo radeonfb_default_var = { - 640, 480, 640, 480, 0, 0, 8, 0, - {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, - 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2, - 0, FB_VMODE_NONINTERLACED -}; - - -/* - * IO macros - */ - -#define INREG8(addr) readb((rinfo->mmio_base)+addr) -#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) -#define INREG(addr) readl((rinfo->mmio_base)+addr) -#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) - -#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ - OUTREG(CLOCK_CNTL_DATA, val) -#define OUTPLLP(addr,val,mask) \ - do { \ - unsigned int _tmp = INPLL(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTPLL(addr, _tmp); \ - } while (0) - -#define OUTREGP(addr,val,mask) \ - do { \ - unsigned int _tmp = INREG(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTREG(addr, _tmp); \ - } while (0) - - -static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr) -{ - OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); - return (INREG(CLOCK_CNTL_DATA)); -} - -#define INPLL(addr) _INPLL(rinfo, addr) - -static __inline__ u8 radeon_get_post_div_bitval(int post_div) -{ - switch (post_div) { - case 1: - return 0x00; - case 2: - return 0x01; - case 3: - return 0x04; - case 4: - return 0x02; - case 6: - return 0x06; - case 8: - return 0x03; - case 12: - return 0x07; - default: - return 0x02; - } -} - - - -static __inline__ int round_div(int num, int den) -{ - return (num + (den / 2)) / den; -} - - - -static __inline__ int min_bits_req(int val) -{ - int bits_req = 0; - - if (val == 0) - bits_req = 1; - - while (val) { - val >>= 1; - bits_req++; - } - - return (bits_req); -} - - -static __inline__ int _max(int val1, int val2) -{ - if (val1 >= val2) - return val1; - else - return val2; -} - - -/* - * 2D engine routines - */ - -static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo) -{ - int i; - - /* initiate flush */ - OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); - - for (i=0; i < 2000000; i++) { - if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) - break; - } -} - - -static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries) -{ - int i; - - for (i=0; i<2000000; i++) - if ((INREG(RBBM_STATUS) & 0x7f) >= entries) - return; -} - - -static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo) -{ - int i; - - /* ensure FIFO is empty before waiting for idle */ - _radeon_fifo_wait (rinfo, 64); - - for (i=0; i<2000000; i++) { - if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { - radeon_engine_flush (rinfo); - return; - } - } -} - - - -#define radeon_engine_idle() _radeon_engine_idle(rinfo) -#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) - - - -/* - * helper routines - */ - -static __inline__ u32 radeon_get_dstbpp(u16 depth) -{ - switch (depth) { - case 8: - return DST_8BPP; - case 15: - return DST_15BPP; - case 16: - return DST_16BPP; - case 24: - return DST_24BPP; - case 32: - return DST_32BPP; - default: - return 0; - } -} - - -static void _radeon_engine_reset(struct radeonfb_info *rinfo) -{ - u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; - - radeon_engine_flush (rinfo); - - clock_cntl_index = INREG(CLOCK_CNTL_INDEX); - mclk_cntl = INPLL(MCLK_CNTL); - - OUTPLL(MCLK_CNTL, (mclk_cntl | - FORCEON_MCLKA | - FORCEON_MCLKB | - FORCEON_YCLKA | - FORCEON_YCLKB | - FORCEON_MC | - FORCEON_AIC)); - rbbm_soft_reset = INREG(RBBM_SOFT_RESET); - - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | - SOFT_RESET_CP | - SOFT_RESET_HI | - SOFT_RESET_SE | - SOFT_RESET_RE | - SOFT_RESET_PP | - SOFT_RESET_E2 | - SOFT_RESET_RB | - SOFT_RESET_HDP); - INREG(RBBM_SOFT_RESET); - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32) - ~(SOFT_RESET_CP | - SOFT_RESET_HI | - SOFT_RESET_SE | - SOFT_RESET_RE | - SOFT_RESET_PP | - SOFT_RESET_E2 | - SOFT_RESET_RB | - SOFT_RESET_HDP)); - INREG(RBBM_SOFT_RESET); - - OUTPLL(MCLK_CNTL, mclk_cntl); - OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); - - return; -} - -#define radeon_engine_reset() _radeon_engine_reset(rinfo) - -/* - * globals - */ - -static char fontname[40] __initdata; -static char *mode_option __initdata; -static char noaccel __initdata = 0; -static int nomtrr __initdata = 0; -static int yres_panel __initdata = 0; -static char panel_yres __initdata = 0; - -#if 0 -#ifdef FBCON_HAS_CFB8 -static struct display_switch fbcon_radeon8; -#endif -#endif - -#ifdef CONFIG_MTRR -static int mtrr = 1; -#endif - -/* - * prototypes - */ - -static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con, - struct fb_info *info); -static int radeonfb_get_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -static int radeonfb_set_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info); -static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info); -static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg, int con, struct fb_info *info); -static int radeonfb_switch (int con, struct fb_info *info); -static int radeonfb_updatevar (int con, struct fb_info *info); -static void radeonfb_blank (int blank, struct fb_info *info); -static int radeon_get_cmap_len (const struct fb_var_screeninfo *var); -static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green, - unsigned *blue, unsigned *transp, - struct fb_info *info); -static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, struct fb_info *info); -static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp); -static void radeon_save_mode (struct radeonfb_info *rinfo, - struct radeon_regs *save); -static void radeon_save_state (struct radeonfb_info *rinfo, - struct radeon_regs *save); -static void radeon_engine_init (struct radeonfb_info *rinfo); -static int radeon_load_video_mode (struct radeonfb_info *rinfo, - struct fb_var_screeninfo *mode); -static void radeon_write_mode (struct radeonfb_info *rinfo, - struct radeon_regs *mode); -static void radeon_write_state (struct radeonfb_info *rinfo, - struct radeon_regs *mode); -static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo); -static int __devinit radeon_init_disp (struct radeonfb_info *rinfo); -static int radeon_init_disp_var (struct radeonfb_info *rinfo); -static int radeonfb_pci_register (struct pci_dev *pdev, - const struct pci_device_id *ent); -static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev); -static char *radeon_find_rom(struct radeonfb_info *rinfo); -static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg); -static void do_install_cmap(int con, struct fb_info *info); -static int radeonfb_do_maximize(struct radeonfb_info *rinfo, - struct fb_var_screeninfo *var, - struct fb_var_screeninfo *v, - int nom, int den); -#if defined(__powerpc__) -extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev); -#endif - -static struct fb_ops radeon_fb_ops = { - fb_get_fix: radeonfb_get_fix, - fb_get_var: radeonfb_get_var, - fb_set_var: radeonfb_set_var, - fb_get_cmap: radeonfb_get_cmap, - fb_set_cmap: radeonfb_set_cmap, - fb_pan_display: radeonfb_pan_display, - fb_ioctl: radeonfb_ioctl, -}; - - -static struct pci_driver radeonfb_driver = { - name: "radeonfb", - id_table: radeonfb_pci_table, - probe: radeonfb_pci_register, - remove: radeonfb_pci_unregister, -}; - -static void _radeon_wait_for_idle(struct radeonfb_info *rinfo); -/* Restore the acceleration hardware to its previous state. */ -static void _radeon_engine_restore(struct radeonfb_info *rinfo) -{ - int pitch64; - - radeon_fifo_wait(1); - /* turn of all automatic flushing - we'll do it all */ - OUTREG(RB2D_DSTCACHE_MODE, 0); - - pitch64 = ((rinfo->xres * (rinfo->bpp / 8) + 0x3f)) >> 6; - - radeon_fifo_wait(1); - OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | - (pitch64 << 22)); - - radeon_fifo_wait(1); -#if defined(__BIG_ENDIAN) - OUTREGP(DP_DATATYPE, - HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); -#else - OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); -#endif - - radeon_fifo_wait(1); - OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX - | DEFAULT_SC_BOTTOM_MAX)); - radeon_fifo_wait(1); - OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) - | GMC_BRUSH_SOLID_COLOR - | GMC_SRC_DATATYPE_COLOR)); - - radeon_fifo_wait(7); - OUTREG(DST_LINE_START, 0); - OUTREG(DST_LINE_END, 0); - OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); - OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); - OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); - OUTREG(DP_SRC_BKGD_CLR, 0x00000000); - OUTREG(DP_WRITE_MASK, 0xffffffff); - - _radeon_wait_for_idle(rinfo); -} - -/* The FIFO has 64 slots. This routines waits until at least `entries' of - these slots are empty. */ -#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ -static void _radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int entries) -{ - int i; - - for (;;) { - for (i = 0; i < RADEON_TIMEOUT; i++) { - if((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) return; - } - radeon_engine_reset(); - _radeon_engine_restore(rinfo); - /* it might be that DRI has been compiled in, but corresponding - library was not loaded.. */ - } -} -/* Wait for the graphics engine to be completely idle: the FIFO has - drained, the Pixel Cache is flushed, and the engine is idle. This is a - standard "sync" function that will make the hardware "quiescent". */ -static void _radeon_wait_for_idle(struct radeonfb_info *rinfo) -{ - int i; - - _radeon_wait_for_fifo_function(rinfo, 64); - - for (;;) { - for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(RBBM_STATUS) & RBBM_ACTIVE)) { - radeon_engine_flush(rinfo); - return; - } - } - _radeon_engine_reset(rinfo); - _radeon_engine_restore(rinfo); - } -} - -int __init radeonfb_init (void) -{ -#ifdef CONFIG_MTRR - if (nomtrr) { - mtrr = 0; - printk("radeonfb: Parameter NOMTRR set\n"); - } -#endif - if (yres_panel) panel_yres = yres_panel; - return pci_module_init (&radeonfb_driver); -} - - -void __exit radeonfb_exit (void) -{ - pci_unregister_driver (&radeonfb_driver); -} - - -int __init radeonfb_setup (char *options) -{ - char *this_opt; - - if (!options || !*options) - return 0; - - while ((this_opt = strsep (&options, ",")) != NULL) { - if (!*this_opt) - continue; - if (!strncmp (this_opt, "font:", 5)) { - char *p; - int i; - - p = this_opt + 5; - for (i=0; i<sizeof (fontname) - 1; i++) - if (!*p || *p == ' ' || *p == ',') - break; - memcpy(fontname, this_opt + 5, i); - } else if (!strncmp(this_opt, "noaccel", 7)) { - noaccel = 1; - } -#ifdef CONFIG_MTRR - else if(!strncmp(this_opt, "nomtrr", 6)) { - mtrr = 0; - } -#endif - else if (!strncmp(this_opt, "panel_yres:", 11)) { - panel_yres = simple_strtoul((this_opt+11), NULL, 0); - } else - mode_option = this_opt; - } - - return 0; -} - -#ifdef MODULE -module_init(radeonfb_init); -module_exit(radeonfb_exit); -#endif - -static char * GET_MON_NAME(int type) -{ - char *pret; - switch(type) - { - case MT_NONE: pret = "no"; break; - case MT_CRT: pret = "CRT"; break; - case MT_DFP: pret = "DFP"; break; - case MT_LCD: pret = "LCD"; break; - case MT_CTV: pret = "CTV"; break; - case MT_STV: pret = "STV"; break; - default: pret = "Unknown"; - } - return pret; -} - -/*This funtion is used to reverse calculate - panel information from register settings in VGA mode. - More graceful way is to use EDID information... if it can be detected. - This way may be better than directly probing BIOS image. Because - BIOS image could change from version to version, while the - registers should always(?) contain right information, otherwise - the VGA mode display will not be correct. Well, if someone - messes up these registers before our driver is loaded, we'll be in - trouble...*/ -static int radeon_get_dfp_info(struct radeonfb_info *rinfo) -{ - unsigned long r; - unsigned short a, b; - - if (panel_yres) { - rinfo->PanelYRes = panel_yres; - } else { - r = INREG(FP_VERT_STRETCH); - r &= 0x00fff000; - rinfo->PanelYRes = (unsigned short)(r >> 0x0c) + 1; - } - switch(rinfo->PanelYRes) - { - case 480: rinfo->PanelXRes = 640; - break; - case 600: rinfo->PanelXRes = 800; - break; - case 768: rinfo->PanelXRes = 1024; - break; - case 1024: rinfo->PanelXRes = 1280; - break; - case 1050: rinfo->PanelXRes = 1400; - break; - case 1200: rinfo->PanelXRes = 1600; - break; - default: - printk("radeonfb: Failed to detect the DFP panel size.\n"); - return 0; - - } - - printk("Detected DFP panel size: %dx%d\n", rinfo->PanelXRes, rinfo->PanelYRes); - - r = INREG(FP_CRTC_H_TOTAL_DISP); - a = (r & FP_CRTC_H_TOTAL_MASK) + 4; - b = (r & 0x01FF0000) >> FP_CRTC_H_DISP_SHIFT; - rinfo->HBlank = (a - b + 1) * 8; - - r = INREG(FP_H_SYNC_STRT_WID); - rinfo->HOverPlus = - (unsigned short)((r & FP_H_SYNC_STRT_CHAR_MASK) - >> FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1; - rinfo->HOverPlus *= 8; - rinfo->HSyncWidth = - (unsigned short)((r & FP_H_SYNC_WID_MASK) - >> FP_H_SYNC_WID_SHIFT); - rinfo->HSyncWidth *= 8; - r = INREG(FP_CRTC_V_TOTAL_DISP); - a = (r & FP_CRTC_V_TOTAL_MASK) + 1; - b = (r & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT; - rinfo->VBlank = a - b /*+ 24*/; - - r = INREG(FP_V_SYNC_STRT_WID); - rinfo->VOverPlus = (unsigned short)(r & FP_V_SYNC_STRT_MASK) - - b + 1; - rinfo->VSyncWidth = (unsigned short)((r & FP_V_SYNC_WID_MASK) - >> FP_V_SYNC_WID_SHIFT); - - return 1; -} - -static void radeon_get_moninfo (struct radeonfb_info *rinfo) -{ - unsigned int tmp; - - tmp = INREG(RADEON_BIOS_4_SCRATCH); - - if (rinfo->hasCRTC2) { - /* primary DVI port */ - if (tmp & 0x08) - rinfo->dviDispType = MT_DFP; - else if (tmp & 0x4) - rinfo->dviDispType = MT_LCD; - else if (tmp & 0x200) - rinfo->dviDispType = MT_CRT; - else if (tmp & 0x10) - rinfo->dviDispType = MT_CTV; - else if (tmp & 0x20) - rinfo->dviDispType = MT_STV; - - /* secondary CRT port */ - if (tmp & 0x2) - rinfo->crtDispType = MT_CRT; - else if (tmp & 0x800) - rinfo->crtDispType = MT_DFP; - else if (tmp & 0x400) - rinfo->crtDispType = MT_LCD; - else if (tmp & 0x1000) - rinfo->crtDispType = MT_CTV; - else if (tmp & 0x2000) - rinfo->crtDispType = MT_STV; - } else { - rinfo->dviDispType = MT_NONE; - - tmp = INREG(FP_GEN_CNTL); - - if (tmp & FP_EN_TMDS) - rinfo->crtDispType = MT_DFP; - else - rinfo->crtDispType = MT_CRT; - } -} - -static int radeonfb_pci_register (struct pci_dev *pdev, - const struct pci_device_id *ent) -{ - struct radeonfb_info *rinfo; - u32 tmp; - int i, j; - char *bios_seg = NULL; - - rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL); - if (!rinfo) { - printk ("radeonfb: could not allocate memory\n"); - return -ENODEV; - } - - memset (rinfo, 0, sizeof (struct radeonfb_info)); - - rinfo->pdev = pdev; - - /* enable device */ - { - int err; - - if ((err = pci_enable_device(pdev))) { - printk("radeonfb: cannot enable device\n"); - kfree (rinfo); - return -ENODEV; - } - } - - /* set base addrs */ - rinfo->fb_base_phys = pci_resource_start (pdev, 0); - rinfo->mmio_base_phys = pci_resource_start (pdev, 2); - - /* request the mem regions */ - if (!request_mem_region (rinfo->fb_base_phys, - pci_resource_len(pdev, 0), "radeonfb")) { - printk ("radeonfb: cannot reserve FB region\n"); - kfree (rinfo); - return -ENODEV; - } - - if (!request_mem_region (rinfo->mmio_base_phys, - pci_resource_len(pdev, 2), "radeonfb")) { - printk ("radeonfb: cannot reserve MMIO region\n"); - release_mem_region (rinfo->fb_base_phys, - pci_resource_len(pdev, 0)); - kfree (rinfo); - return -ENODEV; - } - - /* map the regions */ - rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys, - RADEON_REGSIZE); - if (!rinfo->mmio_base) { - printk ("radeonfb: cannot map MMIO\n"); - release_mem_region (rinfo->mmio_base_phys, - pci_resource_len(pdev, 2)); - release_mem_region (rinfo->fb_base_phys, - pci_resource_len(pdev, 0)); - kfree (rinfo); - return -ENODEV; - } - - rinfo->chipset = pdev->device; - - /* chipset */ - switch (pdev->device) { - case PCI_DEVICE_ID_RADEON_QD: - strcpy(rinfo->name, "Radeon QD "); - break; - case PCI_DEVICE_ID_RADEON_QE: - strcpy(rinfo->name, "Radeon QE "); - break; - case PCI_DEVICE_ID_RADEON_QF: - strcpy(rinfo->name, "Radeon QF "); - break; - case PCI_DEVICE_ID_RADEON_QG: - strcpy(rinfo->name, "Radeon QG "); - break; - case PCI_DEVICE_ID_RADEON_QY: - rinfo->hasCRTC2 = 1; - strcpy(rinfo->name, "Radeon VE QY "); - break; - case PCI_DEVICE_ID_RADEON_QZ: - rinfo->hasCRTC2 = 1; - strcpy(rinfo->name, "Radeon VE QZ "); - break; - case PCI_DEVICE_ID_RADEON_LY: - rinfo->hasCRTC2 = 1; - rinfo->isM6 = 1; - strcpy(rinfo->name, "Radeon M6 LY "); - break; - case PCI_DEVICE_ID_RADEON_LZ: - rinfo->hasCRTC2 = 1; - rinfo->isM6 = 1; - strcpy(rinfo->name, "Radeon M6 LZ "); - break; - case PCI_DEVICE_ID_RADEON_LW: -/* Note: Only difference between VE,M6 and M7 is initialization CRTC2 - registers in dual monitor configuration!!! */ - rinfo->hasCRTC2 = 1; - rinfo->isM7 = 1; - strcpy(rinfo->name, "Radeon M7 LW "); - break; - case PCI_DEVICE_ID_R200_QL: - rinfo->hasCRTC2 = 1; - rinfo->isR200 = 1; - strcpy(rinfo->name, "Radeon2 8500 QL "); - break; - case PCI_DEVICE_ID_R200_BB: - rinfo->hasCRTC2 = 1; - rinfo->isR200 = 1; - strcpy(rinfo->name, "Radeon2 8500 AIW"); - break; - case PCI_DEVICE_ID_RV200_QW: - rinfo->hasCRTC2 = 1; - rinfo->isM7 = 1; - strcpy(rinfo->name, "Radeon2 7500 QW "); - break; - default: - release_mem_region (rinfo->mmio_base_phys, |